Lines Matching +full:pruss +full:- +full:mii
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2023 Josua Mayer <josua@solid-run.com>
7 #include <dt-bindings/net/ti-dp83869.h>
11 compatible = "solidrun,am642-sr-som", "ti,am642";
24 stdout-path = "serial2:115200n8";
29 compatible = "ti,am642-icssg-prueth";
30 pinctrl-names = "default";
31 pinctrl-0 = <&pru_rgmii1_default_pins>, <&pru_rgmii2_default_pins>;
35 firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
36 "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
37 "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
38 "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
39 "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
40 "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
42 /* configure internal pinmux for mii mode */
43 ti,pruss-gp-mux-sel = <2>, <2>, <2>, <2>, <2>, <2>;
45 ti,mii-g-rt = <&icssg1_mii_g_rt>;
46 ti,mii-rt = <&icssg1_mii_rt>;
50 * Configure icssg interrupt controller to map pru-internal
54 * Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml
56 interrupt-parent = <&icssg1_intc>;
58 interrupt-names = "tx_ts0", "tx_ts1";
70 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
71 "tx1-0", "tx1-1", "tx1-2", "tx1-3",
74 ethernet-ports {
75 #address-cells = <1>;
76 #size-cells = <0>;
80 ti,syscon-rgmii-delay = <&main_conf 0x4110>;
82 local-mac-address = [00 00 00 00 00 00];
83 phy-handle = <ðernet_phy2>;
84 phy-mode = "rgmii-id";
89 ti,syscon-rgmii-delay = <&main_conf 0x4114>;
91 local-mac-address = [00 00 00 00 00 00];
92 phy-handle = <ðernet_phy1>;
93 phy-mode = "rgmii-id";
99 * - Bank 1 @ 0x080000000-0x0FFFFFFFF: max. 2GB in 32-bit address space
100 * - Bank 2 @ 0x880000000-0x9FFFFFFFF: max. 6GB in 64-bit address space
108 reserved-memory {
109 #address-cells = <2>;
110 #size-cells = <2>;
114 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
115 no-map;
118 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
119 compatible = "shared-dma-pool";
121 no-map;
124 main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
125 compatible = "shared-dma-pool";
127 no-map;
130 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
131 compatible = "shared-dma-pool";
133 no-map;
136 main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
137 compatible = "shared-dma-pool";
139 no-map;
142 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
143 compatible = "shared-dma-pool";
145 no-map;
148 main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
149 compatible = "shared-dma-pool";
151 no-map;
154 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
155 compatible = "shared-dma-pool";
157 no-map;
160 main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
161 compatible = "shared-dma-pool";
163 no-map;
167 vdd_mmc0: regulator-vdd-mmc0 {
168 compatible = "regulator-fixed";
169 regulator-name = "vdd-mmc0";
170 regulator-min-microvolt = <1800000>;
171 regulator-max-microvolt = <1800000>;
172 regulator-always-on;
173 regulator-boot-on;
178 pinctrl-names = "default";
179 pinctrl-0 = <&rgmii1_default_pins>;
184 pinctrl-names = "default";
185 pinctrl-0 = <&mdio0_default_pins>;
188 ethernet_phy0: ethernet-phy@0 {
189 compatible = "ethernet-phy-id2000.a0f1";
191 pinctrl-names = "default";
192 pinctrl-0 = <ðernet_phy0_default_pins>;
193 ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
194 ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;
198 * interrupt-parent = <&main_gpio1>;
202 * Disable HW Reset because clock signal is daisy-chained
204 * reset-gpios = <&main_gpio0 84 GPIO_ACTIVE_LOW>;
205 * reset-assert-us = <1>;
206 * reset-deassert-us = <30>;
212 phy-mode = "rgmii-id";
213 phy-handle = <ðernet_phy0>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&pru1_mdio0_default_pins>;
222 ethernet_phy1: ethernet-phy@3 {
223 compatible = "ethernet-phy-id2000.a0f1";
225 pinctrl-names = "default";
226 pinctrl-0 = <ðernet_phy1_default_pins>;
227 ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
228 ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;
232 * interrupt-parent = <&main_gpio1>;
236 * Disable HW Reset because clock signal is daisy-chained
238 * reset-gpios = <&main_gpio0 20 GPIO_ACTIVE_LOW>;
239 * reset-assert-us = <1>;
240 * reset-deassert-us = <30>;
244 ethernet_phy2: ethernet-phy@f {
245 compatible = "ethernet-phy-id2000.a0f1";
247 pinctrl-names = "default";
248 pinctrl-0 = <ðernet_phy2_default_pins>;
249 ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;
253 * interrupt-parent = <&main_gpio1>;
257 * Disable HW Reset because clock signal is daisy-chained
259 * reset-gpios = <&main_gpio0 52 GPIO_ACTIVE_LOW>;
260 * reset-assert-us = <1>;
261 * reset-deassert-us = <30>;
269 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
270 ti,mbox-rx = <0 0 2>;
271 ti,mbox-tx = <1 0 2>;
274 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
275 ti,mbox-rx = <2 0 2>;
276 ti,mbox-tx = <3 0 2>;
283 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
284 ti,mbox-rx = <0 0 2>;
285 ti,mbox-tx = <1 0 2>;
288 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
289 ti,mbox-rx = <2 0 2>;
290 ti,mbox-tx = <3 0 2>;
295 pinctrl-names = "default";
296 pinctrl-0 = <&main_i2c0_default_pins>;
308 pinctrl-names = "default";
309 pinctrl-0 = <ðernet_phy_default_pins>;
311 ethernet_phy_default_pins: ethernet-phy-default-pins {
312 pinctrl-single,pins = <
313 /* interrupt / power-down, external pull-up on SoM */
318 ethernet_phy0_default_pins: ethernet-phy0-default-pins {
319 pinctrl-single,pins = <
327 ethernet_phy1_default_pins: ethernet-phy1-default-pins {
328 pinctrl-single,pins = <
331 /* led0, external pull-down on SoM */
338 ethernet_phy2_default_pins: ethernet-phy2-default-pins {
339 pinctrl-single,pins = <
342 /* led0, external pull-down on SoM */
349 main_i2c0_default_pins: main-i2c0-default-pins {
350 pinctrl-single,pins = <
351 /* external pull-up on SoM */
358 * main_mmc0_default_pins: main-mmc0-default-pins
361 * MMC0_CLK: no padconfig, external pull-up on SoM
370 * MMC0_DS: no padconfig, external pull-down on SoM
373 main_mmc1_default_pins: main-mmc1-default-pins {
374 pinctrl-single,pins = <
381 /* external pull-down on SoM & Carrier */
387 main_uart0_default_pins: main-uart0-default-pins {
388 pinctrl-single,pins = <
394 mdio0_default_pins: mdio0-default-pins {
395 pinctrl-single,pins = <
401 ospi0_default_pins: ospi0-default-pins {
402 pinctrl-single,pins = <
403 /* external pull-down on SoM */
406 /* external pull-up on SoM */
419 ospi0_flash0_default_pins: ospi0-flash0-default-pins {
420 pinctrl-single,pins = <
426 pru1_mdio0_default_pins: pru1-mdio0-default-pins {
427 pinctrl-single,pins = <
433 pru_rgmii1_default_pins: pru-rgmii1-default-pins {
434 pinctrl-single,pins = <
450 pru_rgmii2_default_pins: pru-rgmii2-default-pins {
451 pinctrl-single,pins = <
467 rgmii1_default_pins: rgmii1-default-pins {
468 pinctrl-single,pins = <
484 usb0_default_pins: usb0-default-pins {
485 pinctrl-single,pins = <
493 memory-region = <&main_r5fss0_core0_dma_memory_region>,
499 memory-region = <&main_r5fss0_core1_dma_memory_region>,
505 memory-region = <&main_r5fss1_core0_dma_memory_region>,
511 memory-region = <&main_r5fss1_core1_dma_memory_region>,
517 pinctrl-names = "default";
518 pinctrl-0 = <&main_uart0_default_pins>;
523 pinctrl-names = "default";
524 pinctrl-0 = <&ospi0_default_pins>;
525 num-cs = <1>;
529 compatible = "jedec,spi-nor";
531 pinctrl-names = "default";
532 pinctrl-0 = <&ospi0_flash0_default_pins>;
533 spi-tx-bus-width = <8>;
534 spi-rx-bus-width = <8>;
535 spi-max-frequency = <200000000>;
536 cdns,tshsl-ns = <50>;
537 cdns,tsd2d-ns = <50>;
538 cdns,tchsh-ns = <4>;
539 cdns,tslch-ns = <4>;
540 cdns,read-delay = <0>;
541 interrupt-parent = <&main_gpio0>;
543 reset-gpios = <&main_gpio0 13 GPIO_ACTIVE_LOW>;
549 bus-width = <8>;
550 ti,driver-strength-ohm = <50>;
551 disable-wp;
552 non-removable;
553 cap-mmc-hw-reset;
554 no-sd;
561 vqmmc-supply = <&vdd_mmc0>;
566 * microSD is on carrier - however since SoC can boot from it,
570 pinctrl-names = "default";
571 pinctrl-0 = <&main_mmc1_default_pins>;
572 bus-width = <4>;
573 ti,driver-strength-ohm = <50>;
574 disable-wp;
579 * USB settings are a carrier choice - however since SoC can boot from it,
580 * configure as USB-2.0 OTG here, keeping USB-3 serdes disabled.
583 pinctrl-names = "default";
584 pinctrl-0 = <&usb0_default_pins>;
586 maximum-speed = "high-speed";
590 ti,vbus-divider;
591 ti,usb2-only;