Lines Matching +full:mii +full:- +full:g +full:- +full:rt
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2021-2024 PHYTEC America, LLC - https://www.phytec.com
6 * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH
10 * https://www.phytec.com/product/phyboard-am64x
13 /dts-v1/;
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/leds/common.h>
18 #include <dt-bindings/leds/leds-pca9532.h>
19 #include <dt-bindings/phy/phy.h>
20 #include "k3-am642.dtsi"
21 #include "k3-am64-phycore-som.dtsi"
23 #include "k3-serdes.h"
26 compatible = "phytec,am642-phyboard-electra-rdk",
27 "phytec,am64-phycore-som", "ti,am642";
28 model = "PHYTEC phyBOARD-Electra-AM64x RDK";
39 stdout-path = &main_uart0;
42 can_tc1: can-phy0 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&can_tc1_pins_default>;
46 #phy-cells = <0>;
47 max-bitrate = <8000000>;
48 standby-gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>;
51 can_tc2: can-phy1 {
53 pinctrl-names = "default";
54 pinctrl-0 = <&can_tc2_pins_default>;
55 #phy-cells = <0>;
56 max-bitrate = <8000000>;
57 standby-gpios = <&main_gpio0 35 GPIO_ACTIVE_HIGH>;
60 /* Dual Ethernet application node on PRU-ICSSG0 */
62 compatible = "ti,am642-icssg-prueth";
63 pinctrl-names = "default";
64 pinctrl-0 = <&icssg0_rgmii1_pins_default>, <&icssg0_rgmii2_pins_default>;
66 interrupt-parent = <&icssg0_intc>;
68 interrupt-names = "tx_ts0", "tx_ts1";
71 firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
72 "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
73 "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
74 "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
75 "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
76 "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
88 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
89 "tx1-0", "tx1-1", "tx1-2", "tx1-3",
93 ti,pruss-gp-mux-sel = <2>, /* MII mode */
96 <2>, /* MII mode */
100 ti,mii-g-rt = <&icssg0_mii_g_rt>;
101 ti,mii-rt = <&icssg0_mii_rt>;
104 ethernet-ports {
105 #address-cells = <1>;
106 #size-cells = <0>;
109 phy-handle = <&icssg0_phy1>;
110 phy-mode = "rgmii-id";
112 local-mac-address = [00 00 00 00 00 00];
113 ti,syscon-rgmii-delay = <&main_conf 0x4100>;
118 phy-handle = <&icssg0_phy2>;
119 phy-mode = "rgmii-id";
121 local-mac-address = [00 00 00 00 00 00];
122 ti,syscon-rgmii-delay = <&main_conf 0x4104>;
128 compatible = "gpio-keys";
130 pinctrl-names = "default";
131 pinctrl-0 = <&gpio_keys_pins_default>;
133 key-home {
139 key-menu {
147 compatible = "gpio-leds";
148 pinctrl-names = "default";
149 pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>;
151 led-1 {
154 linux,default-trigger = "mmc0";
158 led-2 {
161 linux,default-trigger = "mmc1";
166 vcc_3v3_mmc: regulator-sd {
168 compatible = "regulator-fixed";
169 regulator-name = "VCC_3V3_MMC";
170 regulator-min-microvolt = <3300000>;
171 regulator-max-microvolt = <3300000>;
172 regulator-boot-on;
173 regulator-always-on;
174 bootph-all;
179 can_tc1_pins_default: can-tc1-default-pins {
180 pinctrl-single,pins = <
185 can_tc2_pins_default: can-tc2-default-pins {
186 pinctrl-single,pins = <
191 clkout0_pins_default: clkout0-default-pins {
192 pinctrl-single,pins = <
197 gpio_keys_pins_default: gpio-keys-default-pins {
198 pinctrl-single,pins = <
204 icssg0_mdio_pins_default: icssg0-mdio-default-pins {
205 pinctrl-single,pins = <
213 icssg0_rgmii1_pins_default: icssg0-rgmii1-default-pins {
214 pinctrl-single,pins = <
230 icssg0_rgmii2_pins_default: icssg0-rgmii2-default-pins {
231 pinctrl-single,pins = <
247 main_i2c1_pins_default: main-i2c1-default-pins {
248 pinctrl-single,pins = <
254 main_mcan0_pins_default: main-mcan0-default-pins {
255 pinctrl-single,pins = <
261 main_mcan1_pins_default: main-mcan1-default-pins {
262 pinctrl-single,pins = <
268 main_mmc1_pins_default: main-mmc1-default-pins {
269 pinctrl-single,pins = <
279 bootph-all;
282 main_spi0_pins_default: main-spi0-default-pins {
283 pinctrl-single,pins = <
291 main_uart0_pins_default: main-uart0-default-pins {
292 pinctrl-single,pins = <
296 bootph-all;
299 main_uart1_pins_default: main-uart1-default-pins {
300 pinctrl-single,pins = <
308 main_usb0_pins_default: main-usb0-default-pins {
309 pinctrl-single,pins = <
314 user_leds_pins_default: user-leds-default-pins {
315 pinctrl-single,pins = <
323 pinctrl-names = "default";
324 pinctrl-0 = <&icssg0_mdio_pins_default &clkout0_pins_default>;
325 assigned-clocks = <&k3_clks 157 123>;
326 assigned-clock-parents = <&k3_clks 157 125>;
329 icssg0_phy1: ethernet-phy@1 {
330 compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
332 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
333 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
334 reset-gpios = <&main_gpio1 18 GPIO_ACTIVE_LOW>;
335 reset-assert-us = <1000>;
336 reset-deassert-us = <1000>;
337 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
340 icssg0_phy2: ethernet-phy@2 {
341 compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
343 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
344 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
345 reset-gpios = <&main_gpio1 19 GPIO_ACTIVE_LOW>;
346 reset-assert-us = <1000>;
347 reset-deassert-us = <1000>;
348 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
353 trickle-resistor-ohms = <3000>;
357 pinctrl-names = "default";
358 pinctrl-0 = <&main_i2c1_pins_default>;
359 clock-frequency = <400000>;
368 led-controller@62 {
372 led-3 {
377 led-4 {
382 led-5 {
390 pinctrl-names = "default";
391 pinctrl-0 = <&main_mcan0_pins_default>;
397 pinctrl-names = "default";
398 pinctrl-0 = <&main_mcan1_pins_default>;
404 pinctrl-names = "default";
405 pinctrl-0 = <&main_spi0_pins_default>;
406 cs-gpios = <0>, <&main_gpio1 43 GPIO_ACTIVE_LOW>;
407 ti,pindir-d0-out-d1-in;
411 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
413 spi-max-frequency = <10000000>;
418 pinctrl-names = "default";
419 pinctrl-0 = <&main_uart0_pins_default>;
420 bootph-all;
425 pinctrl-names = "default";
426 pinctrl-0 = <&main_uart1_pins_default>;
427 uart-has-rtscts;
432 vmmc-supply = <&vcc_3v3_mmc>;
433 pinctrl-names = "default";
434 pinctrl-0 = <&main_mmc1_pins_default>;
435 disable-wp;
436 no-1-8-v;
437 bootph-all;
444 cdns,num-lanes = <1>;
445 #phy-cells = <0>;
446 cdns,phy-type = <PHY_TYPE_USB3>;
452 idle-states = <AM64_SERDES0_LANE0_USB>;
456 ti,vbus-divider;
460 pinctrl-names = "default";
461 pinctrl-0 = <&main_usb0_pins_default>;
463 maximum-speed = "super-speed";
465 phy-names = "cdns3,usb3-phy";