Lines Matching +full:usb +full:- +full:plugin
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * DT overlay for PCIe support (limits USB to 2.0/high-speed)
5 * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
8 * Copyright (C) 2024 PHYTEC America, LLC - https://www.phytec.com
12 /dts-v1/;
13 /plugin/;
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
17 #include <dt-bindings/phy/phy-cadence.h>
19 #include "k3-pinctrl.h"
20 #include "k3-serdes.h"
23 pcie_refclk0: pcie-refclk0 {
24 compatible = "gpio-gate-clock";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pcie_usb_sel_pins_default>;
28 #clock-cells = <0>;
29 enable-gpios = <&main_gpio1 7 GPIO_ACTIVE_HIGH>;
34 pcie_usb_sel_pins_default: pcie-usb-sel-default-pins {
35 pinctrl-single,pins = <
40 pcie_pins_default: pcie-default-pins {
41 pinctrl-single,pins = <
48 pinctrl-names = "default";
49 pinctrl-0 = <&pcie_pins_default>;
50 reset-gpios = <&main_gpio0 37 GPIO_ACTIVE_HIGH>;
52 phy-names = "pcie-phy";
53 num-lanes = <1>;
58 cdns,phy-type = <PHY_TYPE_PCIE>;
62 idle-states = <AM64_SERDES0_LANE0_PCIE0>;
66 assigned-clock-parents = <&pcie_refclk0>, <&pcie_refclk0>, <&pcie_refclk0>;
70 clock-frequency = <100000000>;
82 ti,usb2-only;
86 maximum-speed = "high-speed";