Lines Matching +full:regulator +full:- +full:v6
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include "k3-am642.dtsi"
14 #include "k3-serdes.h"
17 compatible = "ti,am642-evm", "ti,am642";
21 stdout-path = &main_uart0;
39 bootph-all;
45 reserved-memory {
46 #address-cells = <2>;
47 #size-cells = <2>;
51 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
53 no-map;
56 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
57 compatible = "shared-dma-pool";
59 no-map;
62 main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
63 compatible = "shared-dma-pool";
65 no-map;
68 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
69 compatible = "shared-dma-pool";
71 no-map;
74 main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
75 compatible = "shared-dma-pool";
77 no-map;
80 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
81 compatible = "shared-dma-pool";
83 no-map;
86 main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
87 compatible = "shared-dma-pool";
89 no-map;
92 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
93 compatible = "shared-dma-pool";
95 no-map;
98 main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
99 compatible = "shared-dma-pool";
101 no-map;
104 mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
105 compatible = "shared-dma-pool";
107 no-map;
110 mcu_m4fss_memory_region: m4f-memory@a4100000 {
111 compatible = "shared-dma-pool";
113 no-map;
116 rtos_ipc_memory_region: ipc-memories@a5000000 {
119 no-map;
123 evm_12v0: regulator-0 {
125 bootph-all;
126 compatible = "regulator-fixed";
127 regulator-name = "evm_12v0";
128 regulator-min-microvolt = <12000000>;
129 regulator-max-microvolt = <12000000>;
130 regulator-always-on;
131 regulator-boot-on;
134 vsys_5v0: regulator-1 {
136 compatible = "regulator-fixed";
137 regulator-name = "vsys_5v0";
138 regulator-min-microvolt = <5000000>;
139 regulator-max-microvolt = <5000000>;
140 vin-supply = <&evm_12v0>;
141 regulator-always-on;
142 regulator-boot-on;
145 vsys_3v3: regulator-2 {
147 bootph-all;
148 compatible = "regulator-fixed";
149 regulator-name = "vsys_3v3";
150 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <3300000>;
152 vin-supply = <&evm_12v0>;
153 regulator-always-on;
154 regulator-boot-on;
157 vdd_mmc1: regulator-3 {
159 bootph-all;
160 compatible = "regulator-fixed";
161 regulator-name = "vdd_mmc1";
162 regulator-min-microvolt = <3300000>;
163 regulator-max-microvolt = <3300000>;
164 regulator-boot-on;
165 enable-active-high;
166 vin-supply = <&vsys_3v3>;
170 vddb: regulator-4 {
171 compatible = "regulator-fixed";
172 regulator-name = "vddb_3v3_display";
173 regulator-min-microvolt = <3300000>;
174 regulator-max-microvolt = <3300000>;
175 vin-supply = <&vsys_3v3>;
176 regulator-always-on;
177 regulator-boot-on;
180 vtt_supply: regulator-5 {
181 bootph-all;
182 compatible = "regulator-fixed";
183 regulator-name = "vtt";
184 pinctrl-names = "default";
185 pinctrl-0 = <&ddr_vtt_pins_default>;
186 regulator-min-microvolt = <3300000>;
187 regulator-max-microvolt = <3300000>;
189 vin-supply = <&vsys_3v3>;
190 enable-active-high;
191 regulator-always-on;
192 regulator-boot-on;
196 compatible = "gpio-leds";
198 led-0 {
199 label = "am64-evm:red:heartbeat";
201 linux,default-trigger = "heartbeat";
203 default-state = "off";
207 mdio_mux: mux-controller {
208 compatible = "gpio-mux";
209 #mux-control-cells = <0>;
211 mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
214 mdio_mux_1: mdio-mux-1 {
215 compatible = "mdio-mux-multiplexer";
216 mux-controls = <&mdio_mux>;
217 mdio-parent-bus = <&cpsw3g_mdio>;
218 #address-cells = <1>;
219 #size-cells = <0>;
223 #address-cells = <1>;
224 #size-cells = <0>;
226 cpsw3g_phy3: ethernet-phy@3 {
232 transceiver1: can-phy0 {
234 #phy-cells = <0>;
235 max-bitrate = <5000000>;
236 standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>;
239 transceiver2: can-phy1 {
241 #phy-cells = <0>;
242 max-bitrate = <5000000>;
243 standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>;
246 icssg1_eth: icssg1-eth {
247 compatible = "ti,am642-icssg-prueth";
248 pinctrl-names = "default";
249 pinctrl-0 = <&icssg1_rgmii1_pins_default>;
252 firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf",
253 "ti-pruss/am64x-sr2-rtu0-prueth-fw.elf",
254 "ti-pruss/am64x-sr2-txpru0-prueth-fw.elf",
255 "ti-pruss/am64x-sr2-pru1-prueth-fw.elf",
256 "ti-pruss/am64x-sr2-rtu1-prueth-fw.elf",
257 "ti-pruss/am64x-sr2-txpru1-prueth-fw.elf";
259 ti,pruss-gp-mux-sel = <2>, /* MII mode */
265 ti,mii-g-rt = <&icssg1_mii_g_rt>;
266 ti,mii-rt = <&icssg1_mii_rt>;
268 ti,pa-stats = <&icssg1_pa_stats>;
269 interrupt-parent = <&icssg1_intc>;
271 interrupt-names = "tx_ts0", "tx_ts1";
282 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
283 "tx1-0", "tx1-1", "tx1-2", "tx1-3",
286 ethernet-ports {
287 #address-cells = <1>;
288 #size-cells = <0>;
291 phy-handle = <&icssg1_phy1>;
292 phy-mode = "rgmii-id";
294 local-mac-address = [00 00 00 00 00 00];
299 local-mac-address = [00 00 00 00 00 00];
307 main_mmc1_pins_default: main-mmc1-default-pins {
308 pinctrl-single,pins = <
321 main_uart1_pins_default: main-uart1-default-pins {
322 pinctrl-single,pins = <
330 main_uart0_pins_default: main-uart0-default-pins {
331 bootph-all;
332 pinctrl-single,pins = <
340 main_spi0_pins_default: main-spi0-default-pins {
341 pinctrl-single,pins = <
349 main_i2c0_pins_default: main-i2c0-default-pins {
350 bootph-all;
351 pinctrl-single,pins = <
357 main_i2c1_pins_default: main-i2c1-default-pins {
358 bootph-all;
359 pinctrl-single,pins = <
365 mdio1_pins_default: mdio1-default-pins {
366 bootph-all;
367 pinctrl-single,pins = <
373 rgmii1_pins_default: rgmii1-default-pins {
374 bootph-all;
375 pinctrl-single,pins = <
378 AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
391 rgmii2_pins_default: rgmii2-default-pins {
392 bootph-all;
393 pinctrl-single,pins = <
409 main_usb0_pins_default: main-usb0-default-pins {
410 bootph-all;
411 pinctrl-single,pins = <
416 ospi0_pins_default: ospi0-default-pins {
417 pinctrl-single,pins = <
432 main_ecap0_pins_default: main-ecap0-default-pins {
433 pinctrl-single,pins = <
438 main_mcan0_pins_default: main-mcan0-default-pins {
439 pinctrl-single,pins = <
445 main_mcan1_pins_default: main-mcan1-default-pins {
446 pinctrl-single,pins = <
452 ddr_vtt_pins_default: ddr-vtt-default-pins {
453 bootph-all;
454 pinctrl-single,pins = <
459 icssg1_mdio1_pins_default: icssg1-mdio1-default-pins {
460 pinctrl-single,pins = <
466 icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins {
467 pinctrl-single,pins = <
483 icssg1_iep0_pins_default: icssg1-iep0-default-pins {
484 pinctrl-single,pins = <
491 bootph-all;
493 pinctrl-names = "default";
494 pinctrl-0 = <&main_uart0_pins_default>;
500 pinctrl-names = "default";
501 pinctrl-0 = <&main_uart1_pins_default>;
505 bootph-all;
507 pinctrl-names = "default";
508 pinctrl-0 = <&main_i2c0_pins_default>;
509 clock-frequency = <400000>;
515 gpio-controller;
516 #gpio-cells = <2>;
517 gpio-line-names = "HSE_DETECT";
528 bootph-all;
530 pinctrl-names = "default";
531 pinctrl-0 = <&main_i2c1_pins_default>;
532 clock-frequency = <400000>;
535 bootph-all;
538 gpio-controller;
539 #gpio-cells = <2>;
540 gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
552 /* osd9616p0899-10 */
554 compatible = "solomon,ssd1306fb-i2c";
556 reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
557 vbat-supply = <&vddb>;
560 solomon,com-seq;
561 solomon,com-invdir;
562 solomon,page-offset = <0>;
569 bootph-all;
583 pinctrl-names = "default";
584 pinctrl-0 = <&main_spi0_pins_default>;
585 ti,pindir-d0-out-d1-in;
589 spi-max-frequency = <1000000>;
590 spi-cs-high;
591 data-size = <16>;
598 non-removable;
599 ti,driver-strength-ohm = <50>;
600 disable-wp;
601 bootph-all;
606 bootph-all;
608 vmmc-supply = <&vdd_mmc1>;
609 pinctrl-names = "default";
610 pinctrl-0 = <&main_mmc1_pins_default>;
611 disable-wp;
615 bootph-all;
616 ti,vbus-divider;
617 ti,usb2-only;
621 bootph-all;
623 maximum-speed = "high-speed";
624 pinctrl-names = "default";
625 pinctrl-0 = <&main_usb0_pins_default>;
629 bootph-all;
630 pinctrl-names = "default";
631 pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
636 bootph-all;
637 phy-mode = "rgmii-rxid";
638 phy-handle = <&cpsw3g_phy0>;
643 phy-mode = "rgmii-rxid";
644 phy-handle = <&cpsw3g_phy3>;
649 bootph-all;
651 pinctrl-names = "default";
652 pinctrl-0 = <&mdio1_pins_default>;
654 cpsw3g_phy0: ethernet-phy@0 {
655 bootph-all;
657 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
658 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
667 ti,adc-channels = <0 1 2 3 4 5 6 7>;
673 pinctrl-names = "default";
674 pinctrl-0 = <&ospi0_pins_default>;
677 compatible = "jedec,spi-nor";
679 spi-tx-bus-width = <8>;
680 spi-rx-bus-width = <8>;
681 spi-max-frequency = <25000000>;
682 cdns,tshsl-ns = <60>;
683 cdns,tsd2d-ns = <60>;
684 cdns,tchsh-ns = <60>;
685 cdns,tslch-ns = <60>;
686 cdns,read-delay = <4>;
689 compatible = "fixed-partitions";
690 #address-cells = <1>;
691 #size-cells = <1>;
704 label = "ospi.u-boot";
734 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
735 ti,mbox-rx = <0 0 2>;
736 ti,mbox-tx = <1 0 2>;
739 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
740 ti,mbox-rx = <2 0 2>;
741 ti,mbox-tx = <3 0 2>;
748 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
749 ti,mbox-rx = <0 0 2>;
750 ti,mbox-tx = <1 0 2>;
753 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
754 ti,mbox-rx = <2 0 2>;
755 ti,mbox-tx = <3 0 2>;
762 mbox_m4_0: mbox-m4-0 {
763 ti,mbox-rx = <0 0 2>;
764 ti,mbox-tx = <1 0 2>;
770 memory-region = <&main_r5fss0_core0_dma_memory_region>,
776 memory-region = <&main_r5fss0_core1_dma_memory_region>,
782 memory-region = <&main_r5fss1_core0_dma_memory_region>,
788 memory-region = <&main_r5fss1_core1_dma_memory_region>,
794 memory-region = <&mcu_m4fss_dma_memory_region>,
800 idle-states = <AM64_SERDES0_LANE0_PCIE0>;
806 cdns,num-lanes = <1>;
807 #phy-cells = <0>;
808 cdns,phy-type = <PHY_TYPE_PCIE>;
815 reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
817 phy-names = "pcie-phy";
818 num-lanes = <1>;
824 pinctrl-names = "default";
825 pinctrl-0 = <&main_ecap0_pins_default>;
830 pinctrl-names = "default";
831 pinctrl-0 = <&main_mcan0_pins_default>;
837 pinctrl-names = "default";
838 pinctrl-0 = <&main_mcan1_pins_default>;
844 pinctrl-names = "default";
845 pinctrl-0 = <&icssg1_mdio1_pins_default>;
847 icssg1_phy1: ethernet-phy@f {
849 tx-internal-delay-ps = <250>;
850 rx-internal-delay-ps = <2000>;
859 pinctrl-names = "default";
860 pinctrl-0 = <&icssg1_iep0_pins_default>;