Lines Matching +full:r5f +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include "k3-am642.dtsi"
14 #include "k3-serdes.h"
17 compatible = "ti,am642-evm", "ti,am642";
21 stdout-path = &main_uart0;
39 bootph-all;
42 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
45 reserved-memory {
46 #address-cells = <2>;
47 #size-cells = <2>;
51 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
52 alignment = <0x1000>;
53 no-map;
56 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
57 compatible = "shared-dma-pool";
58 reg = <0x00 0xa0000000 0x00 0x100000>;
59 no-map;
62 main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
63 compatible = "shared-dma-pool";
64 reg = <0x00 0xa0100000 0x00 0xf00000>;
65 no-map;
68 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
69 compatible = "shared-dma-pool";
70 reg = <0x00 0xa1000000 0x00 0x100000>;
71 no-map;
74 main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
75 compatible = "shared-dma-pool";
76 reg = <0x00 0xa1100000 0x00 0xf00000>;
77 no-map;
80 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
81 compatible = "shared-dma-pool";
82 reg = <0x00 0xa2000000 0x00 0x100000>;
83 no-map;
86 main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
87 compatible = "shared-dma-pool";
88 reg = <0x00 0xa2100000 0x00 0xf00000>;
89 no-map;
92 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
93 compatible = "shared-dma-pool";
94 reg = <0x00 0xa3000000 0x00 0x100000>;
95 no-map;
98 main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
99 compatible = "shared-dma-pool";
100 reg = <0x00 0xa3100000 0x00 0xf00000>;
101 no-map;
104 mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
105 compatible = "shared-dma-pool";
106 reg = <0x00 0xa4000000 0x00 0x100000>;
107 no-map;
110 mcu_m4fss_memory_region: m4f-memory@a4100000 {
111 compatible = "shared-dma-pool";
112 reg = <0x00 0xa4100000 0x00 0xf00000>;
113 no-map;
116 rtos_ipc_memory_region: ipc-memories@a5000000 {
117 reg = <0x00 0xa5000000 0x00 0x00800000>;
118 alignment = <0x1000>;
119 no-map;
123 evm_12v0: regulator-0 {
125 bootph-all;
126 compatible = "regulator-fixed";
127 regulator-name = "evm_12v0";
128 regulator-min-microvolt = <12000000>;
129 regulator-max-microvolt = <12000000>;
130 regulator-always-on;
131 regulator-boot-on;
134 vsys_5v0: regulator-1 {
136 compatible = "regulator-fixed";
137 regulator-name = "vsys_5v0";
138 regulator-min-microvolt = <5000000>;
139 regulator-max-microvolt = <5000000>;
140 vin-supply = <&evm_12v0>;
141 regulator-always-on;
142 regulator-boot-on;
145 vsys_3v3: regulator-2 {
147 bootph-all;
148 compatible = "regulator-fixed";
149 regulator-name = "vsys_3v3";
150 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <3300000>;
152 vin-supply = <&evm_12v0>;
153 regulator-always-on;
154 regulator-boot-on;
157 vdd_mmc1: regulator-3 {
159 bootph-all;
160 compatible = "regulator-fixed";
161 regulator-name = "vdd_mmc1";
162 regulator-min-microvolt = <3300000>;
163 regulator-max-microvolt = <3300000>;
164 regulator-boot-on;
165 enable-active-high;
166 vin-supply = <&vsys_3v3>;
170 vddb: regulator-4 {
171 compatible = "regulator-fixed";
172 regulator-name = "vddb_3v3_display";
173 regulator-min-microvolt = <3300000>;
174 regulator-max-microvolt = <3300000>;
175 vin-supply = <&vsys_3v3>;
176 regulator-always-on;
177 regulator-boot-on;
180 vtt_supply: regulator-5 {
181 bootph-all;
182 compatible = "regulator-fixed";
183 regulator-name = "vtt";
184 pinctrl-names = "default";
185 pinctrl-0 = <&ddr_vtt_pins_default>;
186 regulator-min-microvolt = <3300000>;
187 regulator-max-microvolt = <3300000>;
189 vin-supply = <&vsys_3v3>;
190 enable-active-high;
191 regulator-always-on;
192 regulator-boot-on;
196 compatible = "gpio-leds";
198 led-0 {
199 label = "am64-evm:red:heartbeat";
201 linux,default-trigger = "heartbeat";
203 default-state = "off";
207 mdio_mux: mux-controller {
208 compatible = "gpio-mux";
209 #mux-control-cells = <0>;
211 mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
214 mdio_mux_1: mdio-mux-1 {
215 compatible = "mdio-mux-multiplexer";
216 mux-controls = <&mdio_mux>;
217 mdio-parent-bus = <&cpsw3g_mdio>;
218 #address-cells = <1>;
219 #size-cells = <0>;
222 reg = <0x1>;
223 #address-cells = <1>;
224 #size-cells = <0>;
226 cpsw3g_phy3: ethernet-phy@3 {
232 transceiver1: can-phy0 {
234 #phy-cells = <0>;
235 max-bitrate = <5000000>;
236 standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>;
239 transceiver2: can-phy1 {
241 #phy-cells = <0>;
242 max-bitrate = <5000000>;
243 standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>;
246 icssg1_eth: icssg1-eth {
247 compatible = "ti,am642-icssg-prueth";
248 pinctrl-names = "default";
249 pinctrl-0 = <&icssg1_rgmii1_pins_default>;
252 firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf",
253 "ti-pruss/am64x-sr2-rtu0-prueth-fw.elf",
254 "ti-pruss/am64x-sr2-txpru0-prueth-fw.elf",
255 "ti-pruss/am64x-sr2-pru1-prueth-fw.elf",
256 "ti-pruss/am64x-sr2-rtu1-prueth-fw.elf",
257 "ti-pruss/am64x-sr2-txpru1-prueth-fw.elf";
259 ti,pruss-gp-mux-sel = <2>, /* MII mode */
265 ti,mii-g-rt = <&icssg1_mii_g_rt>;
266 ti,mii-rt = <&icssg1_mii_rt>;
268 ti,pa-stats = <&icssg1_pa_stats>;
269 interrupt-parent = <&icssg1_intc>;
270 interrupts = <24 0 2>, <25 1 3>;
271 interrupt-names = "tx_ts0", "tx_ts1";
272 dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
273 <&main_pktdma 0xc201 15>, /* egress slice 0 */
274 <&main_pktdma 0xc202 15>, /* egress slice 0 */
275 <&main_pktdma 0xc203 15>, /* egress slice 0 */
276 <&main_pktdma 0xc204 15>, /* egress slice 1 */
277 <&main_pktdma 0xc205 15>, /* egress slice 1 */
278 <&main_pktdma 0xc206 15>, /* egress slice 1 */
279 <&main_pktdma 0xc207 15>, /* egress slice 1 */
280 <&main_pktdma 0x4200 15>, /* ingress slice 0 */
281 <&main_pktdma 0x4201 15>; /* ingress slice 1 */
282 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
283 "tx1-0", "tx1-1", "tx1-2", "tx1-3",
286 ethernet-ports {
287 #address-cells = <1>;
288 #size-cells = <0>;
289 icssg1_emac0: port@0 {
290 reg = <0>;
291 phy-handle = <&icssg1_phy1>;
292 phy-mode = "rgmii-id";
294 local-mac-address = [00 00 00 00 00 00];
299 local-mac-address = [00 00 00 00 00 00];
307 main_mmc1_pins_default: main-mmc1-default-pins {
308 pinctrl-single,pins = <
309 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
310 AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
311 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
312 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
313 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
314 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
315 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
316 AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
317 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
321 main_uart1_pins_default: main-uart1-default-pins {
322 pinctrl-single,pins = <
323 AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
324 AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
325 AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
326 AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
330 main_uart0_pins_default: main-uart0-default-pins {
331 bootph-all;
332 pinctrl-single,pins = <
333 AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
334 AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
335 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
336 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
340 main_spi0_pins_default: main-spi0-default-pins {
341 pinctrl-single,pins = <
342 AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
343 AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
344 AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
345 AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
349 main_i2c0_pins_default: main-i2c0-default-pins {
350 bootph-all;
351 pinctrl-single,pins = <
352 AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
353 AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
357 main_i2c1_pins_default: main-i2c1-default-pins {
358 bootph-all;
359 pinctrl-single,pins = <
360 AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
361 AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
365 mdio1_pins_default: mdio1-default-pins {
366 bootph-all;
367 pinctrl-single,pins = <
368 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
369 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
373 rgmii1_pins_default: rgmii1-default-pins {
374 bootph-all;
375 pinctrl-single,pins = <
376 AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
377 AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
378 AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
379 AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
380 AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
381 AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
382 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
383 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
384 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
385 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
386 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
387 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
391 rgmii2_pins_default: rgmii2-default-pins {
392 bootph-all;
393 pinctrl-single,pins = <
394 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
395 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
396 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
397 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
398 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
399 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
400 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
401 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
402 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
403 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
404 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
405 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
409 main_usb0_pins_default: main-usb0-default-pins {
410 bootph-all;
411 pinctrl-single,pins = <
412 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
416 ospi0_pins_default: ospi0-default-pins {
417 pinctrl-single,pins = <
418 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
419 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
420 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
421 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
422 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
423 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
424 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
425 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
426 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
427 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
428 AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
432 main_ecap0_pins_default: main-ecap0-default-pins {
433 pinctrl-single,pins = <
434 AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
438 main_mcan0_pins_default: main-mcan0-default-pins {
439 pinctrl-single,pins = <
440 AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
441 AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
445 main_mcan1_pins_default: main-mcan1-default-pins {
446 pinctrl-single,pins = <
447 AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
448 AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
452 ddr_vtt_pins_default: ddr-vtt-default-pins {
453 bootph-all;
454 pinctrl-single,pins = <
455 AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
459 icssg1_mdio1_pins_default: icssg1-mdio1-default-pins {
460 pinctrl-single,pins = <
461 AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */
462 AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */
466 icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins {
467 pinctrl-single,pins = <
468 AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
469 AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
470 AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
471 AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
472 AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
473 AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
474 AM64X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */
475 AM64X_IOPAD(0x00e8, PIN_INPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */
476 AM64X_IOPAD(0x00ec, PIN_INPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */
477 AM64X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */
478 AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
479 AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */
483 icssg1_iep0_pins_default: icssg1-iep0-default-pins {
484 pinctrl-single,pins = <
485 AM64X_IOPAD(0x0104, PIN_OUTPUT, 2) /* (W7) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */
491 bootph-all;
493 pinctrl-names = "default";
494 pinctrl-0 = <&main_uart0_pins_default>;
500 pinctrl-names = "default";
501 pinctrl-0 = <&main_uart1_pins_default>;
505 bootph-all;
507 pinctrl-names = "default";
508 pinctrl-0 = <&main_i2c0_pins_default>;
509 clock-frequency = <400000>;
514 reg = <0x38>;
515 gpio-controller;
516 #gpio-cells = <2>;
517 gpio-line-names = "HSE_DETECT";
523 reg = <0x50>;
528 bootph-all;
530 pinctrl-names = "default";
531 pinctrl-0 = <&main_i2c1_pins_default>;
532 clock-frequency = <400000>;
535 bootph-all;
537 reg = <0x22>;
538 gpio-controller;
539 #gpio-cells = <2>;
540 gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
552 /* osd9616p0899-10 */
554 compatible = "solomon,ssd1306fb-i2c";
555 reg = <0x3c>;
556 reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
557 vbat-supply = <&vddb>;
560 solomon,com-seq;
561 solomon,com-invdir;
562 solomon,page-offset = <0>;
569 bootph-all;
583 pinctrl-names = "default";
584 pinctrl-0 = <&main_spi0_pins_default>;
585 ti,pindir-d0-out-d1-in;
586 eeprom@0 {
588 reg = <0>;
589 spi-max-frequency = <1000000>;
590 spi-cs-high;
591 data-size = <16>;
598 non-removable;
599 ti,driver-strength-ohm = <50>;
600 bootph-all;
605 bootph-all;
607 vmmc-supply = <&vdd_mmc1>;
608 pinctrl-names = "default";
609 pinctrl-0 = <&main_mmc1_pins_default>;
610 disable-wp;
614 bootph-all;
615 ti,vbus-divider;
616 ti,usb2-only;
620 bootph-all;
622 maximum-speed = "high-speed";
623 pinctrl-names = "default";
624 pinctrl-0 = <&main_usb0_pins_default>;
628 bootph-all;
629 pinctrl-names = "default";
630 pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
635 bootph-all;
636 phy-mode = "rgmii-rxid";
637 phy-handle = <&cpsw3g_phy0>;
642 phy-mode = "rgmii-rxid";
643 phy-handle = <&cpsw3g_phy3>;
648 bootph-all;
650 pinctrl-names = "default";
651 pinctrl-0 = <&mdio1_pins_default>;
653 cpsw3g_phy0: ethernet-phy@0 {
654 bootph-all;
655 reg = <0>;
656 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
657 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
666 ti,adc-channels = <0 1 2 3 4 5 6 7>;
672 pinctrl-names = "default";
673 pinctrl-0 = <&ospi0_pins_default>;
675 flash@0 {
676 compatible = "jedec,spi-nor";
677 reg = <0x0>;
678 spi-tx-bus-width = <8>;
679 spi-rx-bus-width = <8>;
680 spi-max-frequency = <25000000>;
681 cdns,tshsl-ns = <60>;
682 cdns,tsd2d-ns = <60>;
683 cdns,tchsh-ns = <60>;
684 cdns,tslch-ns = <60>;
685 cdns,read-delay = <4>;
688 compatible = "fixed-partitions";
689 #address-cells = <1>;
690 #size-cells = <1>;
692 partition@0 {
694 reg = <0x0 0x100000>;
699 reg = <0x100000 0x200000>;
703 label = "ospi.u-boot";
704 reg = <0x300000 0x400000>;
709 reg = <0x700000 0x40000>;
714 reg = <0x740000 0x40000>;
719 reg = <0x800000 0x37c0000>;
724 reg = <0x3fc0000 0x40000>;
733 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
734 ti,mbox-rx = <0 0 2>;
735 ti,mbox-tx = <1 0 2>;
738 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
739 ti,mbox-rx = <2 0 2>;
740 ti,mbox-tx = <3 0 2>;
747 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
748 ti,mbox-rx = <0 0 2>;
749 ti,mbox-tx = <1 0 2>;
752 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
753 ti,mbox-rx = <2 0 2>;
754 ti,mbox-tx = <3 0 2>;
761 mbox_m4_0: mbox-m4-0 {
762 ti,mbox-rx = <0 0 2>;
763 ti,mbox-tx = <1 0 2>;
769 memory-region = <&main_r5fss0_core0_dma_memory_region>,
775 memory-region = <&main_r5fss0_core1_dma_memory_region>,
781 memory-region = <&main_r5fss1_core0_dma_memory_region>,
787 memory-region = <&main_r5fss1_core1_dma_memory_region>,
793 memory-region = <&mcu_m4fss_dma_memory_region>,
798 /* main_timer8 is used by r5f0-0 */
803 /* main_timer9 is used by r5f0-1 */
808 /* main_timer10 is used by r5f1-0 */
813 /* main_timer11 is used by r5f1-1 */
819 idle-states = <AM64_SERDES0_LANE0_PCIE0>;
823 serdes0_pcie_link: phy@0 {
824 reg = <0>;
825 cdns,num-lanes = <1>;
826 #phy-cells = <0>;
827 cdns,phy-type = <PHY_TYPE_PCIE>;
834 reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
836 phy-names = "pcie-phy";
837 num-lanes = <1>;
843 pinctrl-names = "default";
844 pinctrl-0 = <&main_ecap0_pins_default>;
849 pinctrl-names = "default";
850 pinctrl-0 = <&main_mcan0_pins_default>;
856 pinctrl-names = "default";
857 pinctrl-0 = <&main_mcan1_pins_default>;
863 pinctrl-names = "default";
864 pinctrl-0 = <&icssg1_mdio1_pins_default>;
866 icssg1_phy1: ethernet-phy@f {
867 reg = <0xf>;
868 tx-internal-delay-ps = <250>;
869 rx-internal-delay-ps = <2000>;
874 ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */
878 pinctrl-names = "default";
879 pinctrl-0 = <&icssg1_iep0_pins_default>;