Lines Matching +full:f +full:- +full:ospi
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include "k3-am642.dtsi"
14 #include "k3-serdes.h"
17 compatible = "ti,am642-evm", "ti,am642";
21 stdout-path = &main_uart0;
39 bootph-all;
45 reserved-memory {
46 #address-cells = <2>;
47 #size-cells = <2>;
51 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
53 no-map;
56 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
57 compatible = "shared-dma-pool";
59 no-map;
62 main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
63 compatible = "shared-dma-pool";
65 no-map;
68 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
69 compatible = "shared-dma-pool";
71 no-map;
74 main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
75 compatible = "shared-dma-pool";
77 no-map;
80 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
81 compatible = "shared-dma-pool";
83 no-map;
86 main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
87 compatible = "shared-dma-pool";
89 no-map;
92 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
93 compatible = "shared-dma-pool";
95 no-map;
98 main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
99 compatible = "shared-dma-pool";
101 no-map;
104 rtos_ipc_memory_region: ipc-memories@a5000000 {
107 no-map;
111 evm_12v0: regulator-0 {
113 bootph-all;
114 compatible = "regulator-fixed";
115 regulator-name = "evm_12v0";
116 regulator-min-microvolt = <12000000>;
117 regulator-max-microvolt = <12000000>;
118 regulator-always-on;
119 regulator-boot-on;
122 vsys_5v0: regulator-1 {
124 compatible = "regulator-fixed";
125 regulator-name = "vsys_5v0";
126 regulator-min-microvolt = <5000000>;
127 regulator-max-microvolt = <5000000>;
128 vin-supply = <&evm_12v0>;
129 regulator-always-on;
130 regulator-boot-on;
133 vsys_3v3: regulator-2 {
135 bootph-all;
136 compatible = "regulator-fixed";
137 regulator-name = "vsys_3v3";
138 regulator-min-microvolt = <3300000>;
139 regulator-max-microvolt = <3300000>;
140 vin-supply = <&evm_12v0>;
141 regulator-always-on;
142 regulator-boot-on;
145 vdd_mmc1: regulator-3 {
147 bootph-all;
148 compatible = "regulator-fixed";
149 regulator-name = "vdd_mmc1";
150 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <3300000>;
152 regulator-boot-on;
153 enable-active-high;
154 vin-supply = <&vsys_3v3>;
158 vddb: regulator-4 {
159 compatible = "regulator-fixed";
160 regulator-name = "vddb_3v3_display";
161 regulator-min-microvolt = <3300000>;
162 regulator-max-microvolt = <3300000>;
163 vin-supply = <&vsys_3v3>;
164 regulator-always-on;
165 regulator-boot-on;
168 vtt_supply: regulator-5 {
169 bootph-all;
170 compatible = "regulator-fixed";
171 regulator-name = "vtt";
172 pinctrl-names = "default";
173 pinctrl-0 = <&ddr_vtt_pins_default>;
174 regulator-min-microvolt = <3300000>;
175 regulator-max-microvolt = <3300000>;
177 vin-supply = <&vsys_3v3>;
178 enable-active-high;
179 regulator-always-on;
180 regulator-boot-on;
184 compatible = "gpio-leds";
186 led-0 {
187 label = "am64-evm:red:heartbeat";
189 linux,default-trigger = "heartbeat";
191 default-state = "off";
195 mdio_mux: mux-controller {
196 compatible = "gpio-mux";
197 #mux-control-cells = <0>;
199 mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
202 mdio_mux_1: mdio-mux-1 {
203 compatible = "mdio-mux-multiplexer";
204 mux-controls = <&mdio_mux>;
205 mdio-parent-bus = <&cpsw3g_mdio>;
206 #address-cells = <1>;
207 #size-cells = <0>;
211 #address-cells = <1>;
212 #size-cells = <0>;
214 cpsw3g_phy3: ethernet-phy@3 {
220 transceiver1: can-phy0 {
222 #phy-cells = <0>;
223 max-bitrate = <5000000>;
224 standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>;
227 transceiver2: can-phy1 {
229 #phy-cells = <0>;
230 max-bitrate = <5000000>;
231 standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>;
234 icssg1_eth: icssg1-eth {
235 compatible = "ti,am642-icssg-prueth";
236 pinctrl-names = "default";
237 pinctrl-0 = <&icssg1_rgmii1_pins_default>;
240 firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf",
241 "ti-pruss/am64x-sr2-rtu0-prueth-fw.elf",
242 "ti-pruss/am64x-sr2-txpru0-prueth-fw.elf",
243 "ti-pruss/am64x-sr2-pru1-prueth-fw.elf",
244 "ti-pruss/am64x-sr2-rtu1-prueth-fw.elf",
245 "ti-pruss/am64x-sr2-txpru1-prueth-fw.elf";
247 ti,pruss-gp-mux-sel = <2>, /* MII mode */
253 ti,mii-g-rt = <&icssg1_mii_g_rt>;
254 ti,mii-rt = <&icssg1_mii_rt>;
256 interrupt-parent = <&icssg1_intc>;
258 interrupt-names = "tx_ts0", "tx_ts1";
269 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
270 "tx1-0", "tx1-1", "tx1-2", "tx1-3",
273 ethernet-ports {
274 #address-cells = <1>;
275 #size-cells = <0>;
278 phy-handle = <&icssg1_phy1>;
279 phy-mode = "rgmii-id";
281 local-mac-address = [00 00 00 00 00 00];
286 local-mac-address = [00 00 00 00 00 00];
294 main_mmc1_pins_default: main-mmc1-default-pins {
295 pinctrl-single,pins = <
308 main_uart1_pins_default: main-uart1-default-pins {
309 pinctrl-single,pins = <
317 main_uart0_pins_default: main-uart0-default-pins {
318 bootph-all;
319 pinctrl-single,pins = <
327 main_spi0_pins_default: main-spi0-default-pins {
328 pinctrl-single,pins = <
336 main_i2c0_pins_default: main-i2c0-default-pins {
337 bootph-all;
338 pinctrl-single,pins = <
344 main_i2c1_pins_default: main-i2c1-default-pins {
345 bootph-all;
346 pinctrl-single,pins = <
352 mdio1_pins_default: mdio1-default-pins {
353 bootph-all;
354 pinctrl-single,pins = <
360 rgmii1_pins_default: rgmii1-default-pins {
361 bootph-all;
362 pinctrl-single,pins = <
378 rgmii2_pins_default: rgmii2-default-pins {
379 bootph-all;
380 pinctrl-single,pins = <
396 main_usb0_pins_default: main-usb0-default-pins {
397 bootph-all;
398 pinctrl-single,pins = <
403 ospi0_pins_default: ospi0-default-pins {
404 pinctrl-single,pins = <
419 main_ecap0_pins_default: main-ecap0-default-pins {
420 pinctrl-single,pins = <
425 main_mcan0_pins_default: main-mcan0-default-pins {
426 pinctrl-single,pins = <
432 main_mcan1_pins_default: main-mcan1-default-pins {
433 pinctrl-single,pins = <
439 ddr_vtt_pins_default: ddr-vtt-default-pins {
440 bootph-all;
441 pinctrl-single,pins = <
446 icssg1_mdio1_pins_default: icssg1-mdio1-default-pins {
447 pinctrl-single,pins = <
453 icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins{
454 pinctrl-single,pins = <
470 icssg1_iep0_pins_default: icssg1-iep0-default-pins {
471 pinctrl-single,pins = <
478 bootph-all;
480 pinctrl-names = "default";
481 pinctrl-0 = <&main_uart0_pins_default>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&main_uart1_pins_default>;
492 bootph-all;
494 pinctrl-names = "default";
495 pinctrl-0 = <&main_i2c0_pins_default>;
496 clock-frequency = <400000>;
502 gpio-controller;
503 #gpio-cells = <2>;
504 gpio-line-names = "HSE_DETECT";
515 bootph-all;
517 pinctrl-names = "default";
518 pinctrl-0 = <&main_i2c1_pins_default>;
519 clock-frequency = <400000>;
522 bootph-all;
525 gpio-controller;
526 #gpio-cells = <2>;
527 gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
539 /* osd9616p0899-10 */
541 compatible = "solomon,ssd1306fb-i2c";
543 reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
544 vbat-supply = <&vddb>;
547 solomon,com-seq;
548 solomon,com-invdir;
549 solomon,page-offset = <0>;
556 bootph-all;
570 pinctrl-names = "default";
571 pinctrl-0 = <&main_spi0_pins_default>;
572 ti,pindir-d0-out-d1-in;
576 spi-max-frequency = <1000000>;
577 spi-cs-high;
578 data-size = <16>;
585 non-removable;
586 ti,driver-strength-ohm = <50>;
587 disable-wp;
588 bootph-all;
593 bootph-all;
595 vmmc-supply = <&vdd_mmc1>;
596 pinctrl-names = "default";
597 pinctrl-0 = <&main_mmc1_pins_default>;
598 disable-wp;
602 bootph-all;
603 ti,vbus-divider;
604 ti,usb2-only;
608 bootph-all;
610 maximum-speed = "high-speed";
611 pinctrl-names = "default";
612 pinctrl-0 = <&main_usb0_pins_default>;
616 bootph-all;
617 pinctrl-names = "default";
618 pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
623 bootph-all;
624 phy-mode = "rgmii-rxid";
625 phy-handle = <&cpsw3g_phy0>;
630 phy-mode = "rgmii-rxid";
631 phy-handle = <&cpsw3g_phy3>;
636 bootph-all;
638 pinctrl-names = "default";
639 pinctrl-0 = <&mdio1_pins_default>;
641 cpsw3g_phy0: ethernet-phy@0 {
642 bootph-all;
644 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
645 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
654 ti,adc-channels = <0 1 2 3 4 5 6 7>;
660 pinctrl-names = "default";
661 pinctrl-0 = <&ospi0_pins_default>;
664 compatible = "jedec,spi-nor";
666 spi-tx-bus-width = <8>;
667 spi-rx-bus-width = <8>;
668 spi-max-frequency = <25000000>;
669 cdns,tshsl-ns = <60>;
670 cdns,tsd2d-ns = <60>;
671 cdns,tchsh-ns = <60>;
672 cdns,tslch-ns = <60>;
673 cdns,read-delay = <4>;
676 compatible = "fixed-partitions";
677 #address-cells = <1>;
678 #size-cells = <1>;
681 label = "ospi.tiboot3";
686 label = "ospi.tispl";
691 label = "ospi.u-boot";
696 label = "ospi.env";
701 label = "ospi.env.backup";
706 label = "ospi.rootfs";
711 label = "ospi.phypattern";
721 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
722 ti,mbox-rx = <0 0 2>;
723 ti,mbox-tx = <1 0 2>;
726 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
727 ti,mbox-rx = <2 0 2>;
728 ti,mbox-tx = <3 0 2>;
735 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
736 ti,mbox-rx = <0 0 2>;
737 ti,mbox-tx = <1 0 2>;
740 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
741 ti,mbox-rx = <2 0 2>;
742 ti,mbox-tx = <3 0 2>;
749 mbox_m4_0: mbox-m4-0 {
750 ti,mbox-rx = <0 0 2>;
751 ti,mbox-tx = <1 0 2>;
757 memory-region = <&main_r5fss0_core0_dma_memory_region>,
763 memory-region = <&main_r5fss0_core1_dma_memory_region>,
769 memory-region = <&main_r5fss1_core0_dma_memory_region>,
775 memory-region = <&main_r5fss1_core1_dma_memory_region>,
780 idle-states = <AM64_SERDES0_LANE0_PCIE0>;
786 cdns,num-lanes = <1>;
787 #phy-cells = <0>;
788 cdns,phy-type = <PHY_TYPE_PCIE>;
795 reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
797 phy-names = "pcie-phy";
798 num-lanes = <1>;
804 pinctrl-names = "default";
805 pinctrl-0 = <&main_ecap0_pins_default>;
810 pinctrl-names = "default";
811 pinctrl-0 = <&main_mcan0_pins_default>;
817 pinctrl-names = "default";
818 pinctrl-0 = <&main_mcan1_pins_default>;
824 pinctrl-names = "default";
825 pinctrl-0 = <&icssg1_mdio1_pins_default>;
827 icssg1_phy1: ethernet-phy@f {
829 tx-internal-delay-ps = <250>;
830 rx-internal-delay-ps = <2000>;
839 pinctrl-names = "default";
840 pinctrl-0 = <&icssg1_iep0_pins_default>;