Lines Matching +full:1 +full:fc0000
134 vsys_5v0: regulator-1 {
214 mdio_mux_1: mdio-mux-1 {
218 #address-cells = <1>;
221 mdio@1 {
223 #address-cells = <1>;
270 interrupts = <24 0 2>, <25 1 3>;
276 <&main_pktdma 0xc204 15>, /* egress slice 1 */
277 <&main_pktdma 0xc205 15>, /* egress slice 1 */
278 <&main_pktdma 0xc206 15>, /* egress slice 1 */
279 <&main_pktdma 0xc207 15>, /* egress slice 1 */
281 <&main_pktdma 0x4201 15>; /* ingress slice 1 */
282 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
283 "tx1-0", "tx1-1", "tx1-2", "tx1-3",
287 #address-cells = <1>;
296 icssg1_emac1: port@1 {
297 reg = <1>;
667 ti,adc-channels = <0 1 2 3 4 5 6 7>;
690 #address-cells = <1>;
691 #size-cells = <1>;
723 partition@3fc0000 {
736 ti,mbox-tx = <1 0 2>;
750 ti,mbox-tx = <1 0 2>;
764 ti,mbox-tx = <1 0 2>;
806 cdns,num-lanes = <1>;
809 resets = <&serdes_wiz0 1>;
818 num-lanes = <1>;
823 /* PWM is available on Pin 1 of header J12 */