Lines Matching +full:0 +full:x51000000
42 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
51 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
52 alignment = <0x1000>;
58 reg = <0x00 0xa0000000 0x00 0x100000>;
64 reg = <0x00 0xa0100000 0x00 0xf00000>;
70 reg = <0x00 0xa1000000 0x00 0x100000>;
76 reg = <0x00 0xa1100000 0x00 0xf00000>;
82 reg = <0x00 0xa2000000 0x00 0x100000>;
88 reg = <0x00 0xa2100000 0x00 0xf00000>;
94 reg = <0x00 0xa3000000 0x00 0x100000>;
100 reg = <0x00 0xa3100000 0x00 0xf00000>;
106 reg = <0x00 0xa4000000 0x00 0x100000>;
112 reg = <0x00 0xa4100000 0x00 0xf00000>;
117 reg = <0x00 0xa5000000 0x00 0x00800000>;
118 alignment = <0x1000>;
123 evm_12v0: regulator-0 {
185 pinctrl-0 = <&ddr_vtt_pins_default>;
198 led-0 {
209 #mux-control-cells = <0>;
219 #size-cells = <0>;
222 reg = <0x1>;
224 #size-cells = <0>;
234 #phy-cells = <0>;
241 #phy-cells = <0>;
249 pinctrl-0 = <&icssg1_rgmii1_pins_default>;
270 interrupts = <24 0 2>, <25 1 3>;
272 dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
273 <&main_pktdma 0xc201 15>, /* egress slice 0 */
274 <&main_pktdma 0xc202 15>, /* egress slice 0 */
275 <&main_pktdma 0xc203 15>, /* egress slice 0 */
276 <&main_pktdma 0xc204 15>, /* egress slice 1 */
277 <&main_pktdma 0xc205 15>, /* egress slice 1 */
278 <&main_pktdma 0xc206 15>, /* egress slice 1 */
279 <&main_pktdma 0xc207 15>, /* egress slice 1 */
280 <&main_pktdma 0x4200 15>, /* ingress slice 0 */
281 <&main_pktdma 0x4201 15>; /* ingress slice 1 */
282 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
283 "tx1-0", "tx1-1", "tx1-2", "tx1-3",
288 #size-cells = <0>;
289 icssg1_emac0: port@0 {
290 reg = <0>;
309 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
310 AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
311 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
312 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
313 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
314 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
315 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
316 AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
317 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
323 AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
324 AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
325 AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
326 AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
333 AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
334 AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
335 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
336 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
342 AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
343 AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
344 AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
345 AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
352 AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
353 AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
360 AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
361 AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
368 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
369 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
376 AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
377 AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
378 AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
379 AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
380 AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
381 AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
382 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
383 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
384 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
385 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
386 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
387 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
394 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
395 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
396 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
397 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
398 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
399 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
400 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
401 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
402 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
403 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
404 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
405 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
412 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
418 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
419 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
420 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
421 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
422 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
423 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
424 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
425 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
426 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
427 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
428 AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
434 AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
440 AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
441 AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
447 AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
448 AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
455 AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
461 AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */
462 AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */
468 AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
469 AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
470 AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
471 AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
472 AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
473 AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
474 AM64X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */
475 AM64X_IOPAD(0x00e8, PIN_INPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */
476 AM64X_IOPAD(0x00ec, PIN_INPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */
477 AM64X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */
478 AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
479 AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */
485 AM64X_IOPAD(0x0104, PIN_OUTPUT, 2) /* (W7) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */
494 pinctrl-0 = <&main_uart0_pins_default>;
501 pinctrl-0 = <&main_uart1_pins_default>;
508 pinctrl-0 = <&main_i2c0_pins_default>;
514 reg = <0x38>;
523 reg = <0x50>;
531 pinctrl-0 = <&main_i2c1_pins_default>;
537 reg = <0x22>;
555 reg = <0x3c>;
562 solomon,page-offset = <0>;
584 pinctrl-0 = <&main_spi0_pins_default>;
586 eeprom@0 {
588 reg = <0>;
610 pinctrl-0 = <&main_mmc1_pins_default>;
625 pinctrl-0 = <&main_usb0_pins_default>;
631 pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
652 pinctrl-0 = <&mdio1_pins_default>;
654 cpsw3g_phy0: ethernet-phy@0 {
656 reg = <0>;
667 ti,adc-channels = <0 1 2 3 4 5 6 7>;
674 pinctrl-0 = <&ospi0_pins_default>;
676 flash@0 {
678 reg = <0x0>;
693 partition@0 {
695 reg = <0x0 0x100000>;
700 reg = <0x100000 0x200000>;
705 reg = <0x300000 0x400000>;
710 reg = <0x700000 0x40000>;
715 reg = <0x740000 0x40000>;
720 reg = <0x800000 0x37c0000>;
725 reg = <0x3fc0000 0x40000>;
735 ti,mbox-rx = <0 0 2>;
736 ti,mbox-tx = <1 0 2>;
740 ti,mbox-rx = <2 0 2>;
741 ti,mbox-tx = <3 0 2>;
749 ti,mbox-rx = <0 0 2>;
750 ti,mbox-tx = <1 0 2>;
754 ti,mbox-rx = <2 0 2>;
755 ti,mbox-tx = <3 0 2>;
762 mbox_m4_0: mbox-m4-0 {
763 ti,mbox-rx = <0 0 2>;
764 ti,mbox-tx = <1 0 2>;
804 serdes0_pcie_link: phy@0 {
805 reg = <0>;
807 #phy-cells = <0>;
825 pinctrl-0 = <&main_ecap0_pins_default>;
831 pinctrl-0 = <&main_mcan0_pins_default>;
838 pinctrl-0 = <&main_mcan1_pins_default>;
845 pinctrl-0 = <&icssg1_mdio1_pins_default>;
848 reg = <0xf>;
855 ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */
860 pinctrl-0 = <&icssg1_iep0_pins_default>;