Lines Matching +full:0 +full:x25800
13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x00 0x70000000 0x00 0x200000>;
25 ranges = <0x0 0x00 0x70000000 0x200000>;
28 reg = <0x1c0000 0x20000>;
32 reg = <0x1e0000 0x1c000>;
36 reg = <0x1fc000 0x4000>;
43 reg = <0x0 0x43000000 0x0 0x20000>;
46 ranges = <0x0 0x0 0x43000000 0x20000>;
51 reg = <0x00000014 0x4>;
56 reg = <0x4080 0x4>;
58 mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */
63 reg = <0x4044 0x8>;
69 reg = <0x4130 0x4>;
81 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
82 <0x00 0x01840000 0x00 0xC0000>, /* GICR */
83 <0x01 0x00000000 0x00 0x2000>, /* GICC */
84 <0x01 0x00010000 0x00 0x1000>, /* GICH */
85 <0x01 0x00020000 0x00 0x2000>; /* GICV */
94 reg = <0x00 0x01820000 0x00 0x10000>;
95 socionext,synquacer-pre-its = <0x1000000 0x400000>;
107 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
116 reg = <0x00 0x4d000000 0x00 0x80000>,
117 <0x00 0x4a600000 0x00 0x80000>,
118 <0x00 0x4a400000 0x00 0x80000>;
125 reg = <0x00 0x48000000 0x00 0x100000>;
126 #interrupt-cells = <0>;
138 reg = <0x00 0x485c0100 0x00 0x100>,
139 <0x00 0x4c000000 0x00 0x20000>,
140 <0x00 0x4a820000 0x00 0x20000>,
141 <0x00 0x4aa40000 0x00 0x20000>,
142 <0x00 0x4bc00000 0x00 0x100000>,
143 <0x00 0x48600000 0x00 0x8000>,
144 <0x00 0x484a4000 0x00 0x2000>,
145 <0x00 0x484c2000 0x00 0x2000>,
146 <0x00 0x48420000 0x00 0x2000>;
154 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
155 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
156 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
161 reg = <0x00 0x485c0000 0x00 0x100>,
162 <0x00 0x4a800000 0x00 0x20000>,
163 <0x00 0x4aa00000 0x00 0x40000>,
164 <0x00 0x4b800000 0x00 0x400000>,
165 <0x00 0x485e0000 0x00 0x20000>,
166 <0x00 0x484a0000 0x00 0x4000>,
167 <0x00 0x484c0000 0x00 0x2000>,
168 <0x00 0x48430000 0x00 0x4000>;
176 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
177 <0x24>, /* CPSW_TX_CHAN */
178 <0x25>, /* SAUL_TX_0_CHAN */
179 <0x26>, /* SAUL_TX_1_CHAN */
180 <0x27>, /* ICSSG_0_TX_CHAN */
181 <0x28>; /* ICSSG_1_TX_CHAN */
182 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
183 <0x11>, /* RING_CPSW_TX_CHAN */
184 <0x12>, /* RING_SAUL_TX_0_CHAN */
185 <0x13>, /* RING_SAUL_TX_1_CHAN */
186 <0x14>, /* RING_ICSSG_0_TX_CHAN */
187 <0x15>; /* RING_ICSSG_1_TX_CHAN */
188 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
189 <0x2b>, /* CPSW_RX_CHAN */
190 <0x2d>, /* SAUL_RX_0_CHAN */
191 <0x2f>, /* SAUL_RX_1_CHAN */
192 <0x31>, /* SAUL_RX_2_CHAN */
193 <0x33>, /* SAUL_RX_3_CHAN */
194 <0x35>, /* ICSSG_0_RX_CHAN */
195 <0x37>; /* ICSSG_1_RX_CHAN */
196 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
197 <0x2c>, /* FLOW_CPSW_RX_CHAN */
198 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
199 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
200 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */
201 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */
213 reg = <0x00 0x44043000 0x00 0xfe0>;
237 reg = <0x00 0xf4000 0x00 0x2d0>;
240 pinctrl-single,function-mask = <0xffffffff>;
246 reg = <0x00 0x2400000 0x00 0x400>;
258 reg = <0x00 0x2410000 0x00 0x400>;
270 reg = <0x00 0x2420000 0x00 0x400>;
282 reg = <0x00 0x2430000 0x00 0x400>;
294 reg = <0x00 0x2440000 0x00 0x400>;
306 reg = <0x00 0x2450000 0x00 0x400>;
318 reg = <0x00 0x2460000 0x00 0x400>;
330 reg = <0x00 0x2470000 0x00 0x400>;
342 reg = <0x00 0x2480000 0x00 0x400>;
354 reg = <0x00 0x2490000 0x00 0x400>;
366 reg = <0x00 0x24a0000 0x00 0x400>;
378 reg = <0x00 0x24b0000 0x00 0x400>;
391 reg = <0x00 0x420000 0x00 0x1000>;
398 reg = <0x00 0x02800000 0x00 0x100>;
402 clocks = <&k3_clks 146 0>;
409 reg = <0x00 0x02810000 0x00 0x100>;
413 clocks = <&k3_clks 152 0>;
420 reg = <0x00 0x02820000 0x00 0x100>;
424 clocks = <&k3_clks 153 0>;
431 reg = <0x00 0x02830000 0x00 0x100>;
435 clocks = <&k3_clks 154 0>;
442 reg = <0x00 0x02840000 0x00 0x100>;
446 clocks = <&k3_clks 155 0>;
453 reg = <0x00 0x02850000 0x00 0x100>;
457 clocks = <&k3_clks 156 0>;
464 reg = <0x00 0x02860000 0x00 0x100>;
468 clocks = <&k3_clks 158 0>;
475 reg = <0x00 0x20000000 0x00 0x100>;
478 #size-cells = <0>;
487 reg = <0x00 0x20010000 0x00 0x100>;
490 #size-cells = <0>;
499 reg = <0x00 0x20020000 0x00 0x100>;
502 #size-cells = <0>;
511 reg = <0x00 0x20030000 0x00 0x100>;
514 #size-cells = <0>;
523 reg = <0x00 0x20100000 0x00 0x400>;
526 #size-cells = <0>;
528 clocks = <&k3_clks 141 0>;
529 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
536 reg = <0x00 0x20110000 0x00 0x400>;
539 #size-cells = <0>;
541 clocks = <&k3_clks 142 0>;
547 reg = <0x00 0x20120000 0x00 0x400>;
550 #size-cells = <0>;
552 clocks = <&k3_clks 143 0>;
558 reg = <0x00 0x20130000 0x00 0x400>;
561 #size-cells = <0>;
563 clocks = <&k3_clks 144 0>;
569 reg = <0x00 0x20140000 0x00 0x400>;
572 #size-cells = <0>;
574 clocks = <&k3_clks 145 0>;
580 reg = <0x00 0x00a00000 0x00 0x800>;
587 ti,interrupt-ranges = <0 32 16>;
592 reg = <0x0 0x00600000 0x0 0x100>;
601 ti,davinci-gpio-unbanked = <0>;
603 clocks = <&k3_clks 77 0>;
609 reg = <0x0 0x00601000 0x0 0x100>;
618 ti,davinci-gpio-unbanked = <0>;
620 clocks = <&k3_clks 78 0>;
626 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
629 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
634 ti,clkbuf-sel = <0x7>;
635 ti,trm-icp = <0x2>;
636 ti,otap-del-sel-legacy = <0x0>;
637 ti,otap-del-sel-mmc-hs = <0x0>;
638 ti,otap-del-sel-ddr52 = <0x6>;
639 ti,otap-del-sel-hs200 = <0x7>;
640 ti,itap-del-sel-legacy = <0x10>;
641 ti,itap-del-sel-mmc-hs = <0xa>;
642 ti,itap-del-sel-ddr52 = <0x3>;
648 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
654 ti,clkbuf-sel = <0x7>;
655 ti,otap-del-sel-legacy = <0x0>;
656 ti,otap-del-sel-sd-hs = <0x0>;
657 ti,otap-del-sel-sdr12 = <0xf>;
658 ti,otap-del-sel-sdr25 = <0xf>;
659 ti,otap-del-sel-sdr50 = <0xc>;
660 ti,otap-del-sel-sdr104 = <0x6>;
661 ti,otap-del-sel-ddr50 = <0x9>;
662 ti,itap-del-sel-legacy = <0x0>;
663 ti,itap-del-sel-sd-hs = <0x0>;
664 ti,itap-del-sel-sdr12 = <0x0>;
665 ti,itap-del-sel-sdr25 = <0x0>;
673 reg = <0x0 0x8000000 0x0 0x200000>;
675 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
676 clocks = <&k3_clks 13 0>;
683 dmas = <&main_pktdma 0xC500 15>,
684 <&main_pktdma 0xC501 15>,
685 <&main_pktdma 0xC502 15>,
686 <&main_pktdma 0xC503 15>,
687 <&main_pktdma 0xC504 15>,
688 <&main_pktdma 0xC505 15>,
689 <&main_pktdma 0xC506 15>,
690 <&main_pktdma 0xC507 15>,
691 <&main_pktdma 0x4500 15>;
697 #size-cells = <0>;
705 ti,syscon-efuse = <&main_conf 0x200>;
721 reg = <0x0 0xf00 0x0 0x100>;
723 #size-cells = <0>;
724 clocks = <&k3_clks 13 0>;
732 reg = <0x0 0x3d000 0x0 0x400>;
744 reg = <0x0 0x39000000 0x0 0x400>;
747 clocks = <&k3_clks 84 0>;
749 assigned-clocks = <&k3_clks 84 0>;
759 reg = <0x0 0xa40000 0x0 0x800>;
762 pinctrl-single,function-mask = <0x000107ff>;
767 reg = <0x00 0xf900000 0x00 0x100>;
778 reg = <0x00 0xf400000 0x00 0x10000>,
779 <0x00 0xf410000 0x00 0x10000>,
780 <0x00 0xf420000 0x00 0x10000>;
784 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
797 reg = <0x00 0x28001000 0x00 0x1000>;
799 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
800 clocks = <&k3_clks 0 0>;
801 assigned-clocks = <&k3_clks 0 0>;
802 assigned-clock-parents = <&k3_clks 0 3>;
815 reg = <0x00 0x0fc00000 0x00 0x70000>;
822 reg = <0x00 0x0fc40000 0x00 0x100>,
823 <0x05 0x00000000 0x01 0x00000000>;
827 cdns,trigger-address = <0x0>;
828 #address-cells = <0x1>;
829 #size-cells = <0x0>;
841 reg = <0x00 0x2a000000 0x00 0x1000>;
847 reg = <0x00 0x29020000 0x00 0x200>;
858 reg = <0x00 0x29030000 0x00 0x200>;
869 reg = <0x00 0x29040000 0x00 0x200>;
880 reg = <0x00 0x29050000 0x00 0x200>;
891 reg = <0x00 0x29060000 0x00 0x200>;
901 reg = <0x00 0x29070000 0x00 0x200>;
911 ti,cluster-mode = <0>;
914 ranges = <0x78000000 0x00 0x78000000 0x10000>,
915 <0x78100000 0x00 0x78100000 0x10000>,
916 <0x78200000 0x00 0x78200000 0x08000>,
917 <0x78300000 0x00 0x78300000 0x08000>;
922 reg = <0x78000000 0x00010000>,
923 <0x78100000 0x00010000>;
927 ti,sci-proc-ids = <0x01 0xff>;
937 reg = <0x78200000 0x00008000>,
938 <0x78300000 0x00008000>;
942 ti,sci-proc-ids = <0x02 0xff>;
953 ti,cluster-mode = <0>;
956 ranges = <0x78400000 0x00 0x78400000 0x10000>,
957 <0x78500000 0x00 0x78500000 0x10000>,
958 <0x78600000 0x00 0x78600000 0x08000>,
959 <0x78700000 0x00 0x78700000 0x08000>;
964 reg = <0x78400000 0x00010000>,
965 <0x78500000 0x00010000>;
969 ti,sci-proc-ids = <0x06 0xff>;
979 reg = <0x78600000 0x00008000>,
980 <0x78700000 0x00008000>;
984 ti,sci-proc-ids = <0x07 0xff>;
998 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>;
1003 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
1010 reg = <0x0f000000 0x00010000>;
1012 resets = <&serdes_wiz0 0>;
1024 #size-cells = <0>;
1031 reg = <0x00 0x0f102000 0x00 0x1000>,
1032 <0x00 0x0f100000 0x00 0x400>,
1033 <0x00 0x0d000000 0x00 0x00800000>,
1034 <0x00 0x68000000 0x00 0x00001000>;
1039 ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
1043 clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
1047 bus-range = <0x0 0xff>;
1049 vendor-id = <0x104c>;
1050 device-id = <0xb010>;
1051 msi-map = <0x0 &gic_its 0x0 0x10000>;
1052 ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
1053 <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
1054 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
1061 reg = <0x0 0x23000000 0x0 0x100>;
1063 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
1071 reg = <0x0 0x23010000 0x0 0x100>;
1073 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
1081 reg = <0x0 0x23020000 0x0 0x100>;
1083 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
1091 reg = <0x0 0x23030000 0x0 0x100>;
1093 clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>;
1101 reg = <0x0 0x23040000 0x0 0x100>;
1103 clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>;
1111 reg = <0x0 0x23050000 0x0 0x100>;
1113 clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>;
1121 reg = <0x0 0x23060000 0x0 0x100>;
1123 clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>;
1131 reg = <0x0 0x23070000 0x0 0x100>;
1133 clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>;
1141 reg = <0x0 0x23080000 0x0 0x100>;
1143 clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>;
1151 reg = <0x0 0x23100000 0x0 0x60>;
1153 clocks = <&k3_clks 51 0>;
1161 reg = <0x0 0x23110000 0x0 0x60>;
1163 clocks = <&k3_clks 52 0>;
1171 reg = <0x0 0x23120000 0x0 0x60>;
1173 clocks = <&k3_clks 53 0>;
1180 reg = <0x00 0x23200000 0x00 0x100>;
1182 clocks = <&k3_clks 59 0>;
1189 reg = <0x00 0x23210000 0x00 0x100>;
1191 clocks = <&k3_clks 60 0>;
1198 reg = <0x00 0x23220000 0x00 0x100>;
1200 clocks = <&k3_clks 62 0>;
1207 reg = <0x00 0xe000000 0x00 0x100>;
1208 clocks = <&k3_clks 125 0>;
1210 assigned-clocks = <&k3_clks 125 0>;
1216 reg = <0x00 0xe010000 0x00 0x100>;
1217 clocks = <&k3_clks 126 0>;
1219 assigned-clocks = <&k3_clks 126 0>;
1225 reg = <0x00 0x30000000 0x00 0x80000>;
1229 ranges = <0x0 0x00 0x30000000 0x80000>;
1231 icssg0_mem: memories@0 {
1232 reg = <0x0 0x2000>,
1233 <0x2000 0x2000>,
1234 <0x10000 0x10000>;
1240 reg = <0x26000 0x200>;
1243 ranges = <0x0 0x26000 0x2000>;
1247 #size-cells = <0>;
1250 reg = <0x3c>;
1251 #clock-cells = <0>;
1252 clocks = <&k3_clks 81 0>, /* icssg0_core_clk */
1259 reg = <0x30>;
1260 #clock-cells = <0>;
1271 reg = <0x2e000 0x1000>;
1277 reg = <0x2f000 0x1000>;
1283 reg = <0x32000 0x100>;
1288 reg = <0x33000 0x1000>;
1293 reg = <0x2c000 0x1000>;
1298 reg = <0x20000 0x2000>;
1317 reg = <0x34000 0x3000>,
1318 <0x22000 0x100>,
1319 <0x22400 0x100>;
1329 reg = <0x4000 0x2000>,
1330 <0x23000 0x100>,
1331 <0x23400 0x100>;
1341 reg = <0xa000 0x1800>,
1342 <0x25000 0x100>,
1343 <0x25400 0x100>;
1350 reg = <0x38000 0x3000>,
1351 <0x24000 0x100>,
1352 <0x24400 0x100>;
1362 reg = <0x6000 0x2000>,
1363 <0x23800 0x100>,
1364 <0x23c00 0x100>;
1374 reg = <0xc000 0x1800>,
1375 <0x25800 0x100>,
1376 <0x25c00 0x100>;
1383 reg = <0x32400 0x100>;
1387 #size-cells = <0>;
1395 reg = <0x00 0x30080000 0x00 0x80000>;
1399 ranges = <0x0 0x00 0x30080000 0x80000>;
1401 icssg1_mem: memories@0 {
1402 reg = <0x0 0x2000>,
1403 <0x2000 0x2000>,
1404 <0x10000 0x10000>;
1410 reg = <0x26000 0x200>;
1413 ranges = <0x0 0x26000 0x2000>;
1417 #size-cells = <0>;
1420 reg = <0x3c>;
1421 #clock-cells = <0>;
1422 clocks = <&k3_clks 82 0>, /* icssg1_core_clk */
1429 reg = <0x30>;
1430 #clock-cells = <0>;
1441 reg = <0x2e000 0x1000>;
1447 reg = <0x2f000 0x1000>;
1453 reg = <0x32000 0x100>;
1458 reg = <0x33000 0x1000>;
1463 reg = <0x2c000 0x1000>;
1468 reg = <0x20000 0x2000>;
1487 reg = <0x34000 0x4000>,
1488 <0x22000 0x100>,
1489 <0x22400 0x100>;
1499 reg = <0x4000 0x2000>,
1500 <0x23000 0x100>,
1501 <0x23400 0x100>;
1511 reg = <0xa000 0x1800>,
1512 <0x25000 0x100>,
1513 <0x25400 0x100>;
1520 reg = <0x38000 0x4000>,
1521 <0x24000 0x100>,
1522 <0x24400 0x100>;
1532 reg = <0x6000 0x2000>,
1533 <0x23800 0x100>,
1534 <0x23c00 0x100>;
1544 reg = <0xc000 0x1800>,
1545 <0x25800 0x100>,
1546 <0x25c00 0x100>;
1553 reg = <0x32400 0x100>;
1555 #size-cells = <0>;
1556 clocks = <&k3_clks 82 0>;
1565 reg = <0x00 0x20701000 0x00 0x200>,
1566 <0x00 0x20708000 0x00 0x8000>;
1569 clocks = <&k3_clks 98 5>, <&k3_clks 98 0>;
1574 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1580 reg = <0x00 0x20711000 0x00 0x200>,
1581 <0x00 0x20718000 0x00 0x8000>;
1584 clocks = <&k3_clks 99 5>, <&k3_clks 99 0>;
1589 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1595 reg = <0x00 0x40900000 0x00 0x1200>;
1599 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
1600 dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>,
1601 <&main_pktdma 0x4003 0>;
1606 reg = <0x00 0x40910000 0x00 0x7d>;
1615 clocks = <&k3_clks 80 0>;
1617 reg = <0x00 0x3b000000 0x00 0x400>,
1618 <0x00 0x50000000 0x00 0x8000000>;
1634 reg = <0x00 0x25010000 0x00 0x2000>;
1637 clocks = <&k3_clks 54 0>;
1644 reg = <0x00 0xb00000 0x00 0x400>,
1645 <0x00 0xb01000 0x00 0x400>;