Lines Matching +full:omap4 +full:- +full:mcspi
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "pinctrl-single";
12 #pinctrl-cells = <1>;
13 pinctrl-single,register-width = <32>;
14 pinctrl-single,function-mask = <0xffffffff>;
15 pinctrl-single,gpio-range =
19 bootph-all;
21 mcu_pmx_range: gpio-range {
22 #pinctrl-single,gpio-range-cells = <3>;
27 compatible = "ti,j721e-esm";
29 bootph-pre-ram;
31 ti,esm-pins = <0>, <1>, <2>, <85>, <86>;
40 compatible = "ti,am654-timer";
43 clock-names = "fck";
44 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
45 ti,timer-pwm;
50 compatible = "ti,am654-timer";
53 clock-names = "fck";
54 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
55 ti,timer-pwm;
60 compatible = "ti,am654-timer";
63 clock-names = "fck";
64 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
65 ti,timer-pwm;
70 compatible = "ti,am654-timer";
73 clock-names = "fck";
74 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
75 ti,timer-pwm;
80 compatible = "ti,am64-uart", "ti,am654-uart";
83 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
85 clock-names = "fclk";
90 compatible = "ti,am64-i2c", "ti,omap4-i2c";
93 #address-cells = <1>;
94 #size-cells = <0>;
95 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
97 clock-names = "fck";
102 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
105 #address-cells = <1>;
106 #size-cells = <0>;
107 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
113 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
116 #address-cells = <1>;
117 #size-cells = <0>;
118 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
123 mcu_gpio_intr: interrupt-controller@4210000 {
124 compatible = "ti,sci-intr";
126 ti,intr-trigger-type = <1>;
127 interrupt-controller;
128 interrupt-parent = <&gic500>;
129 #interrupt-cells = <1>;
131 ti,sci-dev-id = <5>;
132 ti,interrupt-ranges = <0 104 4>;
136 compatible = "ti,am64-gpio", "ti,keystone-gpio";
138 gpio-controller;
139 #gpio-cells = <2>;
140 interrupt-parent = <&mcu_gpio_intr>;
142 interrupt-controller;
143 #interrupt-cells = <2>;
145 ti,davinci-gpio-unbanked = <0>;
146 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
148 clock-names = "gpio";
149 gpio-ranges = <&mcu_pmx0 0 0 21>, <&mcu_pmx0 21 23 1>,
154 compatible = "ti,j7-rti-wdt";
157 power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
158 assigned-clocks = <&k3_clks 131 0>;
159 assigned-clock-parents = <&k3_clks 131 2>;
168 reg-names = "m_can", "message_ram";
169 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
171 clock-names = "hclk", "cclk";
172 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
175 interrupt-names = "int0", "int1";
183 reg-names = "m_can", "message_ram";
184 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
186 clock-names = "hclk", "cclk";
187 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
190 interrupt-names = "int0", "int1";
195 compatible = "ti,am62-r5fss";
196 #address-cells = <1>;
197 #size-cells = <1>;
200 power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>;
204 compatible = "ti,am62-r5f";
207 reg-names = "atcm", "btcm";
209 ti,sci-dev-id = <9>;
210 ti,sci-proc-ids = <0x03 0xff>;
212 firmware-name = "am62p-mcu-r5f0_0-fw";
213 ti,atcm-enable = <0>;
214 ti,btcm-enable = <1>;