Lines Matching +full:0 +full:x2430000
22 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
23 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
24 <0x01 0x00000000 0x00 0x2000>, /* GICC */
25 <0x01 0x00010000 0x00 0x1000>, /* GICH */
26 <0x01 0x00020000 0x00 0x2000>; /* GICV */
35 reg = <0x00 0x01820000 0x00 0x10000>;
36 socionext,synquacer-pre-its = <0x1000000 0x400000>;
44 reg = <0x00 0x00100000 0x00 0x20000>;
47 ranges = <0x00 0x00 0x00100000 0x20000>;
51 reg = <0x4044 0x8>;
57 reg = <0x4130 0x4>;
67 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
76 reg = <0x00 0x4d000000 0x00 0x80000>,
77 <0x00 0x4a600000 0x00 0x80000>,
78 <0x00 0x4a400000 0x00 0x80000>;
86 reg = <0x00 0x48000000 0x00 0x100000>;
87 #interrupt-cells = <0>;
98 reg = <0x00 0x485c0100 0x00 0x100>,
99 <0x00 0x4c000000 0x00 0x20000>,
100 <0x00 0x4a820000 0x00 0x20000>,
101 <0x00 0x4aa40000 0x00 0x20000>,
102 <0x00 0x4bc00000 0x00 0x100000>,
103 <0x00 0x48600000 0x00 0x8000>,
104 <0x00 0x484a4000 0x00 0x2000>,
105 <0x00 0x484c2000 0x00 0x2000>,
106 <0x00 0x48420000 0x00 0x2000>;
114 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
115 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
116 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
122 reg = <0x00 0x485c0000 0x00 0x100>,
123 <0x00 0x4a800000 0x00 0x20000>,
124 <0x00 0x4aa00000 0x00 0x20000>,
125 <0x00 0x4b800000 0x00 0x200000>,
126 <0x00 0x485e0000 0x00 0x10000>,
127 <0x00 0x484a0000 0x00 0x2000>,
128 <0x00 0x484c0000 0x00 0x2000>,
129 <0x00 0x48430000 0x00 0x1000>;
138 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
139 <0x24>, /* CPSW_TX_CHAN */
140 <0x25>, /* SAUL_TX_0_CHAN */
141 <0x26>; /* SAUL_TX_1_CHAN */
142 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
143 <0x11>, /* RING_CPSW_TX_CHAN */
144 <0x12>, /* RING_SAUL_TX_0_CHAN */
145 <0x13>; /* RING_SAUL_TX_1_CHAN */
146 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
147 <0x2b>, /* CPSW_RX_CHAN */
148 <0x2d>, /* SAUL_RX_0_CHAN */
149 <0x2f>, /* SAUL_RX_1_CHAN */
150 <0x31>, /* SAUL_RX_2_CHAN */
151 <0x33>; /* SAUL_RX_3_CHAN */
152 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
153 <0x2c>, /* FLOW_CPSW_RX_CHAN */
154 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
155 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
161 ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x408000>;
169 reg = <0x00 0x4e400000 0x00 0x8000>;
170 #interrupt-cells = <0>;
177 ti,interrupt-ranges = <0 237 8>;
183 reg = <0x00 0x4e230000 0x00 0x100>,
184 <0x00 0x4e180000 0x00 0x8000>,
185 <0x00 0x4e100000 0x00 0x10000>;
192 ti,sci-rm-range-rchan = <0x21>;
203 reg = <0x00 0x44043000 0x00 0xfe0>;
227 reg = <0x00 0x40900000 0x00 0x1200>;
230 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
231 <&main_pktdma 0x7507 0>;
239 reg = <0x00 0x43600000 0x00 0x10000>,
240 <0x00 0x44880000 0x00 0x20000>,
241 <0x00 0x44860000 0x00 0x20000>;
253 reg = <0x00 0xf4000 0x00 0x2ac>;
256 pinctrl-single,function-mask = <0xffffffff>;
262 reg = <0x00 0x420000 0x00 0x1000>;
270 reg = <0x00 0x2400000 0x00 0x400>;
283 reg = <0x00 0x2410000 0x00 0x400>;
295 reg = <0x00 0x2420000 0x00 0x400>;
307 reg = <0x00 0x2430000 0x00 0x400>;
319 reg = <0x00 0x2440000 0x00 0x400>;
331 reg = <0x00 0x2450000 0x00 0x400>;
343 reg = <0x00 0x2460000 0x00 0x400>;
355 reg = <0x00 0x2470000 0x00 0x400>;
367 reg = <0x00 0x02800000 0x00 0x100>;
370 clocks = <&k3_clks 146 0>;
377 reg = <0x00 0x02810000 0x00 0x100>;
380 clocks = <&k3_clks 152 0>;
387 reg = <0x00 0x02820000 0x00 0x100>;
390 clocks = <&k3_clks 153 0>;
397 reg = <0x00 0x02830000 0x00 0x100>;
400 clocks = <&k3_clks 154 0>;
407 reg = <0x00 0x02840000 0x00 0x100>;
410 clocks = <&k3_clks 155 0>;
417 reg = <0x00 0x02850000 0x00 0x100>;
420 clocks = <&k3_clks 156 0>;
427 reg = <0x00 0x02860000 0x00 0x100>;
430 clocks = <&k3_clks 158 0>;
437 reg = <0x00 0x20000000 0x00 0x100>;
440 #size-cells = <0>;
449 reg = <0x00 0x20010000 0x00 0x100>;
452 #size-cells = <0>;
461 reg = <0x00 0x20020000 0x00 0x100>;
464 #size-cells = <0>;
473 reg = <0x00 0x20030000 0x00 0x100>;
476 #size-cells = <0>;
485 reg = <0x00 0x20100000 0x00 0x400>;
488 #size-cells = <0>;
490 clocks = <&k3_clks 141 0>;
496 reg = <0x00 0x20110000 0x00 0x400>;
499 #size-cells = <0>;
501 clocks = <&k3_clks 142 0>;
507 reg = <0x00 0x20120000 0x00 0x400>;
510 #size-cells = <0>;
512 clocks = <&k3_clks 143 0>;
518 reg = <0x00 0x00a00000 0x00 0x800>;
525 ti,interrupt-ranges = <0 32 16>;
530 reg = <0x00 0x00600000 0x00 0x100>;
538 ti,davinci-gpio-unbanked = <0>;
540 clocks = <&k3_clks 77 0>;
546 reg = <0x00 0x00601000 0x00 0x100>;
554 ti,davinci-gpio-unbanked = <0>;
556 clocks = <&k3_clks 78 0>;
562 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
573 ti,clkbuf-sel = <0x7>;
574 ti,strobe-sel = <0x77>;
575 ti,trm-icp = <0x8>;
576 ti,otap-del-sel-legacy = <0x1>;
577 ti,otap-del-sel-mmc-hs = <0x1>;
578 ti,otap-del-sel-ddr52 = <0x6>;
579 ti,otap-del-sel-hs200 = <0x8>;
580 ti,otap-del-sel-hs400 = <0x5>;
581 ti,itap-del-sel-legacy = <0x10>;
582 ti,itap-del-sel-mmc-hs = <0xa>;
583 ti,itap-del-sel-ddr52 = <0x3>;
589 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
595 ti,clkbuf-sel = <0x7>;
596 ti,otap-del-sel-legacy = <0x0>;
597 ti,otap-del-sel-sd-hs = <0x0>;
598 ti,otap-del-sel-sdr12 = <0xf>;
599 ti,otap-del-sel-sdr25 = <0xf>;
600 ti,otap-del-sel-sdr50 = <0xc>;
601 ti,otap-del-sel-ddr50 = <0x9>;
602 ti,otap-del-sel-sdr104 = <0x6>;
603 ti,itap-del-sel-legacy = <0x0>;
604 ti,itap-del-sel-sd-hs = <0x0>;
605 ti,itap-del-sel-sdr12 = <0x0>;
606 ti,itap-del-sel-sdr25 = <0x0>;
612 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
618 ti,clkbuf-sel = <0x7>;
619 ti,otap-del-sel-legacy = <0x0>;
620 ti,otap-del-sel-sd-hs = <0x0>;
621 ti,otap-del-sel-sdr12 = <0xf>;
622 ti,otap-del-sel-sdr25 = <0xf>;
623 ti,otap-del-sel-sdr50 = <0xc>;
624 ti,otap-del-sel-ddr50 = <0x9>;
625 ti,otap-del-sel-sdr104 = <0x6>;
626 ti,itap-del-sel-legacy = <0x0>;
627 ti,itap-del-sel-sd-hs = <0x0>;
628 ti,itap-del-sel-sdr12 = <0x0>;
629 ti,itap-del-sel-sdr25 = <0x0>;
635 reg = <0x00 0x0f900000 0x00 0x800>,
636 <0x00 0x0f908000 0x00 0x400>;
639 ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>;
648 reg = <0x00 0x31000000 0x00 0x50000>;
649 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
650 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
661 reg = <0x00 0x0fc00000 0x00 0x70000>;
668 reg = <0x00 0x0fc40000 0x00 0x100>,
669 <0x05 0x00000000 0x01 0x00000000>;
673 cdns,trigger-address = <0x0>;
680 #size-cells = <0>;
689 reg = <0x00 0x08000000 0x00 0x200000>;
691 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
692 clocks = <&k3_clks 13 0>;
699 dmas = <&main_pktdma 0xc600 15>,
700 <&main_pktdma 0xc601 15>,
701 <&main_pktdma 0xc602 15>,
702 <&main_pktdma 0xc603 15>,
703 <&main_pktdma 0xc604 15>,
704 <&main_pktdma 0xc605 15>,
705 <&main_pktdma 0xc606 15>,
706 <&main_pktdma 0xc607 15>,
707 <&main_pktdma 0x4600 15>;
713 #size-cells = <0>;
721 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
737 reg = <0x00 0xf00 0x00 0x100>;
739 #size-cells = <0>;
740 clocks = <&k3_clks 13 0>;
748 reg = <0x00 0x3d000 0x00 0x400>;
760 reg = <0x00 0x2a000000 0x00 0x1000>;
766 reg = <0x00 0x29000000 0x00 0x200>;
775 reg = <0x00 0x29010000 0x00 0x200>;
784 reg = <0x00 0x29020000 0x00 0x200>;
793 reg = <0x00 0x29030000 0x00 0x200>;
803 reg = <0x00 0x23100000 0x00 0x100>;
805 clocks = <&k3_clks 51 0>;
813 reg = <0x00 0x23110000 0x00 0x100>;
815 clocks = <&k3_clks 52 0>;
823 reg = <0x00 0x23120000 0x00 0x100>;
825 clocks = <&k3_clks 53 0>;
832 reg = <0x00 0x23200000 0x00 0x100>;
834 clocks = <&k3_clks 59 0>;
841 reg = <0x00 0x23210000 0x00 0x100>;
843 clocks = <&k3_clks 60 0>;
850 reg = <0x00 0x23220000 0x00 0x100>;
852 clocks = <&k3_clks 62 0>;
859 reg = <0x00 0x20701000 0x00 0x200>,
860 <0x00 0x20708000 0x00 0x8000>;
868 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
874 reg = <0x00 0x20711000 0x00 0x200>,
875 <0x00 0x20718000 0x00 0x8000>;
883 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
889 reg = <0x00 0x0e000000 0x00 0x100>;
890 clocks = <&k3_clks 125 0>;
892 assigned-clocks = <&k3_clks 125 0>;
898 reg = <0x00 0x0e010000 0x00 0x100>;
899 clocks = <&k3_clks 126 0>;
901 assigned-clocks = <&k3_clks 126 0>;
907 reg = <0x00 0x0e020000 0x00 0x100>;
908 clocks = <&k3_clks 127 0>;
910 assigned-clocks = <&k3_clks 127 0>;
916 reg = <0x00 0x0e030000 0x00 0x100>;
917 clocks = <&k3_clks 128 0>;
919 assigned-clocks = <&k3_clks 128 0>;
925 reg = <0x00 0x0e0f0000 0x00 0x100>;
926 clocks = <&k3_clks 130 0>;
928 assigned-clocks = <&k3_clks 130 0>;
935 reg = <0x00 0x23000000 0x00 0x100>;
937 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
945 reg = <0x00 0x23010000 0x00 0x100>;
947 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
955 reg = <0x00 0x23020000 0x00 0x100>;
957 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
964 reg = <0x00 0x02b00000 0x00 0x2000>,
965 <0x00 0x02b08000 0x00 0x400>;
971 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
974 clocks = <&k3_clks 190 0>;
976 assigned-clocks = <&k3_clks 190 0>;
984 reg = <0x00 0x02b10000 0x00 0x2000>,
985 <0x00 0x02b18000 0x00 0x400>;
991 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
994 clocks = <&k3_clks 191 0>;
996 assigned-clocks = <&k3_clks 191 0>;
1004 reg = <0x00 0x02b20000 0x00 0x2000>,
1005 <0x00 0x02b28000 0x00 0x400>;
1011 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
1014 clocks = <&k3_clks 192 0>;
1016 assigned-clocks = <&k3_clks 192 0>;
1024 reg = <0x00 0x30102000 0x00 0x1000>;
1028 dmas = <&main_bcdma_csi 0 0x5000 0>;
1035 reg = <0x00 0x30101000 0x00 0x1000>;
1036 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
1037 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
1045 #size-cells = <0>;
1047 csi0_port0: port@0 {
1048 reg = <0>;
1077 reg = <0x00 0x30110000 0x00 0x1100>;
1078 #phy-cells = <0>;
1085 reg = <0x00 0x30210000 0x00 0x10000>;