Lines Matching +full:0 +full:xfa00000
11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
21 <0x01 0x00000000 0x00 0x2000>, /* GICC */
22 <0x01 0x00010000 0x00 0x1000>, /* GICH */
23 <0x01 0x00020000 0x00 0x2000>; /* GICV */
37 reg = <0x00 0x01820000 0x00 0x10000>;
38 socionext,synquacer-pre-its = <0x1000000 0x400000>;
48 ranges = <0x00 0x00 0x00100000 0x20000>;
52 reg = <0x4044 0x8>;
58 reg = <0x4130 0x4>;
64 reg = <0x82e0 0x4>;
65 clocks = <&k3_clks 157 0>;
66 assigned-clocks = <&k3_clks 157 0>;
68 #clock-cells = <0>;
73 reg = <0x82e4 0x4>;
77 #clock-cells = <0>;
86 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>;
92 reg = <0x00 0x4d000000 0x00 0x80000>,
93 <0x00 0x4a600000 0x00 0x80000>,
94 <0x00 0x4a400000 0x00 0x80000>;
103 reg = <0x00 0x48000000 0x00 0x100000>;
104 #interrupt-cells = <0>;
116 reg = <0x00 0x485c0100 0x00 0x100>,
117 <0x00 0x4c000000 0x00 0x20000>,
118 <0x00 0x4a820000 0x00 0x20000>,
119 <0x00 0x4aa40000 0x00 0x20000>,
120 <0x00 0x4bc00000 0x00 0x100000>,
121 <0x00 0x48600000 0x00 0x8000>,
122 <0x00 0x484a4000 0x00 0x2000>,
123 <0x00 0x484c2000 0x00 0x2000>,
124 <0x00 0x48420000 0x00 0x2000>;
131 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
132 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
133 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
138 reg = <0x00 0x485c0000 0x00 0x100>,
139 <0x00 0x4a800000 0x00 0x20000>,
140 <0x00 0x4aa00000 0x00 0x20000>,
141 <0x00 0x4b800000 0x00 0x200000>,
142 <0x00 0x485e0000 0x00 0x10000>,
143 <0x00 0x484a0000 0x00 0x2000>,
144 <0x00 0x484c0000 0x00 0x2000>,
145 <0x00 0x48430000 0x00 0x1000>;
152 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
153 <0x24>, /* CPSW_TX_CHAN */
154 <0x25>, /* SAUL_TX_0_CHAN */
155 <0x26>; /* SAUL_TX_1_CHAN */
156 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
157 <0x11>, /* RING_CPSW_TX_CHAN */
158 <0x12>, /* RING_SAUL_TX_0_CHAN */
159 <0x13>; /* RING_SAUL_TX_1_CHAN */
160 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
161 <0x2b>, /* CPSW_RX_CHAN */
162 <0x2d>, /* SAUL_RX_0_CHAN */
163 <0x2f>, /* SAUL_RX_1_CHAN */
164 <0x31>, /* SAUL_RX_2_CHAN */
165 <0x33>; /* SAUL_RX_3_CHAN */
166 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
167 <0x2c>, /* FLOW_CPSW_RX_CHAN */
168 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
169 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
178 ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x300000>;
184 reg = <0x00 0x4e0a0000 0x00 0x8000>;
185 #interrupt-cells = <0>;
191 ti,interrupt-ranges = <0 237 8>;
198 reg = <0x00 0x4e230000 0x00 0x100>,
199 <0x00 0x4e180000 0x00 0x8000>,
200 <0x00 0x4e100000 0x00 0x10000>;
206 ti,sci-rm-range-rchan = <0x21>;
213 reg = <0x00 0x44043000 0x00 0xfe0>;
238 reg = <0x00 0x40900000 0x00 0x1200>;
239 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
240 <&main_pktdma 0x7507 0>;
248 reg = <0x00 0x43600000 0x00 0x10000>,
249 <0x00 0x44880000 0x00 0x20000>,
250 <0x00 0x44860000 0x00 0x20000>;
261 reg = <0x00 0xf4000 0x00 0x2ac>;
264 pinctrl-single,function-mask = <0xffffffff>;
269 reg = <0x0 0x420000 0x0 0x1000>;
277 reg = <0x00 0x2400000 0x00 0x400>;
289 reg = <0x00 0x2410000 0x00 0x400>;
301 reg = <0x00 0x2420000 0x00 0x400>;
313 reg = <0x00 0x2430000 0x00 0x400>;
325 reg = <0x00 0x2440000 0x00 0x400>;
337 reg = <0x00 0x2450000 0x00 0x400>;
349 reg = <0x00 0x2460000 0x00 0x400>;
361 reg = <0x00 0x2470000 0x00 0x400>;
373 reg = <0x00 0x02800000 0x00 0x100>;
376 clocks = <&k3_clks 146 0>;
383 reg = <0x00 0x02810000 0x00 0x100>;
386 clocks = <&k3_clks 152 0>;
393 reg = <0x00 0x02820000 0x00 0x100>;
396 clocks = <&k3_clks 153 0>;
403 reg = <0x00 0x02830000 0x00 0x100>;
406 clocks = <&k3_clks 154 0>;
413 reg = <0x00 0x02840000 0x00 0x100>;
416 clocks = <&k3_clks 155 0>;
423 reg = <0x00 0x02850000 0x00 0x100>;
426 clocks = <&k3_clks 156 0>;
433 reg = <0x00 0x02860000 0x00 0x100>;
436 clocks = <&k3_clks 158 0>;
443 reg = <0x00 0x20000000 0x00 0x100>;
446 #size-cells = <0>;
455 reg = <0x00 0x20010000 0x00 0x100>;
458 #size-cells = <0>;
467 reg = <0x00 0x20020000 0x00 0x100>;
470 #size-cells = <0>;
479 reg = <0x00 0x20030000 0x00 0x100>;
482 #size-cells = <0>;
491 reg = <0x00 0x20100000 0x00 0x400>;
494 #size-cells = <0>;
496 clocks = <&k3_clks 141 0>;
502 reg = <0x00 0x20110000 0x00 0x400>;
505 #size-cells = <0>;
507 clocks = <&k3_clks 142 0>;
513 reg = <0x00 0x20120000 0x00 0x400>;
516 #size-cells = <0>;
518 clocks = <&k3_clks 143 0>;
524 reg = <0x00 0x00a00000 0x00 0x800>;
531 ti,interrupt-ranges = <0 32 16>;
537 reg = <0x00 0x00600000 0x0 0x100>;
546 ti,davinci-gpio-unbanked = <0>;
548 clocks = <&k3_clks 77 0>;
555 reg = <0x00 0x00601000 0x0 0x100>;
564 ti,davinci-gpio-unbanked = <0>;
566 clocks = <&k3_clks 78 0>;
573 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
582 ti,clkbuf-sel = <0x7>;
583 ti,otap-del-sel-legacy = <0x0>;
584 ti,otap-del-sel-mmc-hs = <0x0>;
585 ti,otap-del-sel-hs200 = <0x6>;
591 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
597 ti,clkbuf-sel = <0x7>;
598 ti,otap-del-sel-legacy = <0x0>;
599 ti,otap-del-sel-sd-hs = <0x0>;
600 ti,otap-del-sel-sdr12 = <0xf>;
601 ti,otap-del-sel-sdr25 = <0xf>;
602 ti,otap-del-sel-sdr50 = <0xc>;
603 ti,otap-del-sel-sdr104 = <0x6>;
604 ti,otap-del-sel-ddr50 = <0x9>;
605 ti,itap-del-sel-legacy = <0x0>;
606 ti,itap-del-sel-sd-hs = <0x0>;
607 ti,itap-del-sel-sdr12 = <0x0>;
608 ti,itap-del-sel-sdr25 = <0x0>;
614 reg = <0x00 0xfa20000 0x00 0x260>, <0x00 0xfa28000 0x00 0x134>;
620 ti,clkbuf-sel = <0x7>;
621 ti,otap-del-sel-legacy = <0x0>;
622 ti,otap-del-sel-sd-hs = <0x0>;
623 ti,otap-del-sel-sdr12 = <0xf>;
624 ti,otap-del-sel-sdr25 = <0xf>;
625 ti,otap-del-sel-sdr50 = <0xc>;
626 ti,otap-del-sel-sdr104 = <0x6>;
627 ti,otap-del-sel-ddr50 = <0x9>;
628 ti,itap-del-sel-legacy = <0x0>;
629 ti,itap-del-sel-sd-hs = <0x0>;
630 ti,itap-del-sel-sdr12 = <0x0>;
631 ti,itap-del-sel-sdr25 = <0x0>;
637 reg = <0x00 0x0f900000 0x00 0x800>,
638 <0x00 0x0f908000 0x00 0x400>;
641 ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>;
650 reg = <0x00 0x31000000 0x00 0x50000>;
651 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
652 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
663 reg = <0x00 0x0f910000 0x00 0x800>,
664 <0x00 0x0f918000 0x00 0x400>;
667 ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>;
676 reg = <0x00 0x31100000 0x00 0x50000>;
677 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
678 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
689 reg = <0x00 0x0fc00000 0x00 0x70000>;
697 reg = <0x00 0x0fc40000 0x00 0x100>,
698 <0x05 0x00000000 0x01 0x00000000>;
702 cdns,trigger-address = <0x0>;
709 #size-cells = <0>;
717 reg = <0x0 0x8000000 0x0 0x200000>;
719 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
720 clocks = <&k3_clks 13 0>;
727 dmas = <&main_pktdma 0xc600 15>,
728 <&main_pktdma 0xc601 15>,
729 <&main_pktdma 0xc602 15>,
730 <&main_pktdma 0xc603 15>,
731 <&main_pktdma 0xc604 15>,
732 <&main_pktdma 0xc605 15>,
733 <&main_pktdma 0xc606 15>,
734 <&main_pktdma 0xc607 15>,
735 <&main_pktdma 0x4600 15>;
741 #size-cells = <0>;
749 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
763 reg = <0x0 0xf00 0x0 0x100>;
765 #size-cells = <0>;
766 clocks = <&k3_clks 13 0>;
773 reg = <0x0 0x3d000 0x0 0x400>;
785 reg = <0x00 0x2a000000 0x00 0x1000>;
791 reg = <0x00 0x29000000 0x00 0x200>;
800 reg = <0x00 0x29010000 0x00 0x200>;
809 reg = <0x00 0x29020000 0x00 0x200>;
818 reg = <0x00 0x29030000 0x00 0x200>;
827 reg = <0x00 0x20701000 0x00 0x200>,
828 <0x00 0x20708000 0x00 0x8000>;
836 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
842 reg = <0x00 0x0e000000 0x00 0x100>;
843 clocks = <&k3_clks 125 0>;
845 assigned-clocks = <&k3_clks 125 0>;
851 reg = <0x00 0x0e010000 0x00 0x100>;
852 clocks = <&k3_clks 126 0>;
854 assigned-clocks = <&k3_clks 126 0>;
860 reg = <0x00 0x0e020000 0x00 0x100>;
861 clocks = <&k3_clks 127 0>;
863 assigned-clocks = <&k3_clks 127 0>;
869 reg = <0x00 0x0e030000 0x00 0x100>;
870 clocks = <&k3_clks 128 0>;
872 assigned-clocks = <&k3_clks 128 0>;
878 reg = <0x00 0x0e040000 0x00 0x100>;
879 clocks = <&k3_clks 205 0>;
881 assigned-clocks = <&k3_clks 205 0>;
888 reg = <0x00 0x23000000 0x00 0x100>;
890 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
898 reg = <0x00 0x23010000 0x00 0x100>;
900 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
908 reg = <0x00 0x23020000 0x00 0x100>;
910 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
918 reg = <0x00 0x23100000 0x00 0x100>;
920 clocks = <&k3_clks 51 0>;
928 reg = <0x00 0x23110000 0x00 0x100>;
930 clocks = <&k3_clks 52 0>;
938 reg = <0x00 0x23120000 0x00 0x100>;
940 clocks = <&k3_clks 53 0>;
947 reg = <0x00 0x23200000 0x00 0x100>;
949 clocks = <&k3_clks 59 0>;
956 reg = <0x00 0x23210000 0x00 0x100>;
958 clocks = <&k3_clks 60 0>;
965 reg = <0x00 0x23220000 0x00 0x100>;
967 clocks = <&k3_clks 62 0>;
974 reg = <0x00 0x02b00000 0x00 0x2000>,
975 <0x00 0x02b08000 0x00 0x400>;
981 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
984 clocks = <&k3_clks 190 0>;
986 assigned-clocks = <&k3_clks 190 0>;
994 reg = <0x00 0x02b10000 0x00 0x2000>,
995 <0x00 0x02b18000 0x00 0x400>;
1001 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
1004 clocks = <&k3_clks 191 0>;
1006 assigned-clocks = <&k3_clks 191 0>;
1014 reg = <0x00 0x02b20000 0x00 0x2000>,
1015 <0x00 0x02b28000 0x00 0x400>;
1021 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
1024 clocks = <&k3_clks 192 0>;
1026 assigned-clocks = <&k3_clks 192 0>;
1034 dmas = <&main_bcdma_csi 0 0x5000 0>;
1036 reg = <0x00 0x30102000 0x00 0x1000>;
1045 reg = <0x00 0x30101000 0x00 0x1000>;
1046 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
1047 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
1055 #size-cells = <0>;
1057 csi0_port0: port@0 {
1058 reg = <0>;
1087 reg = <0x00 0x30110000 0x00 0x1100>;
1088 #phy-cells = <0>;
1095 reg = <0x00 0x30200000 0x00 0x1000>, /* common */
1096 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
1097 <0x00 0x30206000 0x00 0x1000>, /* vid */
1098 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
1099 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
1100 <0x00 0x3020a000 0x00 0x1000>, /* vp1: Tied OFF in the SoC */
1101 <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */
1102 <0x00 0x30201000 0x00 0x1000>; /* common1 */
1107 <&k3_clks 186 0>,
1115 #size-cells = <0>;
1121 reg = <0x00 0x30210000 0x00 0x10000>;
1128 reg = <0x00 0xfd20000 0x00 0x100>,
1129 <0x00 0xfd20200 0x00 0x200>;
1131 clocks = <&k3_clks 201 0>;