Lines Matching +full:0 +full:xc500
11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
21 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
22 <0x01 0x00000000 0x00 0x2000>, /* GICC */
23 <0x01 0x00010000 0x00 0x1000>, /* GICH */
24 <0x01 0x00020000 0x00 0x2000>; /* GICV */
38 reg = <0x00 0x01820000 0x00 0x10000>;
39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
49 ranges = <0x00 0x00 0x00100000 0x20000>;
53 reg = <0x4044 0x8>;
59 reg = <0x4130 0x4>;
65 reg = <0x82e0 0x4>;
66 clocks = <&k3_clks 157 0>;
67 assigned-clocks = <&k3_clks 157 0>;
69 #clock-cells = <0>;
74 reg = <0x82e4 0x4>;
78 #clock-cells = <0>;
87 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>;
93 reg = <0x00 0x4d000000 0x00 0x80000>,
94 <0x00 0x4a600000 0x00 0x80000>,
95 <0x00 0x4a400000 0x00 0x80000>;
104 reg = <0x00 0x48000000 0x00 0x100000>;
105 #interrupt-cells = <0>;
117 reg = <0x00 0x485c0100 0x00 0x100>,
118 <0x00 0x4c000000 0x00 0x20000>,
119 <0x00 0x4a820000 0x00 0x20000>,
120 <0x00 0x4aa40000 0x00 0x20000>,
121 <0x00 0x4bc00000 0x00 0x100000>,
122 <0x00 0x48600000 0x00 0x8000>,
123 <0x00 0x484a4000 0x00 0x2000>,
124 <0x00 0x484c2000 0x00 0x2000>,
125 <0x00 0x48420000 0x00 0x2000>;
132 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
133 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
134 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
139 reg = <0x00 0x485c0000 0x00 0x100>,
140 <0x00 0x4a800000 0x00 0x20000>,
141 <0x00 0x4aa00000 0x00 0x20000>,
142 <0x00 0x4b800000 0x00 0x200000>,
143 <0x00 0x485e0000 0x00 0x10000>,
144 <0x00 0x484a0000 0x00 0x2000>,
145 <0x00 0x484c0000 0x00 0x2000>,
146 <0x00 0x48430000 0x00 0x1000>;
153 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
154 <0x24>, /* CPSW_TX_CHAN */
155 <0x25>, /* SAUL_TX_0_CHAN */
156 <0x26>; /* SAUL_TX_1_CHAN */
157 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
158 <0x11>, /* RING_CPSW_TX_CHAN */
159 <0x12>, /* RING_SAUL_TX_0_CHAN */
160 <0x13>; /* RING_SAUL_TX_1_CHAN */
161 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
162 <0x2b>, /* CPSW_RX_CHAN */
163 <0x2d>, /* SAUL_RX_0_CHAN */
164 <0x2f>, /* SAUL_RX_1_CHAN */
165 <0x31>, /* SAUL_RX_2_CHAN */
166 <0x33>; /* SAUL_RX_3_CHAN */
167 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
168 <0x2c>, /* FLOW_CPSW_RX_CHAN */
169 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
170 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
179 ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x300000>;
185 reg = <0x00 0x4e0a0000 0x00 0x8000>;
186 #interrupt-cells = <0>;
192 ti,interrupt-ranges = <0 237 8>;
199 reg = <0x00 0x4e230000 0x00 0x100>,
200 <0x00 0x4e180000 0x00 0x8000>,
201 <0x00 0x4e100000 0x00 0x10000>;
207 ti,sci-rm-range-rchan = <0x21>;
214 reg = <0x00 0x44043000 0x00 0xfe0>;
239 reg = <0x00 0x40900000 0x00 0x1200>;
240 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
241 <&main_pktdma 0x7507 0>;
249 reg = <0x00 0x43600000 0x00 0x10000>,
250 <0x00 0x44880000 0x00 0x20000>,
251 <0x00 0x44860000 0x00 0x20000>;
262 reg = <0x00 0xf4000 0x00 0x2ac>;
265 pinctrl-single,function-mask = <0xffffffff>;
270 reg = <0x0 0x420000 0x0 0x1000>;
278 reg = <0x00 0x2400000 0x00 0x400>;
290 reg = <0x00 0x2410000 0x00 0x400>;
302 reg = <0x00 0x2420000 0x00 0x400>;
314 reg = <0x00 0x2430000 0x00 0x400>;
326 reg = <0x00 0x2440000 0x00 0x400>;
338 reg = <0x00 0x2450000 0x00 0x400>;
350 reg = <0x00 0x2460000 0x00 0x400>;
362 reg = <0x00 0x2470000 0x00 0x400>;
374 reg = <0x00 0x02800000 0x00 0x100>;
377 clocks = <&k3_clks 146 0>;
384 reg = <0x00 0x02810000 0x00 0x100>;
387 clocks = <&k3_clks 152 0>;
394 reg = <0x00 0x02820000 0x00 0x100>;
397 clocks = <&k3_clks 153 0>;
404 reg = <0x00 0x02830000 0x00 0x100>;
407 clocks = <&k3_clks 154 0>;
414 reg = <0x00 0x02840000 0x00 0x100>;
417 clocks = <&k3_clks 155 0>;
424 reg = <0x00 0x02850000 0x00 0x100>;
427 clocks = <&k3_clks 156 0>;
434 reg = <0x00 0x02860000 0x00 0x100>;
437 clocks = <&k3_clks 158 0>;
444 reg = <0x00 0x20000000 0x00 0x100>;
447 #size-cells = <0>;
456 reg = <0x00 0x20010000 0x00 0x100>;
459 #size-cells = <0>;
468 reg = <0x00 0x20020000 0x00 0x100>;
471 #size-cells = <0>;
480 reg = <0x00 0x20030000 0x00 0x100>;
483 #size-cells = <0>;
492 reg = <0x00 0x20100000 0x00 0x400>;
495 #size-cells = <0>;
497 clocks = <&k3_clks 141 0>;
503 reg = <0x00 0x20110000 0x00 0x400>;
506 #size-cells = <0>;
508 clocks = <&k3_clks 142 0>;
514 reg = <0x00 0x20120000 0x00 0x400>;
517 #size-cells = <0>;
519 clocks = <&k3_clks 143 0>;
525 reg = <0x00 0x00a00000 0x00 0x800>;
532 ti,interrupt-ranges = <0 32 16>;
538 reg = <0x00 0x00600000 0x0 0x100>;
547 ti,davinci-gpio-unbanked = <0>;
549 clocks = <&k3_clks 77 0>;
556 reg = <0x00 0x00601000 0x0 0x100>;
565 ti,davinci-gpio-unbanked = <0>;
567 clocks = <&k3_clks 78 0>;
574 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
583 ti,clkbuf-sel = <0x7>;
584 ti,otap-del-sel-legacy = <0x0>;
585 ti,otap-del-sel-mmc-hs = <0x0>;
586 ti,otap-del-sel-hs200 = <0x6>;
592 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
598 ti,clkbuf-sel = <0x7>;
599 ti,otap-del-sel-legacy = <0x0>;
600 ti,otap-del-sel-sd-hs = <0x0>;
601 ti,otap-del-sel-sdr12 = <0xf>;
602 ti,otap-del-sel-sdr25 = <0xf>;
603 ti,otap-del-sel-sdr50 = <0xc>;
604 ti,otap-del-sel-sdr104 = <0x6>;
605 ti,otap-del-sel-ddr50 = <0x9>;
606 ti,itap-del-sel-legacy = <0x0>;
607 ti,itap-del-sel-sd-hs = <0x0>;
608 ti,itap-del-sel-sdr12 = <0x0>;
609 ti,itap-del-sel-sdr25 = <0x0>;
615 reg = <0x00 0xfa20000 0x00 0x260>, <0x00 0xfa28000 0x00 0x134>;
621 ti,clkbuf-sel = <0x7>;
622 ti,otap-del-sel-legacy = <0x0>;
623 ti,otap-del-sel-sd-hs = <0x0>;
624 ti,otap-del-sel-sdr12 = <0xf>;
625 ti,otap-del-sel-sdr25 = <0xf>;
626 ti,otap-del-sel-sdr50 = <0xc>;
627 ti,otap-del-sel-sdr104 = <0x6>;
628 ti,otap-del-sel-ddr50 = <0x9>;
629 ti,itap-del-sel-legacy = <0x0>;
630 ti,itap-del-sel-sd-hs = <0x0>;
631 ti,itap-del-sel-sdr12 = <0x0>;
632 ti,itap-del-sel-sdr25 = <0x0>;
638 reg = <0x00 0x0f900000 0x00 0x800>,
639 <0x00 0x0f908000 0x00 0x400>;
642 ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>;
651 reg = <0x00 0x31000000 0x00 0x50000>;
652 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
653 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
664 reg = <0x00 0x0f910000 0x00 0x800>,
665 <0x00 0x0f918000 0x00 0x400>;
668 ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>;
677 reg = <0x00 0x31100000 0x00 0x50000>;
678 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
679 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
690 reg = <0x00 0x0fc00000 0x00 0x70000>;
698 reg = <0x00 0x0fc40000 0x00 0x100>,
699 <0x05 0x00000000 0x01 0x00000000>;
703 cdns,trigger-address = <0x0>;
710 #size-cells = <0>;
718 reg = <0x0 0x8000000 0x0 0x200000>;
720 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
721 clocks = <&k3_clks 13 0>;
728 dmas = <&main_pktdma 0xc600 15>,
729 <&main_pktdma 0xc601 15>,
730 <&main_pktdma 0xc602 15>,
731 <&main_pktdma 0xc603 15>,
732 <&main_pktdma 0xc604 15>,
733 <&main_pktdma 0xc605 15>,
734 <&main_pktdma 0xc606 15>,
735 <&main_pktdma 0xc607 15>,
736 <&main_pktdma 0x4600 15>;
742 #size-cells = <0>;
750 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
764 reg = <0x0 0xf00 0x0 0x100>;
766 #size-cells = <0>;
767 clocks = <&k3_clks 13 0>;
774 reg = <0x0 0x3d000 0x0 0x400>;
786 reg = <0x00 0x2a000000 0x00 0x1000>;
792 reg = <0x00 0x29000000 0x00 0x200>;
801 reg = <0x00 0x29010000 0x00 0x200>;
810 reg = <0x00 0x29020000 0x00 0x200>;
819 reg = <0x00 0x29030000 0x00 0x200>;
828 reg = <0x00 0x20701000 0x00 0x200>,
829 <0x00 0x20708000 0x00 0x8000>;
837 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
843 reg = <0x00 0x0e000000 0x00 0x100>;
844 clocks = <&k3_clks 125 0>;
846 assigned-clocks = <&k3_clks 125 0>;
852 reg = <0x00 0x0e010000 0x00 0x100>;
853 clocks = <&k3_clks 126 0>;
855 assigned-clocks = <&k3_clks 126 0>;
861 reg = <0x00 0x0e020000 0x00 0x100>;
862 clocks = <&k3_clks 127 0>;
864 assigned-clocks = <&k3_clks 127 0>;
870 reg = <0x00 0x0e030000 0x00 0x100>;
871 clocks = <&k3_clks 128 0>;
873 assigned-clocks = <&k3_clks 128 0>;
879 reg = <0x00 0x0e040000 0x00 0x100>;
880 clocks = <&k3_clks 205 0>;
882 assigned-clocks = <&k3_clks 205 0>;
889 reg = <0x00 0x23000000 0x00 0x100>;
891 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
899 reg = <0x00 0x23010000 0x00 0x100>;
901 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
909 reg = <0x00 0x23020000 0x00 0x100>;
911 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
919 reg = <0x00 0x23100000 0x00 0x100>;
921 clocks = <&k3_clks 51 0>;
929 reg = <0x00 0x23110000 0x00 0x100>;
931 clocks = <&k3_clks 52 0>;
939 reg = <0x00 0x23120000 0x00 0x100>;
941 clocks = <&k3_clks 53 0>;
948 reg = <0x00 0x02b00000 0x00 0x2000>,
949 <0x00 0x02b08000 0x00 0x400>;
955 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
958 clocks = <&k3_clks 190 0>;
960 assigned-clocks = <&k3_clks 190 0>;
968 reg = <0x00 0x02b10000 0x00 0x2000>,
969 <0x00 0x02b18000 0x00 0x400>;
975 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
978 clocks = <&k3_clks 191 0>;
980 assigned-clocks = <&k3_clks 191 0>;
988 reg = <0x00 0x02b20000 0x00 0x2000>,
989 <0x00 0x02b28000 0x00 0x400>;
995 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
998 clocks = <&k3_clks 192 0>;
1000 assigned-clocks = <&k3_clks 192 0>;
1008 dmas = <&main_bcdma_csi 0 0x5000 0>;
1010 reg = <0x00 0x30102000 0x00 0x1000>;
1019 reg = <0x00 0x30101000 0x00 0x1000>;
1020 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
1021 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
1029 #size-cells = <0>;
1031 csi0_port0: port@0 {
1032 reg = <0>;
1061 reg = <0x00 0x30110000 0x00 0x1100>;
1062 #phy-cells = <0>;
1069 reg = <0x00 0x30200000 0x00 0x1000>, /* common */
1070 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
1071 <0x00 0x30206000 0x00 0x1000>, /* vid */
1072 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
1073 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
1074 <0x00 0x3020a000 0x00 0x1000>, /* vp1: Tied OFF in the SoC */
1075 <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */
1076 <0x00 0x30201000 0x00 0x1000>; /* common1 */
1081 <&k3_clks 186 0>,
1089 #size-cells = <0>;
1095 reg = <0x00 0x30210000 0x00 0x10000>;
1102 reg = <0x00 0xfd20000 0x00 0x100>,
1103 <0x00 0xfd20200 0x00 0x200>;
1105 clocks = <&k3_clks 201 0>;