Lines Matching +full:omap4 +full:- +full:mcspi
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 bootph-all;
11 compatible = "pinctrl-single";
13 #pinctrl-cells = <1>;
14 pinctrl-single,register-width = <32>;
15 pinctrl-single,function-mask = <0xffffffff>;
19 bootph-pre-ram;
20 compatible = "ti,j721e-esm";
23 ti,esm-pins = <0>, <1>, <2>, <85>;
32 compatible = "ti,am654-timer";
35 clock-names = "fck";
36 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
37 ti,timer-pwm;
42 compatible = "ti,am654-timer";
45 clock-names = "fck";
46 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
47 ti,timer-pwm;
52 compatible = "ti,am654-timer";
55 clock-names = "fck";
56 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
57 ti,timer-pwm;
62 compatible = "ti,am654-timer";
65 clock-names = "fck";
66 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
67 ti,timer-pwm;
72 compatible = "ti,am64-uart", "ti,am654-uart";
75 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
77 clock-names = "fclk";
82 compatible = "ti,am64-i2c", "ti,omap4-i2c";
85 #address-cells = <1>;
86 #size-cells = <0>;
87 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
89 clock-names = "fck";
94 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
97 #address-cells = <1>;
98 #size-cells = <0>;
99 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
105 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
108 #address-cells = <1>;
109 #size-cells = <0>;
110 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
115 mcu_gpio_intr: interrupt-controller@4210000 {
116 compatible = "ti,sci-intr";
118 ti,intr-trigger-type = <1>;
119 interrupt-controller;
120 interrupt-parent = <&gic500>;
121 #interrupt-cells = <1>;
123 ti,sci-dev-id = <5>;
124 ti,interrupt-ranges = <0 104 4>;
128 compatible = "ti,am64-gpio", "ti,keystone-gpio";
130 gpio-controller;
131 #gpio-cells = <2>;
132 interrupt-parent = <&mcu_gpio_intr>;
134 interrupt-controller;
135 #interrupt-cells = <2>;
137 ti,davinci-gpio-unbanked = <0>;
138 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
140 clock-names = "gpio";
144 compatible = "ti,j7-rti-wdt";
147 power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
148 assigned-clocks = <&k3_clks 131 0>;
149 assigned-clock-parents = <&k3_clks 131 2>;
158 reg-names = "m_can", "message_ram";
159 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
161 clock-names = "hclk", "cclk";
162 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
170 reg-names = "m_can", "message_ram";
171 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
173 clock-names = "hclk", "cclk";
174 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;