Lines Matching +full:0 +full:xc500
11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
26 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
27 <0x01 0x00000000 0x00 0x2000>, /* GICC */
28 <0x01 0x00010000 0x00 0x1000>, /* GICH */
29 <0x01 0x00020000 0x00 0x2000>; /* GICV */
38 reg = <0x00 0x01820000 0x00 0x10000>;
39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
49 ranges = <0x0 0x00 0x00100000 0x20000>;
53 reg = <0x4044 0x8>;
59 reg = <0x4130 0x4>;
65 reg = <0x82e0 0x4>;
66 clocks = <&k3_clks 157 0>;
67 assigned-clocks = <&k3_clks 157 0>;
69 #clock-cells = <0>;
74 reg = <0x82e4 0x4>;
78 #clock-cells = <0>;
88 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
97 reg = <0x00 0x4d000000 0x00 0x80000>,
98 <0x00 0x4a600000 0x00 0x80000>,
99 <0x00 0x4a400000 0x00 0x80000>;
106 reg = <0x00 0x48000000 0x00 0x100000>;
107 #interrupt-cells = <0>;
119 reg = <0x00 0x485c0100 0x00 0x100>,
120 <0x00 0x4c000000 0x00 0x20000>,
121 <0x00 0x4a820000 0x00 0x20000>,
122 <0x00 0x4aa40000 0x00 0x20000>,
123 <0x00 0x4bc00000 0x00 0x100000>,
124 <0x00 0x48600000 0x00 0x8000>,
125 <0x00 0x484a4000 0x00 0x2000>,
126 <0x00 0x484c2000 0x00 0x2000>,
127 <0x00 0x48420000 0x00 0x2000>;
135 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
136 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
137 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
142 reg = <0x00 0x485c0000 0x00 0x100>,
143 <0x00 0x4a800000 0x00 0x20000>,
144 <0x00 0x4aa00000 0x00 0x20000>,
145 <0x00 0x4b800000 0x00 0x200000>,
146 <0x00 0x485e0000 0x00 0x10000>,
147 <0x00 0x484a0000 0x00 0x2000>,
148 <0x00 0x484c0000 0x00 0x2000>,
149 <0x00 0x48430000 0x00 0x1000>;
157 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
158 <0x24>, /* CPSW_TX_CHAN */
159 <0x25>, /* SAUL_TX_0_CHAN */
160 <0x26>; /* SAUL_TX_1_CHAN */
161 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
162 <0x11>, /* RING_CPSW_TX_CHAN */
163 <0x12>, /* RING_SAUL_TX_0_CHAN */
164 <0x13>; /* RING_SAUL_TX_1_CHAN */
165 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
166 <0x2b>, /* CPSW_RX_CHAN */
167 <0x2d>, /* SAUL_RX_0_CHAN */
168 <0x2f>, /* SAUL_RX_1_CHAN */
169 <0x31>, /* SAUL_RX_2_CHAN */
170 <0x33>; /* SAUL_RX_3_CHAN */
171 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
172 <0x2c>, /* FLOW_CPSW_RX_CHAN */
173 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
174 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
186 reg = <0x00 0x44043000 0x00 0xfe0>;
209 reg = <0x00 0x40900000 0x00 0x1200>;
210 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
211 <&main_pktdma 0x7507 0>;
220 reg = <0x00 0x43600000 0x00 0x10000>,
221 <0x00 0x44880000 0x00 0x20000>,
222 <0x00 0x44860000 0x00 0x20000>;
234 reg = <0x00 0xf4000 0x00 0x2ac>;
237 pinctrl-single,function-mask = <0xffffffff>;
243 reg = <0x00 0x420000 0x00 0x1000>;
251 reg = <0x00 0x2400000 0x00 0x400>;
263 reg = <0x00 0x2410000 0x00 0x400>;
275 reg = <0x00 0x2420000 0x00 0x400>;
287 reg = <0x00 0x2430000 0x00 0x400>;
299 reg = <0x00 0x2440000 0x00 0x400>;
311 reg = <0x00 0x2450000 0x00 0x400>;
323 reg = <0x00 0x2460000 0x00 0x400>;
335 reg = <0x00 0x2470000 0x00 0x400>;
347 reg = <0x00 0x02800000 0x00 0x100>;
350 clocks = <&k3_clks 146 0>;
357 reg = <0x00 0x02810000 0x00 0x100>;
360 clocks = <&k3_clks 152 0>;
367 reg = <0x00 0x02820000 0x00 0x100>;
370 clocks = <&k3_clks 153 0>;
377 reg = <0x00 0x02830000 0x00 0x100>;
380 clocks = <&k3_clks 154 0>;
387 reg = <0x00 0x02840000 0x00 0x100>;
390 clocks = <&k3_clks 155 0>;
397 reg = <0x00 0x02850000 0x00 0x100>;
400 clocks = <&k3_clks 156 0>;
407 reg = <0x00 0x02860000 0x00 0x100>;
410 clocks = <&k3_clks 158 0>;
417 reg = <0x00 0x20000000 0x00 0x100>;
420 #size-cells = <0>;
429 reg = <0x00 0x20010000 0x00 0x100>;
432 #size-cells = <0>;
441 reg = <0x00 0x20020000 0x00 0x100>;
444 #size-cells = <0>;
453 reg = <0x00 0x20030000 0x00 0x100>;
456 #size-cells = <0>;
465 reg = <0x00 0x20100000 0x00 0x400>;
468 #size-cells = <0>;
470 clocks = <&k3_clks 141 0>;
476 reg = <0x00 0x20110000 0x00 0x400>;
479 #size-cells = <0>;
481 clocks = <&k3_clks 142 0>;
487 reg = <0x00 0x20120000 0x00 0x400>;
490 #size-cells = <0>;
492 clocks = <&k3_clks 143 0>;
498 reg = <0x00 0x00a00000 0x00 0x800>;
505 ti,interrupt-ranges = <0 32 16>;
510 reg = <0x0 0x00600000 0x0 0x100>;
511 gpio-ranges = <&main_pmx0 0 0 32>,
522 ti,davinci-gpio-unbanked = <0>;
524 clocks = <&k3_clks 77 0>;
530 reg = <0x0 0x00601000 0x0 0x100>;
532 gpio-ranges = <&main_pmx0 0 94 41>,
543 ti,davinci-gpio-unbanked = <0>;
545 clocks = <&k3_clks 78 0>;
551 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
561 ti,clkbuf-sel = <0x7>;
562 ti,otap-del-sel-legacy = <0x0>;
563 ti,otap-del-sel-mmc-hs = <0x0>;
564 ti,otap-del-sel-ddr52 = <0x5>;
565 ti,otap-del-sel-hs200 = <0x5>;
566 ti,itap-del-sel-legacy = <0xa>;
567 ti,itap-del-sel-mmc-hs = <0x1>;
573 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
579 ti,clkbuf-sel = <0x7>;
580 ti,otap-del-sel-legacy = <0x8>;
581 ti,otap-del-sel-sd-hs = <0x0>;
582 ti,otap-del-sel-sdr12 = <0x0>;
583 ti,otap-del-sel-sdr25 = <0x0>;
584 ti,otap-del-sel-sdr50 = <0x8>;
585 ti,otap-del-sel-sdr104 = <0x7>;
586 ti,otap-del-sel-ddr50 = <0x4>;
587 ti,itap-del-sel-legacy = <0xa>;
588 ti,itap-del-sel-sd-hs = <0x1>;
589 ti,itap-del-sel-sdr12 = <0xa>;
590 ti,itap-del-sel-sdr25 = <0x1>;
596 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
602 ti,clkbuf-sel = <0x7>;
603 ti,otap-del-sel-legacy = <0x8>;
604 ti,otap-del-sel-sd-hs = <0x0>;
605 ti,otap-del-sel-sdr12 = <0x0>;
606 ti,otap-del-sel-sdr25 = <0x0>;
607 ti,otap-del-sel-sdr50 = <0x8>;
608 ti,otap-del-sel-sdr104 = <0x7>;
609 ti,otap-del-sel-ddr50 = <0x8>;
610 ti,itap-del-sel-legacy = <0xa>;
611 ti,itap-del-sel-sd-hs = <0xa>;
612 ti,itap-del-sel-sdr12 = <0xa>;
613 ti,itap-del-sel-sdr25 = <0x1>;
619 reg = <0x00 0x0f900000 0x00 0x800>,
620 <0x00 0x0f908000 0x00 0x400>;
623 ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>;
632 reg = <0x00 0x31000000 0x00 0x50000>;
633 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
634 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
645 reg = <0x00 0x0f910000 0x00 0x800>,
646 <0x00 0x0f918000 0x00 0x400>;
649 ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>;
658 reg = <0x00 0x31100000 0x00 0x50000>;
659 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
660 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
671 reg = <0x00 0x0fc00000 0x00 0x70000>;
678 reg = <0x00 0x0fc40000 0x00 0x100>,
679 <0x05 0x00000000 0x01 0x00000000>;
683 cdns,trigger-address = <0x0>;
690 #size-cells = <0>;
697 reg = <0x00 0x0fd00000 0x00 0x20000>;
698 clocks = <&k3_clks 187 0>;
708 reg = <0x00 0x08000000 0x00 0x200000>;
710 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
711 clocks = <&k3_clks 13 0>;
717 dmas = <&main_pktdma 0xc600 15>,
718 <&main_pktdma 0xc601 15>,
719 <&main_pktdma 0xc602 15>,
720 <&main_pktdma 0xc603 15>,
721 <&main_pktdma 0xc604 15>,
722 <&main_pktdma 0xc605 15>,
723 <&main_pktdma 0xc606 15>,
724 <&main_pktdma 0xc607 15>,
725 <&main_pktdma 0x4600 15>;
731 #size-cells = <0>;
739 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
753 reg = <0x00 0xf00 0x00 0x100>;
755 #size-cells = <0>;
756 clocks = <&k3_clks 13 0>;
764 reg = <0x00 0x3d000 0x00 0x400>;
776 reg = <0x00 0x30200000 0x00 0x1000>, /* common */
777 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
778 <0x00 0x30206000 0x00 0x1000>, /* vid */
779 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
780 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
781 <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */
782 <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */
783 <0x00 0x30201000 0x00 0x1000>; /* common1 */
796 #size-cells = <0>;
802 reg = <0x00 0x2a000000 0x00 0x1000>;
808 reg = <0x00 0x29000000 0x00 0x200>;
819 reg = <0x00 0x23100000 0x00 0x100>;
821 clocks = <&k3_clks 51 0>;
829 reg = <0x00 0x23110000 0x00 0x100>;
831 clocks = <&k3_clks 52 0>;
839 reg = <0x00 0x23120000 0x00 0x100>;
841 clocks = <&k3_clks 53 0>;
848 reg = <0x00 0x20701000 0x00 0x200>,
849 <0x00 0x20708000 0x00 0x8000>;
857 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
863 reg = <0x00 0x0e000000 0x00 0x100>;
864 clocks = <&k3_clks 125 0>;
866 assigned-clocks = <&k3_clks 125 0>;
872 reg = <0x00 0x0e010000 0x00 0x100>;
873 clocks = <&k3_clks 126 0>;
875 assigned-clocks = <&k3_clks 126 0>;
881 reg = <0x00 0x0e020000 0x00 0x100>;
882 clocks = <&k3_clks 127 0>;
884 assigned-clocks = <&k3_clks 127 0>;
890 reg = <0x00 0x0e030000 0x00 0x100>;
891 clocks = <&k3_clks 128 0>;
893 assigned-clocks = <&k3_clks 128 0>;
899 reg = <0x00 0x0e0f0000 0x00 0x100>;
900 clocks = <&k3_clks 130 0>;
902 assigned-clocks = <&k3_clks 130 0>;
909 reg = <0x00 0x23000000 0x00 0x100>;
911 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
919 reg = <0x00 0x23010000 0x00 0x100>;
921 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
929 reg = <0x00 0x23020000 0x00 0x100>;
931 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
938 reg = <0x00 0x02b00000 0x00 0x2000>,
939 <0x00 0x02b08000 0x00 0x400>;
945 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
948 clocks = <&k3_clks 190 0>;
950 assigned-clocks = <&k3_clks 190 0>;
958 reg = <0x00 0x02b10000 0x00 0x2000>,
959 <0x00 0x02b18000 0x00 0x400>;
965 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
968 clocks = <&k3_clks 191 0>;
970 assigned-clocks = <&k3_clks 191 0>;
978 reg = <0x00 0x02b20000 0x00 0x2000>,
979 <0x00 0x02b28000 0x00 0x400>;
985 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
988 clocks = <&k3_clks 192 0>;
990 assigned-clocks = <&k3_clks 192 0>;
998 dmas = <&main_bcdma 0 0x4700 0>;
1000 reg = <0x00 0x30102000 0x00 0x1000>;
1009 reg = <0x00 0x30101000 0x00 0x1000>;
1010 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
1011 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
1019 #size-cells = <0>;
1021 csi0_port0: port@0 {
1022 reg = <0>;
1051 reg = <0x00 0x30110000 0x00 0x1100>;
1052 #phy-cells = <0>;
1060 clocks = <&k3_clks 80 0>;
1062 reg = <0x00 0x03b000000 0x00 0x400>,
1063 <0x00 0x050000000 0x00 0x8000000>;
1079 reg = <0x00 0x25010000 0x00 0x2000>;
1082 clocks = <&k3_clks 54 0>;