Lines Matching +full:0 +full:x0f910000
11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
26 <0x01 0x00000000 0x00 0x2000>, /* GICC */
27 <0x01 0x00010000 0x00 0x1000>, /* GICH */
28 <0x01 0x00020000 0x00 0x2000>; /* GICV */
37 reg = <0x00 0x01820000 0x00 0x10000>;
38 socionext,synquacer-pre-its = <0x1000000 0x400000>;
48 ranges = <0x0 0x00 0x00100000 0x20000>;
52 reg = <0x4044 0x8>;
58 reg = <0x4130 0x4>;
64 reg = <0x82e0 0x4>;
65 clocks = <&k3_clks 157 0>;
66 assigned-clocks = <&k3_clks 157 0>;
68 #clock-cells = <0>;
73 reg = <0x82e4 0x4>;
77 #clock-cells = <0>;
87 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
96 reg = <0x00 0x4d000000 0x00 0x80000>,
97 <0x00 0x4a600000 0x00 0x80000>,
98 <0x00 0x4a400000 0x00 0x80000>;
105 reg = <0x00 0x48000000 0x00 0x100000>;
106 #interrupt-cells = <0>;
118 reg = <0x00 0x485c0100 0x00 0x100>,
119 <0x00 0x4c000000 0x00 0x20000>,
120 <0x00 0x4a820000 0x00 0x20000>,
121 <0x00 0x4aa40000 0x00 0x20000>,
122 <0x00 0x4bc00000 0x00 0x100000>,
123 <0x00 0x48600000 0x00 0x8000>,
124 <0x00 0x484a4000 0x00 0x2000>,
125 <0x00 0x484c2000 0x00 0x2000>,
126 <0x00 0x48420000 0x00 0x2000>;
134 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
135 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
136 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
141 reg = <0x00 0x485c0000 0x00 0x100>,
142 <0x00 0x4a800000 0x00 0x20000>,
143 <0x00 0x4aa00000 0x00 0x20000>,
144 <0x00 0x4b800000 0x00 0x200000>,
145 <0x00 0x485e0000 0x00 0x10000>,
146 <0x00 0x484a0000 0x00 0x2000>,
147 <0x00 0x484c0000 0x00 0x2000>,
148 <0x00 0x48430000 0x00 0x1000>;
156 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
157 <0x24>, /* CPSW_TX_CHAN */
158 <0x25>, /* SAUL_TX_0_CHAN */
159 <0x26>; /* SAUL_TX_1_CHAN */
160 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
161 <0x11>, /* RING_CPSW_TX_CHAN */
162 <0x12>, /* RING_SAUL_TX_0_CHAN */
163 <0x13>; /* RING_SAUL_TX_1_CHAN */
164 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
165 <0x2b>, /* CPSW_RX_CHAN */
166 <0x2d>, /* SAUL_RX_0_CHAN */
167 <0x2f>, /* SAUL_RX_1_CHAN */
168 <0x31>, /* SAUL_RX_2_CHAN */
169 <0x33>; /* SAUL_RX_3_CHAN */
170 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
171 <0x2c>, /* FLOW_CPSW_RX_CHAN */
172 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
173 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
185 reg = <0x00 0x44043000 0x00 0xfe0>;
208 reg = <0x00 0x40900000 0x00 0x1200>;
209 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
210 <&main_pktdma 0x7507 0>;
219 reg = <0x00 0x43600000 0x00 0x10000>,
220 <0x00 0x44880000 0x00 0x20000>,
221 <0x00 0x44860000 0x00 0x20000>;
233 reg = <0x00 0xf4000 0x00 0x2ac>;
236 pinctrl-single,function-mask = <0xffffffff>;
242 reg = <0x00 0x420000 0x00 0x1000>;
250 reg = <0x00 0x2400000 0x00 0x400>;
262 reg = <0x00 0x2410000 0x00 0x400>;
274 reg = <0x00 0x2420000 0x00 0x400>;
286 reg = <0x00 0x2430000 0x00 0x400>;
298 reg = <0x00 0x2440000 0x00 0x400>;
310 reg = <0x00 0x2450000 0x00 0x400>;
322 reg = <0x00 0x2460000 0x00 0x400>;
334 reg = <0x00 0x2470000 0x00 0x400>;
346 reg = <0x00 0x02800000 0x00 0x100>;
349 clocks = <&k3_clks 146 0>;
356 reg = <0x00 0x02810000 0x00 0x100>;
359 clocks = <&k3_clks 152 0>;
366 reg = <0x00 0x02820000 0x00 0x100>;
369 clocks = <&k3_clks 153 0>;
376 reg = <0x00 0x02830000 0x00 0x100>;
379 clocks = <&k3_clks 154 0>;
386 reg = <0x00 0x02840000 0x00 0x100>;
389 clocks = <&k3_clks 155 0>;
396 reg = <0x00 0x02850000 0x00 0x100>;
399 clocks = <&k3_clks 156 0>;
406 reg = <0x00 0x02860000 0x00 0x100>;
409 clocks = <&k3_clks 158 0>;
416 reg = <0x00 0x20000000 0x00 0x100>;
419 #size-cells = <0>;
428 reg = <0x00 0x20010000 0x00 0x100>;
431 #size-cells = <0>;
440 reg = <0x00 0x20020000 0x00 0x100>;
443 #size-cells = <0>;
452 reg = <0x00 0x20030000 0x00 0x100>;
455 #size-cells = <0>;
464 reg = <0x00 0x20100000 0x00 0x400>;
467 #size-cells = <0>;
469 clocks = <&k3_clks 141 0>;
475 reg = <0x00 0x20110000 0x00 0x400>;
478 #size-cells = <0>;
480 clocks = <&k3_clks 142 0>;
486 reg = <0x00 0x20120000 0x00 0x400>;
489 #size-cells = <0>;
491 clocks = <&k3_clks 143 0>;
497 reg = <0x00 0x00a00000 0x00 0x800>;
504 ti,interrupt-ranges = <0 32 16>;
509 reg = <0x0 0x00600000 0x0 0x100>;
510 gpio-ranges = <&main_pmx0 0 0 32>,
521 ti,davinci-gpio-unbanked = <0>;
523 clocks = <&k3_clks 77 0>;
529 reg = <0x0 0x00601000 0x0 0x100>;
531 gpio-ranges = <&main_pmx0 0 94 41>,
542 ti,davinci-gpio-unbanked = <0>;
544 clocks = <&k3_clks 78 0>;
550 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
560 ti,clkbuf-sel = <0x7>;
561 ti,otap-del-sel-legacy = <0x0>;
562 ti,otap-del-sel-mmc-hs = <0x0>;
563 ti,otap-del-sel-hs200 = <0x6>;
564 ti,itap-del-sel-legacy = <0x0>;
565 ti,itap-del-sel-mmc-hs = <0x0>;
571 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
577 ti,clkbuf-sel = <0x7>;
578 ti,otap-del-sel-legacy = <0x0>;
579 ti,otap-del-sel-sd-hs = <0x0>;
580 ti,otap-del-sel-sdr12 = <0xf>;
581 ti,otap-del-sel-sdr25 = <0xf>;
582 ti,otap-del-sel-sdr50 = <0xc>;
583 ti,otap-del-sel-sdr104 = <0x6>;
584 ti,otap-del-sel-ddr50 = <0x9>;
585 ti,itap-del-sel-legacy = <0x0>;
586 ti,itap-del-sel-sd-hs = <0x0>;
587 ti,itap-del-sel-sdr12 = <0x0>;
588 ti,itap-del-sel-sdr25 = <0x0>;
594 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
600 ti,clkbuf-sel = <0x7>;
601 ti,otap-del-sel-legacy = <0x0>;
602 ti,otap-del-sel-sd-hs = <0x0>;
603 ti,otap-del-sel-sdr12 = <0xf>;
604 ti,otap-del-sel-sdr25 = <0xf>;
605 ti,otap-del-sel-sdr50 = <0xc>;
606 ti,otap-del-sel-sdr104 = <0x6>;
607 ti,otap-del-sel-ddr50 = <0x9>;
608 ti,itap-del-sel-legacy = <0x0>;
609 ti,itap-del-sel-sd-hs = <0x0>;
610 ti,itap-del-sel-sdr12 = <0x0>;
611 ti,itap-del-sel-sdr25 = <0x0>;
617 reg = <0x00 0x0f900000 0x00 0x800>,
618 <0x00 0x0f908000 0x00 0x400>;
621 ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>;
630 reg = <0x00 0x31000000 0x00 0x50000>;
631 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
632 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
643 reg = <0x00 0x0f910000 0x00 0x800>,
644 <0x00 0x0f918000 0x00 0x400>;
647 ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>;
656 reg = <0x00 0x31100000 0x00 0x50000>;
657 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
658 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
669 reg = <0x00 0x0fc00000 0x00 0x70000>;
676 reg = <0x00 0x0fc40000 0x00 0x100>,
677 <0x05 0x00000000 0x01 0x00000000>;
681 cdns,trigger-address = <0x0>;
688 #size-cells = <0>;
695 reg = <0x00 0x0fd00000 0x00 0x20000>;
696 clocks = <&k3_clks 187 0>;
706 reg = <0x00 0x08000000 0x00 0x200000>;
708 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
709 clocks = <&k3_clks 13 0>;
715 dmas = <&main_pktdma 0xc600 15>,
716 <&main_pktdma 0xc601 15>,
717 <&main_pktdma 0xc602 15>,
718 <&main_pktdma 0xc603 15>,
719 <&main_pktdma 0xc604 15>,
720 <&main_pktdma 0xc605 15>,
721 <&main_pktdma 0xc606 15>,
722 <&main_pktdma 0xc607 15>,
723 <&main_pktdma 0x4600 15>;
729 #size-cells = <0>;
737 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
751 reg = <0x00 0xf00 0x00 0x100>;
753 #size-cells = <0>;
754 clocks = <&k3_clks 13 0>;
762 reg = <0x00 0x3d000 0x00 0x400>;
774 reg = <0x00 0x30200000 0x00 0x1000>, /* common */
775 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
776 <0x00 0x30206000 0x00 0x1000>, /* vid */
777 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
778 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
779 <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */
780 <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */
781 <0x00 0x30201000 0x00 0x1000>; /* common1 */
794 #size-cells = <0>;
800 reg = <0x00 0x2a000000 0x00 0x1000>;
806 reg = <0x00 0x29000000 0x00 0x200>;
817 reg = <0x00 0x23100000 0x00 0x100>;
819 clocks = <&k3_clks 51 0>;
827 reg = <0x00 0x23110000 0x00 0x100>;
829 clocks = <&k3_clks 52 0>;
837 reg = <0x00 0x23120000 0x00 0x100>;
839 clocks = <&k3_clks 53 0>;
846 reg = <0x00 0x23200000 0x00 0x100>;
848 clocks = <&k3_clks 59 0>;
855 reg = <0x00 0x23210000 0x00 0x100>;
857 clocks = <&k3_clks 60 0>;
864 reg = <0x00 0x23220000 0x00 0x100>;
866 clocks = <&k3_clks 62 0>;
873 reg = <0x00 0x20701000 0x00 0x200>,
874 <0x00 0x20708000 0x00 0x8000>;
882 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
888 reg = <0x00 0x0e000000 0x00 0x100>;
889 clocks = <&k3_clks 125 0>;
891 assigned-clocks = <&k3_clks 125 0>;
897 reg = <0x00 0x0e010000 0x00 0x100>;
898 clocks = <&k3_clks 126 0>;
900 assigned-clocks = <&k3_clks 126 0>;
906 reg = <0x00 0x0e020000 0x00 0x100>;
907 clocks = <&k3_clks 127 0>;
909 assigned-clocks = <&k3_clks 127 0>;
915 reg = <0x00 0x0e030000 0x00 0x100>;
916 clocks = <&k3_clks 128 0>;
918 assigned-clocks = <&k3_clks 128 0>;
924 reg = <0x00 0x0e0f0000 0x00 0x100>;
925 clocks = <&k3_clks 130 0>;
927 assigned-clocks = <&k3_clks 130 0>;
934 reg = <0x00 0x23000000 0x00 0x100>;
936 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
944 reg = <0x00 0x23010000 0x00 0x100>;
946 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
954 reg = <0x00 0x23020000 0x00 0x100>;
956 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
963 reg = <0x00 0x02b00000 0x00 0x2000>,
964 <0x00 0x02b08000 0x00 0x400>;
970 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
973 clocks = <&k3_clks 190 0>;
975 assigned-clocks = <&k3_clks 190 0>;
983 reg = <0x00 0x02b10000 0x00 0x2000>,
984 <0x00 0x02b18000 0x00 0x400>;
990 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
993 clocks = <&k3_clks 191 0>;
995 assigned-clocks = <&k3_clks 191 0>;
1003 reg = <0x00 0x02b20000 0x00 0x2000>,
1004 <0x00 0x02b28000 0x00 0x400>;
1010 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
1013 clocks = <&k3_clks 192 0>;
1015 assigned-clocks = <&k3_clks 192 0>;
1023 dmas = <&main_bcdma 0 0x4700 0>;
1025 reg = <0x00 0x30102000 0x00 0x1000>;
1034 reg = <0x00 0x30101000 0x00 0x1000>;
1035 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
1036 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
1044 #size-cells = <0>;
1046 csi0_port0: port@0 {
1047 reg = <0>;
1076 reg = <0x00 0x30110000 0x00 0x1100>;
1077 #phy-cells = <0>;
1085 clocks = <&k3_clks 80 0>;
1087 reg = <0x00 0x03b000000 0x00 0x400>,
1088 <0x00 0x050000000 0x00 0x8000000>;
1104 reg = <0x00 0x25010000 0x00 0x2000>;
1107 clocks = <&k3_clks 54 0>;