Lines Matching +full:timer +full:- +full:secure
1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2022 Tesla, Inc.
11 #include <dt-bindings/clock/fsd-clk.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
38 #address-cells = <2>;
39 #size-cells = <0>;
41 cpu-map {
91 compatible = "arm,cortex-a72";
93 enable-method = "psci";
94 clock-frequency = <2400000000>;
95 cpu-idle-states = <&CPU_SLEEP>;
96 i-cache-size = <0xc000>;
97 i-cache-line-size = <64>;
98 i-cache-sets = <256>;
99 d-cache-size = <0x8000>;
100 d-cache-line-size = <64>;
101 d-cache-sets = <256>;
102 next-level-cache = <&cpucl_l2>;
107 compatible = "arm,cortex-a72";
109 enable-method = "psci";
110 clock-frequency = <2400000000>;
111 cpu-idle-states = <&CPU_SLEEP>;
112 i-cache-size = <0xc000>;
113 i-cache-line-size = <64>;
114 i-cache-sets = <256>;
115 d-cache-size = <0x8000>;
116 d-cache-line-size = <64>;
117 d-cache-sets = <256>;
118 next-level-cache = <&cpucl_l2>;
123 compatible = "arm,cortex-a72";
125 enable-method = "psci";
126 clock-frequency = <2400000000>;
127 cpu-idle-states = <&CPU_SLEEP>;
128 i-cache-size = <0xc000>;
129 i-cache-line-size = <64>;
130 i-cache-sets = <256>;
131 d-cache-size = <0x8000>;
132 d-cache-line-size = <64>;
133 d-cache-sets = <256>;
134 next-level-cache = <&cpucl_l2>;
139 compatible = "arm,cortex-a72";
141 enable-method = "psci";
142 cpu-idle-states = <&CPU_SLEEP>;
143 i-cache-size = <0xc000>;
144 i-cache-line-size = <64>;
145 i-cache-sets = <256>;
146 d-cache-size = <0x8000>;
147 d-cache-line-size = <64>;
148 d-cache-sets = <256>;
149 next-level-cache = <&cpucl_l2>;
155 compatible = "arm,cortex-a72";
157 enable-method = "psci";
158 clock-frequency = <2400000000>;
159 cpu-idle-states = <&CPU_SLEEP>;
160 i-cache-size = <0xc000>;
161 i-cache-line-size = <64>;
162 i-cache-sets = <256>;
163 d-cache-size = <0x8000>;
164 d-cache-line-size = <64>;
165 d-cache-sets = <256>;
166 next-level-cache = <&cpucl_l2>;
171 compatible = "arm,cortex-a72";
173 enable-method = "psci";
174 clock-frequency = <2400000000>;
175 cpu-idle-states = <&CPU_SLEEP>;
176 i-cache-size = <0xc000>;
177 i-cache-line-size = <64>;
178 i-cache-sets = <256>;
179 d-cache-size = <0x8000>;
180 d-cache-line-size = <64>;
181 d-cache-sets = <256>;
182 next-level-cache = <&cpucl_l2>;
187 compatible = "arm,cortex-a72";
189 enable-method = "psci";
190 clock-frequency = <2400000000>;
191 cpu-idle-states = <&CPU_SLEEP>;
192 i-cache-size = <0xc000>;
193 i-cache-line-size = <64>;
194 i-cache-sets = <256>;
195 d-cache-size = <0x8000>;
196 d-cache-line-size = <64>;
197 d-cache-sets = <256>;
198 next-level-cache = <&cpucl_l2>;
203 compatible = "arm,cortex-a72";
205 enable-method = "psci";
206 clock-frequency = <2400000000>;
207 cpu-idle-states = <&CPU_SLEEP>;
208 i-cache-size = <0xc000>;
209 i-cache-line-size = <64>;
210 i-cache-sets = <256>;
211 d-cache-size = <0x8000>;
212 d-cache-line-size = <64>;
213 d-cache-sets = <256>;
214 next-level-cache = <&cpucl_l2>;
220 compatible = "arm,cortex-a72";
222 enable-method = "psci";
223 clock-frequency = <2400000000>;
224 cpu-idle-states = <&CPU_SLEEP>;
225 i-cache-size = <0xc000>;
226 i-cache-line-size = <64>;
227 i-cache-sets = <256>;
228 d-cache-size = <0x8000>;
229 d-cache-line-size = <64>;
230 d-cache-sets = <256>;
231 next-level-cache = <&cpucl_l2>;
236 compatible = "arm,cortex-a72";
238 enable-method = "psci";
239 clock-frequency = <2400000000>;
240 cpu-idle-states = <&CPU_SLEEP>;
241 i-cache-size = <0xc000>;
242 i-cache-line-size = <64>;
243 i-cache-sets = <256>;
244 d-cache-size = <0x8000>;
245 d-cache-line-size = <64>;
246 d-cache-sets = <256>;
247 next-level-cache = <&cpucl_l2>;
252 compatible = "arm,cortex-a72";
254 enable-method = "psci";
255 clock-frequency = <2400000000>;
256 cpu-idle-states = <&CPU_SLEEP>;
257 i-cache-size = <0xc000>;
258 i-cache-line-size = <64>;
259 i-cache-sets = <256>;
260 d-cache-size = <0x8000>;
261 d-cache-line-size = <64>;
262 d-cache-sets = <256>;
263 next-level-cache = <&cpucl_l2>;
268 compatible = "arm,cortex-a72";
270 enable-method = "psci";
271 clock-frequency = <2400000000>;
272 cpu-idle-states = <&CPU_SLEEP>;
273 i-cache-size = <0xc000>;
274 i-cache-line-size = <64>;
275 i-cache-sets = <256>;
276 d-cache-size = <0x8000>;
277 d-cache-line-size = <64>;
278 d-cache-sets = <256>;
279 next-level-cache = <&cpucl_l2>;
282 cpucl_l2: l2-cache0 {
284 cache-level = <2>;
285 cache-unified;
286 cache-size = <0x400000>;
287 cache-line-size = <64>;
288 cache-sets = <4096>;
291 idle-states {
292 entry-method = "psci";
294 CPU_SLEEP: cpu-sleep {
295 idle-state-name = "c2";
296 compatible = "arm,idle-state";
297 local-timer-stop;
298 arm,psci-suspend-param = <0x0010000>;
299 entry-latency-us = <30>;
300 exit-latency-us = <75>;
301 min-residency-us = <300>;
306 arm-pmu {
307 compatible = "arm,cortex-a72-pmu";
320 interrupt-affinity = <&cpucl0_0>, <&cpucl0_1>, <&cpucl0_2>,
327 compatible = "arm,psci-1.0";
331 timer {
332 compatible = "arm,armv8-timer";
340 compatible = "fixed-clock";
341 clock-output-names = "fin_pll";
342 #clock-cells = <0>;
345 reserved-memory {
346 #address-cells = <2>;
347 #size-cells = <2>;
351 compatible = "shared-dma-pool";
352 no-map;
358 compatible = "simple-bus";
359 #address-cells = <2>;
360 #size-cells = <2>;
362 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
364 gic: interrupt-controller@10400000 {
365 compatible = "arm,gic-v3";
366 #interrupt-cells = <3>;
367 interrupt-controller;
374 compatible = "arm,mmu-500";
376 #iommu-cells = <2>;
377 #global-interrupts = <7>;
378 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
379 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
380 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
381 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
386 /* Per context non-secure context interrupts, 0-3 interrupts */
394 compatible = "arm,mmu-500";
396 #iommu-cells = <2>;
397 #global-interrupts = <11>;
398 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
399 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
400 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
401 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
410 /* Per context non-secure context interrupts, 0-7 interrupts */
422 compatible = "arm,mmu-500";
424 #iommu-cells = <2>;
425 #global-interrupts = <5>;
426 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
427 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
428 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
429 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
432 /* Per context non-secure context interrupts, 0-1 interrupts */
438 compatible = "arm,mmu-500";
440 #iommu-cells = <2>;
441 #global-interrupts = <5>;
442 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
443 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
444 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
445 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
448 /* Per context non-secure context interrupts, 0-1 interrupts */
453 clock_imem: clock-controller@10010000 {
454 compatible = "tesla,fsd-clock-imem";
456 #clock-cells = <1>;
461 clock-names = "fin_pll",
467 clock_cmu: clock-controller@11c10000 {
468 compatible = "tesla,fsd-clock-cmu";
470 #clock-cells = <1>;
472 clock-names = "fin_pll";
475 clock_csi: clock-controller@12610000 {
476 compatible = "tesla,fsd-clock-cam_csi";
478 #clock-cells = <1>;
480 clock-names = "fin_pll";
483 sysreg_cam: system-controller@12630000 {
484 compatible = "tesla,fsd-cam-sysreg", "syscon";
488 clock_mfc: clock-controller@12810000 {
489 compatible = "tesla,fsd-clock-mfc";
491 #clock-cells = <1>;
493 clock-names = "fin_pll";
496 clock_peric: clock-controller@14010000 {
497 compatible = "tesla,fsd-clock-peric";
499 #clock-cells = <1>;
506 clock-names = "fin_pll",
514 sysreg_peric: system-controller@14030000 {
515 compatible = "tesla,fsd-peric-sysreg", "syscon";
519 clock_fsys0: clock-controller@15010000 {
520 compatible = "tesla,fsd-clock-fsys0";
522 #clock-cells = <1>;
527 clock-names = "fin_pll",
533 sysreg_fsys0: system-controller@15030000 {
534 compatible = "tesla,fsd-fsys0-sysreg", "syscon";
538 clock_fsys1: clock-controller@16810000 {
539 compatible = "tesla,fsd-clock-fsys1";
541 #clock-cells = <1>;
545 clock-names = "fin_pll",
550 sysreg_fsys1: system-controller@16830000 {
551 compatible = "tesla,fsd-fsys1-sysreg", "syscon";
555 mdma0: dma-controller@10100000 {
559 #dma-cells = <1>;
561 clock-names = "apb_pclk";
565 mdma1: dma-controller@10110000 {
569 #dma-cells = <1>;
571 clock-names = "apb_pclk";
575 pdma0: dma-controller@14280000 {
579 #dma-cells = <1>;
581 clock-names = "apb_pclk";
585 pdma1: dma-controller@14290000 {
589 #dma-cells = <1>;
591 clock-names = "apb_pclk";
596 compatible = "tesla,fsd-uart", "samsung,exynos4210-uart";
600 dma-names = "rx", "tx";
603 clock-names = "uart", "clk_uart_baud0";
604 samsung,uart-fifosize = <64>;
609 compatible = "tesla,fsd-uart", "samsung,exynos4210-uart";
613 dma-names = "rx", "tx";
616 clock-names = "uart", "clk_uart_baud0";
617 samsung,uart-fifosize = <64>;
621 pmu_system_controller: system-controller@11400000 {
622 compatible = "tesla,fsd-pmu", "samsung,exynos7-pmu", "syscon";
627 compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt";
630 samsung,syscon-phandle = <&pmu_system_controller>;
632 clock-names = "watchdog";
636 compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt";
639 samsung,syscon-phandle = <&pmu_system_controller>;
641 clock-names = "watchdog";
645 compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt";
648 samsung,syscon-phandle = <&pmu_system_controller>;
650 clock-names = "watchdog";
654 compatible = "tesla,fsd-pwm", "samsung,exynos4210-pwm";
656 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
657 #pwm-cells = <3>;
659 clock-names = "timers";
664 compatible = "tesla,fsd-pwm", "samsung,exynos4210-pwm";
666 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
667 #pwm-cells = <3>;
669 clock-names = "timers";
674 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
677 #address-cells = <1>;
678 #size-cells = <0>;
679 pinctrl-names = "default";
680 pinctrl-0 = <&hs_i2c0_bus>;
682 clock-names = "hsi2c";
687 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
690 #address-cells = <1>;
691 #size-cells = <0>;
692 pinctrl-names = "default";
693 pinctrl-0 = <&hs_i2c1_bus>;
695 clock-names = "hsi2c";
700 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
703 #address-cells = <1>;
704 #size-cells = <0>;
705 pinctrl-names = "default";
706 pinctrl-0 = <&hs_i2c2_bus>;
708 clock-names = "hsi2c";
713 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
716 #address-cells = <1>;
717 #size-cells = <0>;
718 pinctrl-names = "default";
719 pinctrl-0 = <&hs_i2c3_bus>;
721 clock-names = "hsi2c";
726 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
729 #address-cells = <1>;
730 #size-cells = <0>;
731 pinctrl-names = "default";
732 pinctrl-0 = <&hs_i2c4_bus>;
734 clock-names = "hsi2c";
739 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
742 #address-cells = <1>;
743 #size-cells = <0>;
744 pinctrl-names = "default";
745 pinctrl-0 = <&hs_i2c5_bus>;
747 clock-names = "hsi2c";
752 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
755 #address-cells = <1>;
756 #size-cells = <0>;
757 pinctrl-names = "default";
758 pinctrl-0 = <&hs_i2c6_bus>;
760 clock-names = "hsi2c";
765 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
768 #address-cells = <1>;
769 #size-cells = <0>;
770 pinctrl-names = "default";
771 pinctrl-0 = <&hs_i2c7_bus>;
773 clock-names = "hsi2c";
778 compatible = "tesla,fsd-i2s";
782 dma-names = "tx", "rx", "tx-sec";
783 #clock-cells = <1>;
787 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
788 pinctrl-names = "default";
789 pinctrl-0 = <&i2s0_bus>;
790 #sound-dai-cells = <1>;
795 compatible = "tesla,fsd-i2s";
799 dma-names = "tx", "rx", "tx-sec";
800 #clock-cells = <1>;
804 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
805 pinctrl-names = "default";
806 pinctrl-0 = <&i2s1_bus>;
807 #sound-dai-cells = <1>;
812 compatible = "tesla,fsd-pinctrl";
817 compatible = "tesla,fsd-pinctrl";
823 compatible = "tesla,fsd-pinctrl";
832 reg-names = "m_can", "message_ram";
835 interrupt-names = "int0", "int1";
836 pinctrl-names = "default";
837 pinctrl-0 = <&m_can0_bus>;
840 clock-names = "hclk", "cclk";
841 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
849 reg-names = "m_can", "message_ram";
852 interrupt-names = "int0", "int1";
853 pinctrl-names = "default";
854 pinctrl-0 = <&m_can1_bus>;
857 clock-names = "hclk", "cclk";
858 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
866 reg-names = "m_can", "message_ram";
869 interrupt-names = "int0", "int1";
870 pinctrl-names = "default";
871 pinctrl-0 = <&m_can2_bus>;
874 clock-names = "hclk", "cclk";
875 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
883 reg-names = "m_can", "message_ram";
886 interrupt-names = "int0", "int1";
887 pinctrl-names = "default";
888 pinctrl-0 = <&m_can3_bus>;
891 clock-names = "hclk", "cclk";
892 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
897 compatible = "tesla,fsd-spi";
901 dma-names = "tx", "rx";
902 #address-cells = <1>;
903 #size-cells = <0>;
906 clock-names = "spi", "spi_busclk0";
907 samsung,spi-src-clk = <0>;
908 pinctrl-names = "default";
909 pinctrl-0 = <&spi0_bus>;
910 num-cs = <1>;
915 compatible = "tesla,fsd-spi";
919 dma-names = "tx", "rx";
920 #address-cells = <1>;
921 #size-cells = <0>;
924 clock-names = "spi", "spi_busclk0";
925 samsung,spi-src-clk = <0>;
926 pinctrl-names = "default";
927 pinctrl-0 = <&spi1_bus>;
928 num-cs = <1>;
933 compatible = "tesla,fsd-spi";
937 dma-names = "tx", "rx";
938 #address-cells = <1>;
939 #size-cells = <0>;
942 clock-names = "spi", "spi_busclk0";
943 samsung,spi-src-clk = <0>;
944 pinctrl-names = "default";
945 pinctrl-0 = <&spi2_bus>;
946 num-cs = <1>;
950 timer@10040000 {
951 compatible = "tesla,fsd-mct", "samsung,exynos4210-mct";
970 clock-names = "fin_pll", "mct";
974 compatible = "tesla,fsd-mfc";
977 clock-names = "mfc";
979 memory-region = <&mfc_left>;
983 compatible = "tesla,fsd-ufs";
988 reg-names = "hci", "vs_hci", "unipro", "ufsp";
992 clock-names = "core_clk", "sclk_unipro_main";
993 freq-table-hz = <0 0>, <0 0>;
994 pinctrl-names = "default";
995 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
997 phy-names = "ufs-phy";
1001 ufs_phy: ufs-phy@15124000 {
1002 compatible = "tesla,fsd-ufs-phy";
1004 reg-names = "phy-pma";
1005 samsung,pmu-syscon = <&pmu_system_controller>;
1006 #phy-cells = <0>;
1008 clock-names = "ref_clk";
1013 #include "fsd-pinctrl.dtsi"