Lines Matching +full:stm32mp25 +full:- +full:dma3
1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
6 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
9 #include <dt-bindings/regulator/st,stm32mp25-regulator.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a35";
23 enable-method = "psci";
24 power-domains = <&CPU_PD0>;
25 power-domain-names = "psci";
29 arm-pmu {
30 compatible = "arm,cortex-a35-pmu";
32 interrupt-affinity = <&cpu0>;
33 interrupt-parent = <&intc>;
37 compatible = "arm,smc-wdt";
38 arm,smc-id = <0xb200005a>;
44 #clock-cells = <0>;
45 compatible = "fixed-clock";
46 clock-frequency = <0>;
49 clk_rcbsec: clk-rcbsec {
50 #clock-cells = <0>;
51 compatible = "fixed-clock";
52 clock-frequency = <64000000>;
58 compatible = "linaro,optee-tz";
60 interrupt-parent = <&intc>;
65 compatible = "linaro,scmi-optee";
66 #address-cells = <1>;
67 #size-cells = <0>;
68 linaro,optee-channel-id = <0>;
72 #clock-cells = <1>;
77 #reset-cells = <1>;
84 #address-cells = <1>;
85 #size-cells = <0>;
89 regulator-name = "vddio1";
93 regulator-name = "vddio2";
97 regulator-name = "vddio3";
101 regulator-name = "vddio4";
105 regulator-name = "vdd33ucpd";
109 regulator-name = "vdda18adc";
116 intc: interrupt-controller@4ac00000 {
117 compatible = "arm,cortex-a7-gic";
118 #interrupt-cells = <3>;
119 #address-cells = <1>;
120 interrupt-controller;
128 compatible = "arm,psci-1.0";
131 CPU_PD0: power-domain-cpu0 {
132 #power-domain-cells = <0>;
133 power-domains = <&CLUSTER_PD>;
136 CLUSTER_PD: power-domain-cluster {
137 #power-domain-cells = <0>;
138 power-domains = <&RET_PD>;
141 RET_PD: power-domain-retention {
142 #power-domain-cells = <0>;
147 compatible = "arm,armv8-timer";
148 interrupt-parent = <&intc>;
153 always-on;
157 compatible = "simple-bus";
158 #address-cells = <1>;
159 #size-cells = <1>;
160 interrupt-parent = <&intc>;
163 hpdma: dma-controller@40400000 {
164 compatible = "st,stm32mp25-dma3";
183 #dma-cells = <3>;
186 hpdma2: dma-controller@40410000 {
187 compatible = "st,stm32mp25-dma3";
206 #dma-cells = <3>;
209 hpdma3: dma-controller@40420000 {
210 compatible = "st,stm32mp25-dma3";
229 #dma-cells = <3>;
233 compatible = "st,stm32mp25-rifsc", "simple-bus";
235 #address-cells = <1>;
236 #size-cells = <1>;
237 #access-controller-cells = <1>;
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "st,stm32mp25-spi";
248 access-controllers = <&rifsc 23>;
253 #address-cells = <1>;
254 #size-cells = <0>;
255 compatible = "st,stm32mp25-spi";
260 access-controllers = <&rifsc 24>;
265 compatible = "st,stm32h7-uart";
269 access-controllers = <&rifsc 32>;
274 compatible = "st,stm32h7-uart";
278 access-controllers = <&rifsc 33>;
283 compatible = "st,stm32h7-uart";
287 access-controllers = <&rifsc 34>;
292 compatible = "st,stm32h7-uart";
296 access-controllers = <&rifsc 35>;
301 compatible = "st,stm32mp25-i2c";
303 interrupt-names = "event";
307 #address-cells = <1>;
308 #size-cells = <0>;
309 access-controllers = <&rifsc 41>;
314 compatible = "st,stm32mp25-i2c";
316 interrupt-names = "event";
320 #address-cells = <1>;
321 #size-cells = <0>;
322 access-controllers = <&rifsc 42>;
327 compatible = "st,stm32mp25-i2c";
329 interrupt-names = "event";
333 #address-cells = <1>;
334 #size-cells = <0>;
335 access-controllers = <&rifsc 43>;
340 compatible = "st,stm32mp25-i2c";
342 interrupt-names = "event";
346 #address-cells = <1>;
347 #size-cells = <0>;
348 access-controllers = <&rifsc 44>;
353 compatible = "st,stm32mp25-i2c";
355 interrupt-names = "event";
359 #address-cells = <1>;
360 #size-cells = <0>;
361 access-controllers = <&rifsc 45>;
366 compatible = "st,stm32mp25-i2c";
368 interrupt-names = "event";
372 #address-cells = <1>;
373 #size-cells = <0>;
374 access-controllers = <&rifsc 46>;
379 compatible = "st,stm32mp25-i2c";
381 interrupt-names = "event";
385 #address-cells = <1>;
386 #size-cells = <0>;
387 access-controllers = <&rifsc 47>;
392 compatible = "st,stm32h7-uart";
396 access-controllers = <&rifsc 36>;
401 #address-cells = <1>;
402 #size-cells = <0>;
403 compatible = "st,stm32mp25-spi";
408 access-controllers = <&rifsc 22>;
413 #address-cells = <1>;
414 #size-cells = <0>;
415 compatible = "st,stm32mp25-spi";
420 access-controllers = <&rifsc 25>;
425 #address-cells = <1>;
426 #size-cells = <0>;
427 compatible = "st,stm32mp25-spi";
432 access-controllers = <&rifsc 26>;
437 compatible = "st,stm32h7-uart";
441 access-controllers = <&rifsc 39>;
446 compatible = "st,stm32h7-uart";
450 access-controllers = <&rifsc 31>;
455 #address-cells = <1>;
456 #size-cells = <0>;
457 compatible = "st,stm32mp25-spi";
462 access-controllers = <&rifsc 27>;
467 #address-cells = <1>;
468 #size-cells = <0>;
469 compatible = "st,stm32mp25-spi";
474 access-controllers = <&rifsc 28>;
479 compatible = "st,stm32h7-uart";
483 access-controllers = <&rifsc 37>;
488 compatible = "st,stm32h7-uart";
492 access-controllers = <&rifsc 38>;
497 #address-cells = <1>;
498 #size-cells = <0>;
499 compatible = "st,stm32mp25-spi";
504 access-controllers = <&rifsc 29>;
509 compatible = "st,stm32mp25-i2c";
511 interrupt-names = "event";
515 #address-cells = <1>;
516 #size-cells = <0>;
517 access-controllers = <&rifsc 48>;
522 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
523 arm,primecell-periphid = <0x00353180>;
527 clock-names = "apb_pclk";
529 cap-sd-highspeed;
530 cap-mmc-highspeed;
531 max-frequency = <120000000>;
532 access-controllers = <&rifsc 76>;
537 compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20";
539 reg-names = "stmmaceth";
540 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
541 interrupt-names = "macirq";
542 clock-names = "stmmaceth",
543 "mac-clk-tx",
544 "mac-clk-rx",
547 "eth-ck";
554 snps,axi-config = <&stmmac_axi_config_1>;
555 snps,mixed-burst;
556 snps,mtl-rx-config = <&mtl_rx_setup_1>;
557 snps,mtl-tx-config = <&mtl_tx_setup_1>;
561 access-controllers = <&rifsc 60>;
564 mtl_rx_setup_1: rx-queues-config {
565 snps,rx-queues-to-use = <2>;
570 mtl_tx_setup_1: tx-queues-config {
571 snps,tx-queues-to-use = <4>;
578 stmmac_axi_config_1: stmmac-axi-config {
587 compatible = "st,stm32mp25-bsec";
589 #address-cells = <1>;
590 #size-cells = <1>;
602 rcc: clock-controller@44200000 {
603 compatible = "st,stm32mp25-rcc";
605 #clock-cells = <1>;
606 #reset-cells = <1>;
687 access-controllers = <&rifsc 156>;
690 exti1: interrupt-controller@44220000 {
691 compatible = "st,stm32mp1-exti", "syscon";
692 interrupt-controller;
693 #interrupt-cells = <2>;
695 interrupts-extended =
784 compatible = "st,stm32mp25-syscfg", "syscon";
789 #address-cells = <1>;
790 #size-cells = <1>;
791 compatible = "st,stm32mp257-pinctrl";
793 interrupt-parent = <&exti1>;
795 pins-are-numbered;
798 gpio-controller;
799 #gpio-cells = <2>;
800 interrupt-controller;
801 #interrupt-cells = <2>;
804 st,bank-name = "GPIOA";
809 gpio-controller;
810 #gpio-cells = <2>;
811 interrupt-controller;
812 #interrupt-cells = <2>;
815 st,bank-name = "GPIOB";
820 gpio-controller;
821 #gpio-cells = <2>;
822 interrupt-controller;
823 #interrupt-cells = <2>;
826 st,bank-name = "GPIOC";
831 gpio-controller;
832 #gpio-cells = <2>;
833 interrupt-controller;
834 #interrupt-cells = <2>;
837 st,bank-name = "GPIOD";
842 gpio-controller;
843 #gpio-cells = <2>;
844 interrupt-controller;
845 #interrupt-cells = <2>;
848 st,bank-name = "GPIOE";
853 gpio-controller;
854 #gpio-cells = <2>;
855 interrupt-controller;
856 #interrupt-cells = <2>;
859 st,bank-name = "GPIOF";
864 gpio-controller;
865 #gpio-cells = <2>;
866 interrupt-controller;
867 #interrupt-cells = <2>;
870 st,bank-name = "GPIOG";
875 gpio-controller;
876 #gpio-cells = <2>;
877 interrupt-controller;
878 #interrupt-cells = <2>;
881 st,bank-name = "GPIOH";
886 gpio-controller;
887 #gpio-cells = <2>;
888 interrupt-controller;
889 #interrupt-cells = <2>;
892 st,bank-name = "GPIOI";
897 gpio-controller;
898 #gpio-cells = <2>;
899 interrupt-controller;
900 #interrupt-cells = <2>;
903 st,bank-name = "GPIOJ";
908 gpio-controller;
909 #gpio-cells = <2>;
910 interrupt-controller;
911 #interrupt-cells = <2>;
914 st,bank-name = "GPIOK";
920 #address-cells = <1>;
921 #size-cells = <1>;
922 compatible = "st,stm32mp257-z-pinctrl";
924 interrupt-parent = <&exti1>;
926 pins-are-numbered;
929 gpio-controller;
930 #gpio-cells = <2>;
931 interrupt-controller;
932 #interrupt-cells = <2>;
935 st,bank-name = "GPIOZ";
936 st,bank-ioport = <11>;
942 exti2: interrupt-controller@46230000 {
943 compatible = "st,stm32mp1-exti", "syscon";
944 interrupt-controller;
945 #interrupt-cells = <2>;
947 interrupts-extended =