Lines Matching +full:0 +full:x40380000
17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0>;
38 arm,smc-id = <0xb200005a>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
50 #clock-cells = <0>;
67 #size-cells = <0>;
68 linaro,optee-channel-id = <0>;
71 reg = <0x14>;
76 reg = <0x16>;
81 reg = <0x17>;
85 #size-cells = <0>;
87 scmi_vddio1: regulator@0 {
121 reg = <0x0 0x4ac10000 0x0 0x1000>,
122 <0x0 0x4ac20000 0x0 0x2000>,
123 <0x0 0x4ac40000 0x0 0x2000>,
124 <0x0 0x4ac60000 0x0 0x2000>;
132 #power-domain-cells = <0>;
137 #power-domain-cells = <0>;
142 #power-domain-cells = <0>;
156 soc@0 {
161 ranges = <0x0 0x0 0x0 0x80000000>;
165 reg = <0x40400000 0x1000>;
188 reg = <0x40410000 0x1000>;
211 reg = <0x40420000 0x1000>;
234 reg = <0x42080000 0x1000>;
242 #size-cells = <0>;
244 reg = <0x400b0000 0x400>;
254 #size-cells = <0>;
256 reg = <0x400c0000 0x400>;
266 reg = <0x400e0000 0x400>;
275 reg = <0x400f0000 0x400>;
284 reg = <0x40100000 0x400>;
293 reg = <0x40110000 0x400>;
302 reg = <0x40120000 0x400>;
308 #size-cells = <0>;
315 reg = <0x40130000 0x400>;
321 #size-cells = <0>;
328 reg = <0x40140000 0x400>;
334 #size-cells = <0>;
341 reg = <0x40150000 0x400>;
347 #size-cells = <0>;
354 reg = <0x40160000 0x400>;
360 #size-cells = <0>;
367 reg = <0x40170000 0x400>;
373 #size-cells = <0>;
380 reg = <0x40180000 0x400>;
386 #size-cells = <0>;
393 reg = <0x40220000 0x400>;
402 #size-cells = <0>;
404 reg = <0x40230000 0x400>;
414 #size-cells = <0>;
416 reg = <0x40240000 0x400>;
426 #size-cells = <0>;
428 reg = <0x40280000 0x400>;
438 reg = <0x402c0000 0x400>;
447 reg = <0x40330000 0x400>;
456 #size-cells = <0>;
458 reg = <0x40350000 0x400>;
468 #size-cells = <0>;
470 reg = <0x40360000 0x400>;
480 reg = <0x40370000 0x400>;
489 reg = <0x40380000 0x400>;
498 #size-cells = <0>;
500 reg = <0x46020000 0x400>;
510 reg = <0x46040000 0x400>;
516 #size-cells = <0>;
523 arm,primecell-periphid = <0x00353180>;
524 reg = <0x48220000 0x400>, <0x44230400 0x8>;
538 reg = <0x482c0000 0x4000>;
560 st,syscon = <&syscfg 0x3000>;
579 snps,blen = <0 0 0 0 16 8 4>;
580 snps,rd_osr_lmt = <0x7>;
581 snps,wr_osr_lmt = <0x7>;
588 reg = <0x44000000 0x1000>;
593 reg = <0x24 0x4>;
597 reg = <0x1e8 0x1>;
598 bits = <0 3>;
604 reg = <0x44200000 0x10000>;
694 reg = <0x44220000 0x400>;
712 <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
716 <0>, /* EXTI_20 */
731 <0>,
747 <0>,
748 <0>,
749 <0>,
750 <0>,
751 <0>,
752 <0>,
753 <0>,
754 <0>,
756 <0>, /* EXTI_60 */
758 <0>,
759 <0>,
761 <0>,
762 <0>,
765 <0>,
767 <0>,
776 <0>, /* EXTI_80 */
777 <0>,
778 <0>,
785 reg = <0x44230000 0x10000>;
792 ranges = <0 0x44240000 0xa0400>;
794 st,syscfg = <&exti1 0x60 0xff>;
802 reg = <0x0 0x400>;
813 reg = <0x10000 0x400>;
824 reg = <0x20000 0x400>;
835 reg = <0x30000 0x400>;
846 reg = <0x40000 0x400>;
857 reg = <0x50000 0x400>;
868 reg = <0x60000 0x400>;
879 reg = <0x70000 0x400>;
890 reg = <0x80000 0x400>;
901 reg = <0x90000 0x400>;
912 reg = <0xa0000 0x400>;
923 ranges = <0 0x46200000 0x400>;
925 st,syscfg = <&exti1 0x60 0xff>;
933 reg = <0 0x400>;
946 reg = <0x46230000 0x400>;
966 <0>,
967 <0>,
968 <0>, /* EXTI_20 */
971 <0>,
972 <0>,
976 <0>,
980 <0>,
983 <0>,
984 <0>,
986 <0>,
987 <0>,
989 <0>,
990 <0>,
992 <0>,
993 <0>,
995 <0>,
1002 <0>,
1003 <0>,
1004 <0>,
1005 <0>,
1006 <0>,
1007 <0>,
1008 <0>, /* EXTI_60 */
1011 <0>,
1016 <0>,
1017 <0>,