Lines Matching +full:0 +full:x2e
23 reg = <0 0x20210000 0 0x10000>;
28 reg = <0 0x402b0000 0 0x10000>;
33 reg = <0 0x402e0000 0 0x10000>;
38 reg = <0 0x40400000 0 0x10000>;
43 reg = <0 0x415e0000 0 0x1000000>;
48 reg = <0 0x61100000 0 0x10000>;
53 reg = <0 0x62100000 0 0x10000>;
58 reg = <0 0x63100000 0 0x10000>;
63 reg = <0 0x70b00000 0 0x40000>;
70 ranges = <0 0x0 0x70000000 0x10000000>;
72 uart0: serial@0 {
75 reg = <0x0 0x100>;
87 reg = <0x100000 0x100>;
99 reg = <0x200000 0x100>;
111 reg = <0x300000 0x100>;
129 reg = <0 0x20100000 0 0x4000>;
141 reg = <0 0x50430000 0 0x1000>;
151 sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>;
152 sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>;
153 sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>;
154 sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>;
176 reg = <0 0x40030000 0 0x10000>;
177 hwlocks = <&hwlock 0>;
180 #size-cells = <0>;
185 reg = <0 0x40050000 0 0x20>;
192 reg = <0 0x40050020 0 0x20>;
198 reg = <0 0x40500000 0 0x1000>;
206 reg = <0 0x40210000 0 0x80>;
216 reg = <0 0x40210080 0 0x20>;
226 reg = <0 0x402100a0 0 0x20>;
236 reg = <0 0x402100c0 0 0x20>;
246 reg = <0 0x40280000 0 0x1000>;
256 reg = <0 0x402a0000 0 0x10000>;
261 reg = <0 0x40310000 0 0x1000>;
278 reg = <0 0x41580000 0 0x4000>;
292 #clock-cells = <0>;
299 #clock-cells = <0>;
306 #clock-cells = <0>;
313 #clock-cells = <0>;