Lines Matching +full:sc9836 +full:- +full:uart
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/sprd,ums512-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <2>;
18 #size-cells = <0>;
20 cpu-map {
51 compatible = "arm,cortex-a55";
53 enable-method = "psci";
54 cpu-idle-states = <&CORE_PD>;
59 compatible = "arm,cortex-a55";
61 enable-method = "psci";
62 cpu-idle-states = <&CORE_PD>;
67 compatible = "arm,cortex-a55";
69 enable-method = "psci";
70 cpu-idle-states = <&CORE_PD>;
75 compatible = "arm,cortex-a55";
77 enable-method = "psci";
78 cpu-idle-states = <&CORE_PD>;
83 compatible = "arm,cortex-a55";
85 enable-method = "psci";
86 cpu-idle-states = <&CORE_PD>;
91 compatible = "arm,cortex-a55";
93 enable-method = "psci";
94 cpu-idle-states = <&CORE_PD>;
99 compatible = "arm,cortex-a75";
101 enable-method = "psci";
102 cpu-idle-states = <&CORE_PD>;
107 compatible = "arm,cortex-a75";
109 enable-method = "psci";
110 cpu-idle-states = <&CORE_PD>;
114 idle-states {
115 entry-method = "psci";
116 CORE_PD: cpu-pd {
117 compatible = "arm,idle-state";
118 entry-latency-us = <4000>;
119 exit-latency-us = <4000>;
120 min-residency-us = <10000>;
121 local-timer-stop;
122 arm,psci-suspend-param = <0x00010000>;
127 compatible = "arm,psci-0.2";
132 compatible = "arm,armv8-timer";
134 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
139 pmu-a55 {
140 compatible = "arm,cortex-a55-pmu";
147 interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>;
150 pmu-a75 {
151 compatible = "arm,cortex-a75-pmu";
154 interrupt-affinity = <&CPU6>, <&CPU7>;
158 compatible = "simple-bus";
159 #address-cells = <2>;
160 #size-cells = <2>;
163 gic: interrupt-controller@12000000 {
164 compatible = "arm,gic-v3";
167 #interrupt-cells = <3>;
168 #address-cells = <2>;
169 #size-cells = <2>;
171 redistributor-stride = <0x0 0x20000>; /* 128KB stride */
172 #redistributor-regions = <1>;
173 interrupt-controller;
178 compatible = "sprd,ums512-glbregs", "syscon",
179 "simple-mfd";
181 #address-cells = <1>;
182 #size-cells = <1>;
185 apahb_gate: clock-controller@0 {
186 compatible = "sprd,ums512-apahb-gate";
189 clock-names = "ext-26m";
190 #clock-cells = <1>;
195 compatible = "sprd,ums512-glbregs", "syscon",
196 "simple-mfd";
201 compatible = "sprd,ums512-glbregs", "syscon",
202 "simple-mfd";
207 compatible = "sprd,ums512-glbregs", "syscon",
208 "simple-mfd";
213 compatible = "sprd,ums512-glbregs", "syscon",
214 "simple-mfd";
219 compatible = "sprd,ums512-glbregs", "syscon",
220 "simple-mfd";
225 compatible = "sprd,ums512-glbregs", "syscon",
226 "simple-mfd";
231 compatible = "sprd,ums512-glbregs", "syscon",
232 "simple-mfd";
237 compatible = "sprd,ums512-glbregs", "syscon",
238 "simple-mfd";
243 compatible = "sprd,ums512-glbregs", "syscon",
244 "simple-mfd";
246 #address-cells = <1>;
247 #size-cells = <1>;
250 dpll0: clock-controller@0 {
251 compatible = "sprd,ums512-g0-pll";
253 #clock-cells = <1>;
258 compatible = "sprd,ums512-glbregs", "syscon",
259 "simple-mfd";
261 #address-cells = <1>;
262 #size-cells = <1>;
265 mpll1: clock-controller@0 {
266 compatible = "sprd,ums512-g2-pll";
268 #clock-cells = <1>;
273 compatible = "sprd,ums512-glbregs", "syscon",
274 "simple-mfd";
276 #address-cells = <1>;
277 #size-cells = <1>;
280 pll1: clock-controller@0 {
281 compatible = "sprd,ums512-g3-pll";
284 clock-names = "ext-26m";
285 #clock-cells = <1>;
290 compatible = "sprd,ums512-glbregs", "syscon",
291 "simple-mfd";
293 #address-cells = <1>;
294 #size-cells = <1>;
297 pll2: clock-controller@0 {
298 compatible = "sprd,ums512-gc-pll";
301 clock-names = "ext-26m";
302 #clock-cells = <1>;
307 compatible = "sprd,ums512-glbregs", "syscon",
308 "simple-mfd";
313 compatible = "sprd,ums512-glbregs", "syscon",
314 "simple-mfd";
316 #address-cells = <1>;
317 #size-cells = <1>;
320 aonapb_gate: clock-controller@0 {
321 compatible = "sprd,ums512-aon-gate";
324 clock-names = "ext-26m";
325 #clock-cells = <1>;
330 compatible = "sprd,ums512-glbregs", "syscon",
331 "simple-mfd";
333 #address-cells = <1>;
334 #size-cells = <1>;
337 pmu_gate: clock-controller@0 {
338 compatible = "sprd,ums512-pmu-gate";
341 clock-names = "ext-26m";
342 #clock-cells = <1>;
347 compatible = "sprd,ums512-glbregs", "syscon",
348 "simple-mfd";
350 #address-cells = <1>;
351 #size-cells = <1>;
354 audcpapb_gate: clock-controller@0 {
355 compatible = "sprd,ums512-audcpapb-gate";
357 #clock-cells = <1>;
362 compatible = "sprd,ums512-glbregs", "syscon",
363 "simple-mfd";
365 #address-cells = <1>;
366 #size-cells = <1>;
369 audcpahb_gate: clock-controller@0 {
370 compatible = "sprd,ums512-audcpahb-gate";
372 #clock-cells = <1>;
377 compatible = "sprd,ums512-glbregs", "syscon",
378 "simple-mfd";
380 #address-cells = <1>;
381 #size-cells = <1>;
384 gpu_clk: clock-controller@0 {
385 compatible = "sprd,ums512-gpu-clk";
387 clock-names = "ext-26m";
389 #clock-cells = <1>;
394 compatible = "sprd,ums512-glbregs", "syscon",
395 "simple-mfd";
400 compatible = "sprd,ums512-glbregs", "syscon",
401 "simple-mfd";
403 #address-cells = <1>;
404 #size-cells = <1>;
407 mm_gate: clock-controller@0 {
408 compatible = "sprd,ums512-mm-gate-clk";
410 #clock-cells = <1>;
415 compatible = "sprd,ums512-glbregs", "syscon",
416 "simple-mfd";
418 #address-cells = <1>;
419 #size-cells = <1>;
422 apapb_gate: clock-controller@0 {
423 compatible = "sprd,ums512-apapb-gate";
425 #clock-cells = <1>;
429 ap_clk: clock-controller@20200000 {
430 compatible = "sprd,ums512-ap-clk";
433 clock-names = "ext-26m";
434 #clock-cells = <1>;
437 aon_clk: clock-controller@32080000 {
438 compatible = "sprd,ums512-aonapb-clk";
442 clock-names = "ext-26m", "ext-32k",
443 "ext-4m", "rco-100m";
444 #clock-cells = <1>;
447 mm_clk: clock-controller@62100000 {
448 compatible = "sprd,ums512-mm-clk";
451 clock-names = "ext-26m";
452 #clock-cells = <1>;
457 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
460 clock-names = "apb_pclk";
462 out-ports {
465 remote-endpoint = <&etb_in>;
470 in-ports {
471 #address-cells = <1>;
472 #size-cells = <0>;
477 remote-endpoint =
486 compatible = "arm,coresight-tmc", "arm,primecell";
489 clock-names = "apb_pclk";
491 in-ports {
494 remote-endpoint =
501 /* AP-CPU Funnel for core3/4/5/7 */
503 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
506 clock-names = "apb_pclk";
508 out-ports {
511 remote-endpoint =
517 in-ports {
518 #address-cells = <1>;
519 #size-cells = <0>;
524 remote-endpoint = <&etm3_out>;
531 remote-endpoint = <&etm4_out>;
538 remote-endpoint = <&etm5_out>;
545 remote-endpoint = <&etm7_out>;
551 /* AP-CPU ETF for little cores */
553 compatible = "arm,coresight-tmc", "arm,primecell";
556 clock-names = "apb_pclk";
558 out-ports {
561 remote-endpoint =
567 in-ports {
570 remote-endpoint =
577 /* AP-CPU ETF for big cores */
579 compatible = "arm,coresight-tmc", "arm,primecell";
582 clock-names = "apb_pclk";
584 out-ports {
587 remote-endpoint =
593 in-ports {
596 remote-endpoint =
605 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
608 clock-names = "apb_pclk";
610 out-ports {
613 remote-endpoint =
619 in-ports {
620 #address-cells = <1>;
621 #size-cells = <0>;
626 remote-endpoint = <&corinth_etf_lit_out>;
633 remote-endpoint = <&corinth_etf_big_out>;
639 /* AP-CPU Funnel for core0/1/2/6 */
641 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
644 clock-names = "apb_pclk";
646 out-ports {
649 remote-endpoint = <&corinth_etf_big_in>;
654 in-ports {
655 #address-cells = <1>;
656 #size-cells = <0>;
661 remote-endpoint = <&etm0_out>;
668 remote-endpoint = <&etm1_out>;
675 remote-endpoint = <&etm2_out>;
682 remote-endpoint = <&etm6_out>;
689 compatible = "arm,coresight-etm4x", "arm,primecell";
693 clock-names = "apb_pclk";
695 out-ports {
698 remote-endpoint =
706 compatible = "arm,coresight-etm4x", "arm,primecell";
710 clock-names = "apb_pclk";
712 out-ports {
715 remote-endpoint =
723 compatible = "arm,coresight-etm4x", "arm,primecell";
727 clock-names = "apb_pclk";
729 out-ports {
732 remote-endpoint =
740 compatible = "arm,coresight-etm4x", "arm,primecell";
744 clock-names = "apb_pclk";
746 out-ports {
749 remote-endpoint =
757 compatible = "arm,coresight-etm4x", "arm,primecell";
761 clock-names = "apb_pclk";
763 out-ports {
766 remote-endpoint =
774 compatible = "arm,coresight-etm4x", "arm,primecell";
778 clock-names = "apb_pclk";
780 out-ports {
783 remote-endpoint =
791 compatible = "arm,coresight-etm4x", "arm,primecell";
795 clock-names = "apb_pclk";
797 out-ports {
800 remote-endpoint =
808 compatible = "arm,coresight-etm4x", "arm,primecell";
812 clock-names = "apb_pclk";
814 out-ports {
817 remote-endpoint =
825 compatible = "simple-bus";
826 #address-cells = <1>;
827 #size-cells = <1>;
831 compatible = "sprd,ums512-uart",
832 "sprd,sc9836-uart";
840 compatible = "sprd,ums512-uart",
841 "sprd,sc9836-uart";
849 compatible = "sprd,sdhci-r11";
854 clock-names = "sdio", "enable";
855 assigned-clocks = <&ap_clk CLK_SDIO0_2X>;
856 assigned-clock-parents = <&pll1 CLK_RPLL>;
861 compatible = "sprd,sdhci-r11";
866 clock-names = "sdio", "enable";
867 assigned-clocks = <&ap_clk CLK_EMMC_2X>;
868 assigned-clock-parents = <&pll1 CLK_RPLL>;
874 compatible = "simple-bus";
875 #address-cells = <1>;
876 #size-cells = <1>;
880 compatible = "sprd,ums512-adi";
882 #address-cells = <1>;
883 #size-cells = <0>;
884 sprd,hw-channels = <2 0x18cc>, <3 0x18cc>, <13 0x1854>, <15 0x1874>,
891 ext_26m: clk-26m {
892 compatible = "fixed-clock";
893 #clock-cells = <0>;
894 clock-frequency = <26000000>;
895 clock-output-names = "ext-26m";
898 ext_32k: clk-32k {
899 compatible = "fixed-clock";
900 #clock-cells = <0>;
901 clock-frequency = <32768>;
902 clock-output-names = "ext-32k";
905 ext_4m: clk-4m {
906 compatible = "fixed-clock";
907 #clock-cells = <0>;
908 clock-frequency = <4000000>;
909 clock-output-names = "ext-4m";
912 rco_100m: clk-100m {
913 compatible = "fixed-clock";
914 #clock-cells = <0>;
915 clock-frequency = <100000000>;
916 clock-output-names = "rco-100m";