Lines Matching +full:0 +full:x54006800
21 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0 0x000>;
57 reg = <0 0x001>;
68 reg = <0 0x100>;
79 reg = <0 0x101>;
100 cluster0_opp: opp-table-0 {
184 #clock-cells = <0>;
239 reg = <0x0 0x81000000 0x0 0x01000000>;
244 soc@0 {
248 ranges = <0 0 0 0xffffffff>;
253 reg = <0x54006000 0x100>;
255 #size-cells = <0>;
258 pinctrl-0 = <&pinctrl_spi0>;
266 reg = <0x54006100 0x100>;
268 #size-cells = <0>;
271 pinctrl-0 = <&pinctrl_spi1>;
279 reg = <0x54006200 0x100>;
281 #size-cells = <0>;
284 pinctrl-0 = <&pinctrl_spi2>;
292 reg = <0x54006300 0x100>;
294 #size-cells = <0>;
297 pinctrl-0 = <&pinctrl_spi3>;
305 reg = <0x54006800 0x40>;
308 pinctrl-0 = <&pinctrl_uart0>;
309 clocks = <&peri_clk 0>;
310 resets = <&peri_rst 0>;
316 reg = <0x54006900 0x40>;
319 pinctrl-0 = <&pinctrl_uart1>;
327 reg = <0x54006a00 0x40>;
330 pinctrl-0 = <&pinctrl_uart2>;
338 reg = <0x54006b00 0x40>;
341 pinctrl-0 = <&pinctrl_uart3>;
348 reg = <0x55000000 0x200>;
354 gpio-ranges = <&pinctrl 0 0 0>,
355 <&pinctrl 96 0 0>,
356 <&pinctrl 160 0 0>;
361 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
367 reg = <0x56000000 0x80000>;
370 pinctrl-0 = <&pinctrl_aout1>,
379 i2s_port0: port@0 {
431 reg = <0x57900000 0x1000>;
435 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
438 port@0 {
454 reg = <0x57920000 0x1000>;
465 reg = <0x58780000 0x80>;
467 #size-cells = <0>;
470 pinctrl-0 = <&pinctrl_i2c0>;
479 reg = <0x58781000 0x80>;
481 #size-cells = <0>;
484 pinctrl-0 = <&pinctrl_i2c1>;
492 reg = <0x58782000 0x80>;
494 #size-cells = <0>;
504 reg = <0x58783000 0x80>;
506 #size-cells = <0>;
509 pinctrl-0 = <&pinctrl_i2c3>;
518 reg = <0x58784000 0x80>;
520 #size-cells = <0>;
523 pinctrl-0 = <&pinctrl_i2c4>;
531 reg = <0x58785000 0x80>;
533 #size-cells = <0>;
543 reg = <0x58c00000 0x400>;
547 pinctrl-0 = <&pinctrl_system_bus>;
552 reg = <0x59801000 0x400>;
558 reg = <0x59810000 0x400>;
574 reg = <0x59820000 0x200>;
589 reg = <0x5a000000 0x400>;
592 pinctrl-0 = <&pinctrl_emmc>;
609 reg = <0x5a400000 0x800>;
612 pinctrl-0 = <&pinctrl_sd>;
613 clocks = <&sd_clk 0>;
615 resets = <&sd_rst 0>;
618 socionext,syscon-uhs-mode = <&sdctrl 0>;
624 reg = <0x5f800000 0x2000>;
634 reg = <0x5f900000 0x2000>;
637 ranges = <0 0x5f900000 0x2000>;
641 reg = <0x100 0x28>;
646 reg = <0x200 0x68>;
652 reg = <0x54 1>;
656 reg = <0x55 1>;
660 reg = <0x58 1>;
664 reg = <0x59 1>;
667 usb_sel_t0: trim@54,0 {
668 reg = <0x54 1>;
669 bits = <0 4>;
671 usb_sel_t1: trim@55,0 {
672 reg = <0x55 1>;
673 bits = <0 4>;
675 usb_sel_t2: trim@58,0 {
676 reg = <0x58 1>;
677 bits = <0 4>;
679 usb_sel_t3: trim@59,0 {
680 reg = <0x59 1>;
681 bits = <0 4>;
683 usb_hs_i0: trim@56,0 {
684 reg = <0x56 1>;
685 bits = <0 4>;
687 usb_hs_i2: trim@5a,0 {
688 reg = <0x5a 1>;
689 bits = <0 4>;
696 reg = <0x5fc10000 0x5300>;
704 reg = <0x5fc20000 0x200>;
711 reg = <0x5fe00000 0x10000>, /* GICD */
712 <0x5fe80000 0x80000>; /* GICR */
721 reg = <0x61840000 0x10000>;
740 #thermal-sensor-cells = <0>;
741 socionext,tmod-calibration = <0x0f22 0x68ee>;
748 reg = <0x65000000 0x8500>;
751 pinctrl-0 = <&pinctrl_ether_rgmii>;
758 socionext,syscon-phy-mode = <&soc_glue 0>;
762 #size-cells = <0>;
769 reg = <0x65a00000 0xcd00>;
773 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
787 reg = <0x65b00000 0x400>;
790 ranges = <0 0x65b00000 0x400>;
792 usb_rst: reset-controller@0 {
794 reg = <0x0 0x4>;
804 reg = <0x100 0x10>;
813 reg = <0x110 0x10>;
822 reg = <0x120 0x10>;
831 reg = <0x130 0x10>;
840 reg = <0x200 0x10>;
841 #phy-cells = <0>;
854 reg = <0x210 0x10>;
855 #phy-cells = <0>;
868 reg = <0x220 0x10>;
869 #phy-cells = <0>;
882 reg = <0x230 0x10>;
883 #phy-cells = <0>;
896 reg = <0x300 0x10>;
897 #phy-cells = <0>;
907 reg = <0x310 0x10>;
908 #phy-cells = <0>;
921 reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
922 <0x2fff0000 0x10000>;
929 bus-range = <0x0 0xff>;
933 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
935 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
940 interrupt-map-mask = <0 0 0 7>;
941 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
942 <0 0 0 2 &pcie_intc 1>, /* INTB */
943 <0 0 0 3 &pcie_intc 2>, /* INTC */
944 <0 0 0 4 &pcie_intc 3>; /* INTD */
958 reg = <0x66038000 0x4000>;
959 #phy-cells = <0>;
971 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
973 #size-cells = <0>;
976 pinctrl-0 = <&pinctrl_nand>;