Lines Matching +full:uniphier +full:- +full:system +full:- +full:cache
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD11 SoC
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 compatible = "socionext,uniphier-ld11";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu-map {
35 compatible = "arm,cortex-a53";
38 enable-method = "psci";
39 next-level-cache = <&l2>;
40 operating-points-v2 = <&cluster0_opp>;
45 compatible = "arm,cortex-a53";
48 enable-method = "psci";
49 next-level-cache = <&l2>;
50 operating-points-v2 = <&cluster0_opp>;
53 l2: l2-cache {
54 compatible = "cache";
55 cache-level = <2>;
56 cache-unified;
60 cluster0_opp: opp-table {
61 compatible = "operating-points-v2";
62 opp-shared;
64 opp-245000000 {
65 opp-hz = /bits/ 64 <245000000>;
66 clock-latency-ns = <300>;
68 opp-250000000 {
69 opp-hz = /bits/ 64 <250000000>;
70 clock-latency-ns = <300>;
72 opp-490000000 {
73 opp-hz = /bits/ 64 <490000000>;
74 clock-latency-ns = <300>;
76 opp-500000000 {
77 opp-hz = /bits/ 64 <500000000>;
78 clock-latency-ns = <300>;
80 opp-653334000 {
81 opp-hz = /bits/ 64 <653334000>;
82 clock-latency-ns = <300>;
84 opp-666667000 {
85 opp-hz = /bits/ 64 <666667000>;
86 clock-latency-ns = <300>;
88 opp-980000000 {
89 opp-hz = /bits/ 64 <980000000>;
90 clock-latency-ns = <300>;
95 compatible = "arm,psci-1.0";
101 compatible = "fixed-clock";
102 #clock-cells = <0>;
103 clock-frequency = <25000000>;
107 emmc_pwrseq: emmc-pwrseq {
108 compatible = "mmc-pwrseq-emmc";
109 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
113 compatible = "arm,armv8-timer";
120 reserved-memory {
121 #address-cells = <2>;
122 #size-cells = <2>;
125 secure-memory@81000000 {
127 no-map;
132 compatible = "simple-bus";
133 #address-cells = <1>;
134 #size-cells = <1>;
138 compatible = "socionext,uniphier-scssi";
141 #address-cells = <1>;
142 #size-cells = <0>;
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_spi0>;
151 compatible = "socionext,uniphier-scssi";
154 #address-cells = <1>;
155 #size-cells = <0>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_spi1>;
164 compatible = "socionext,uniphier-uart";
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_uart0>;
175 compatible = "socionext,uniphier-uart";
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_uart1>;
186 compatible = "socionext,uniphier-uart";
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_uart2>;
197 compatible = "socionext,uniphier-uart";
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_uart3>;
208 compatible = "socionext,uniphier-gpio";
210 interrupt-parent = <&aidet>;
211 interrupt-controller;
212 #interrupt-cells = <2>;
213 gpio-controller;
214 #gpio-cells = <2>;
215 gpio-ranges = <&pinctrl 0 0 0>,
221 gpio-ranges-group-names = "gpio_range0",
228 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
233 compatible = "socionext,uniphier-ld11-aio";
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_aout1>,
239 clock-names = "aio";
241 reset-names = "aio";
243 #sound-dai-cells = <1>;
258 dai-format = "i2s";
259 remote-endpoint = <&evea_line>;
270 dai-format = "i2s";
271 remote-endpoint = <&evea_hp>;
297 compatible = "socionext,uniphier-evea";
299 clock-names = "evea", "exiv";
301 reset-names = "evea", "exiv", "adamv";
303 #sound-dai-cells = <1>;
307 remote-endpoint = <&i2s_line>;
313 remote-endpoint = <&i2s_hp>;
319 compatible = "socionext,uniphier-ld11-adamv",
320 "simple-mfd", "syscon";
323 adamv_rst: reset-controller {
324 compatible = "socionext,uniphier-ld11-adamv-reset";
325 #reset-cells = <1>;
330 compatible = "socionext,uniphier-fi2c";
333 #address-cells = <1>;
334 #size-cells = <0>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_i2c0>;
340 clock-frequency = <100000>;
344 compatible = "socionext,uniphier-fi2c";
347 #address-cells = <1>;
348 #size-cells = <0>;
350 pinctrl-names = "default";
351 pinctrl-0 = <&pinctrl_i2c1>;
354 clock-frequency = <100000>;
358 compatible = "socionext,uniphier-fi2c";
360 #address-cells = <1>;
361 #size-cells = <0>;
365 clock-frequency = <400000>;
369 compatible = "socionext,uniphier-fi2c";
372 #address-cells = <1>;
373 #size-cells = <0>;
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_i2c3>;
379 clock-frequency = <100000>;
383 compatible = "socionext,uniphier-fi2c";
386 #address-cells = <1>;
387 #size-cells = <0>;
389 pinctrl-names = "default";
390 pinctrl-0 = <&pinctrl_i2c4>;
393 clock-frequency = <100000>;
397 compatible = "socionext,uniphier-fi2c";
399 #address-cells = <1>;
400 #size-cells = <0>;
404 clock-frequency = <400000>;
407 system_bus: system-bus@58c00000 {
408 compatible = "socionext,uniphier-system-bus";
411 #address-cells = <2>;
412 #size-cells = <1>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_system_bus>;
418 compatible = "socionext,uniphier-smpctrl";
423 compatible = "socionext,uniphier-ld11-sdctrl",
424 "simple-mfd", "syscon";
427 sd_rst: reset-controller {
428 compatible = "socionext,uniphier-ld11-sd-reset";
429 #reset-cells = <1>;
434 compatible = "socionext,uniphier-ld11-perictrl",
435 "simple-mfd", "syscon";
438 peri_clk: clock-controller {
439 compatible = "socionext,uniphier-ld11-peri-clock";
440 #clock-cells = <1>;
443 peri_rst: reset-controller {
444 compatible = "socionext,uniphier-ld11-peri-reset";
445 #reset-cells = <1>;
450 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
453 pinctrl-names = "default";
454 pinctrl-0 = <&pinctrl_emmc>;
457 bus-width = <8>;
458 mmc-ddr-1_8v;
459 mmc-hs200-1_8v;
460 mmc-pwrseq = <&emmc_pwrseq>;
461 cdns,phy-input-delay-legacy = <9>;
462 cdns,phy-input-delay-mmc-highspeed = <2>;
463 cdns,phy-input-delay-mmc-ddr = <3>;
464 cdns,phy-dll-delay-sdclk = <21>;
465 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
469 compatible = "socionext,uniphier-ehci", "generic-ehci";
473 pinctrl-names = "default";
474 pinctrl-0 = <&pinctrl_usb0>;
479 phy-names = "usb";
481 has-transaction-translator;
485 compatible = "socionext,uniphier-ehci", "generic-ehci";
489 pinctrl-names = "default";
490 pinctrl-0 = <&pinctrl_usb1>;
495 phy-names = "usb";
497 has-transaction-translator;
501 compatible = "socionext,uniphier-ehci", "generic-ehci";
505 pinctrl-names = "default";
506 pinctrl-0 = <&pinctrl_usb2>;
511 phy-names = "usb";
513 has-transaction-translator;
517 compatible = "socionext,uniphier-ld11-mioctrl",
518 "simple-mfd", "syscon";
521 mio_clk: clock-controller {
522 compatible = "socionext,uniphier-ld11-mio-clock";
523 #clock-cells = <1>;
526 mio_rst: reset-controller {
527 compatible = "socionext,uniphier-ld11-mio-reset";
528 #reset-cells = <1>;
534 compatible = "socionext,uniphier-ld11-soc-glue",
535 "simple-mfd", "syscon";
539 compatible = "socionext,uniphier-ld11-pinctrl";
542 usb-hub {
543 compatible = "socionext,uniphier-ld11-usb2-phy";
544 #address-cells = <1>;
545 #size-cells = <0>;
549 #phy-cells = <0>;
554 #phy-cells = <0>;
559 #phy-cells = <0>;
565 compatible = "socionext,uniphier-ld11-soc-glue-debug",
566 "simple-mfd", "syscon";
568 #address-cells = <1>;
569 #size-cells = <1>;
573 compatible = "socionext,uniphier-efuse";
578 compatible = "socionext,uniphier-efuse";
583 xdmac: dma-controller@5fc10000 {
584 compatible = "socionext,uniphier-xdmac";
587 dma-channels = <16>;
588 #dma-cells = <2>;
591 aidet: interrupt-controller@5fc20000 {
592 compatible = "socionext,uniphier-ld11-aidet";
594 interrupt-controller;
595 #interrupt-cells = <2>;
598 gic: interrupt-controller@5fe00000 {
599 compatible = "arm,gic-v3";
602 interrupt-controller;
603 #interrupt-cells = <3>;
608 compatible = "socionext,uniphier-ld11-sysctrl",
609 "simple-mfd", "syscon";
612 sys_clk: clock-controller {
613 compatible = "socionext,uniphier-ld11-clock";
614 #clock-cells = <1>;
617 sys_rst: reset-controller {
618 compatible = "socionext,uniphier-ld11-reset";
619 #reset-cells = <1>;
623 compatible = "socionext,uniphier-wdt";
628 compatible = "socionext,uniphier-ld11-ave4";
632 clock-names = "ether";
634 reset-names = "ether";
636 phy-mode = "internal";
637 local-mac-address = [00 00 00 00 00 00];
638 socionext,syscon-phy-mode = <&soc_glue 0>;
641 #address-cells = <1>;
642 #size-cells = <0>;
646 nand: nand-controller@68000000 {
647 compatible = "socionext,uniphier-denali-nand-v5b";
649 reg-names = "nand_data", "denali_reg";
651 #address-cells = <1>;
652 #size-cells = <0>;
654 pinctrl-names = "default";
655 pinctrl-0 = <&pinctrl_nand>;
656 clock-names = "nand", "nand_x", "ecc";
658 reset-names = "nand", "reg";
664 #include "uniphier-pinctrl.dtsi"
667 drive-strength = <4>; /* default: 4mA */
671 drive-strength = <8>; /* 8mA */