Lines Matching +full:pcie +full:- +full:phy +full:- +full:3
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "rk3588-base.dtsi"
7 #include "rk3588-extra-pinctrl.dtsi"
11 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
16 clock-names = "ref_clk", "suspend_clk", "bus_clk";
19 phy-names = "usb2-phy", "usb3-phy";
21 power-domains = <&power RK3588_PD_USB>;
24 snps,dis-u2-freeclk-exists-quirk;
25 snps,dis-del-phy-power-chg-quirk;
26 snps,dis-tx-ipgap-linecheck-quirk;
31 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
36 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
41 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
46 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
48 #address-cells = <1>;
49 #size-cells = <1>;
52 compatible = "rockchip,rk3588-usb2phy";
54 #clock-cells = <0>;
56 clock-names = "phyclk";
57 clock-output-names = "usb480m_phy1";
60 reset-names = "phy", "apb";
63 u2phy1_otg: otg-port {
64 #phy-cells = <0>;
71 compatible = "rockchip,rk3588-i2s-tdm";
75 clock-names = "mclk_tx", "mclk_rx", "hclk";
76 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
77 assigned-clock-parents = <&cru PLL_AUPLL>;
79 dma-names = "tx";
80 power-domains = <&power RK3588_PD_VO0>;
82 reset-names = "tx-m";
83 #sound-dai-cells = <0>;
88 compatible = "rockchip,rk3588-i2s-tdm";
92 clock-names = "mclk_tx", "mclk_rx", "hclk";
93 assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
94 assigned-clock-parents = <&cru PLL_AUPLL>;
96 dma-names = "tx";
97 power-domains = <&power RK3588_PD_VO1>;
99 reset-names = "tx-m";
100 #sound-dai-cells = <0>;
105 compatible = "rockchip,rk3588-i2s-tdm";
109 clock-names = "mclk_tx", "mclk_rx", "hclk";
110 assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
111 assigned-clock-parents = <&cru PLL_AUPLL>;
113 dma-names = "rx";
114 power-domains = <&power RK3588_PD_VO1>;
116 reset-names = "rx-m";
117 #sound-dai-cells = <0>;
122 compatible = "rockchip,rk3588-i2s-tdm";
126 clock-names = "mclk_tx", "mclk_rx", "hclk";
127 assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
128 assigned-clock-parents = <&cru PLL_AUPLL>;
130 dma-names = "rx";
131 power-domains = <&power RK3588_PD_VO1>;
133 reset-names = "rx-m";
134 #sound-dai-cells = <0>;
138 pcie3x4: pcie@fe150000 {
139 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
140 #address-cells = <3>;
141 #size-cells = <2>;
142 bus-range = <0x00 0x0f>;
146 clock-names = "aclk_mst", "aclk_slv",
155 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
156 #interrupt-cells = <1>;
157 interrupt-map-mask = <0 0 0 7>;
158 interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
160 <0 0 0 3 &pcie3x4_intc 2>,
161 <0 0 0 4 &pcie3x4_intc 3>;
162 linux,pci-domain = <0>;
163 max-link-speed = <3>;
164 msi-map = <0x0000 &its1 0x0000 0x1000>;
165 num-lanes = <4>;
167 phy-names = "pcie-phy";
168 power-domains = <&power RK3588_PD_PCIE>;
175 reg-names = "dbi", "apb", "config";
177 reset-names = "pwr", "pipe";
180 pcie3x4_intc: legacy-interrupt-controller {
181 interrupt-controller;
182 #address-cells = <0>;
183 #interrupt-cells = <1>;
184 interrupt-parent = <&gic>;
189 pcie3x4_ep: pcie-ep@fe150000 {
190 compatible = "rockchip,rk3588-pcie-ep";
196 reg-names = "dbi", "dbi2", "apb", "addr_space", "atu";
200 clock-names = "aclk_mst", "aclk_slv",
212 interrupt-names = "sys", "pmc", "msg", "legacy", "err",
214 max-link-speed = <3>;
215 num-lanes = <4>;
217 phy-names = "pcie-phy";
218 power-domains = <&power RK3588_PD_PCIE>;
220 reset-names = "pwr", "pipe";
224 pcie3x2: pcie@fe160000 {
225 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
226 #address-cells = <3>;
227 #size-cells = <2>;
228 bus-range = <0x10 0x1f>;
232 clock-names = "aclk_mst", "aclk_slv",
241 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
242 #interrupt-cells = <1>;
243 interrupt-map-mask = <0 0 0 7>;
244 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
246 <0 0 0 3 &pcie3x2_intc 2>,
247 <0 0 0 4 &pcie3x2_intc 3>;
248 linux,pci-domain = <1>;
249 max-link-speed = <3>;
250 msi-map = <0x1000 &its1 0x1000 0x1000>;
251 num-lanes = <2>;
253 phy-names = "pcie-phy";
254 power-domains = <&power RK3588_PD_PCIE>;
261 reg-names = "dbi", "apb", "config";
263 reset-names = "pwr", "pipe";
266 pcie3x2_intc: legacy-interrupt-controller {
267 interrupt-controller;
268 #address-cells = <0>;
269 #interrupt-cells = <1>;
270 interrupt-parent = <&gic>;
275 pcie2x1l0: pcie@fe170000 {
276 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
277 bus-range = <0x20 0x2f>;
281 clock-names = "aclk_mst", "aclk_slv",
290 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
291 #interrupt-cells = <1>;
292 interrupt-map-mask = <0 0 0 7>;
293 interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
295 <0 0 0 3 &pcie2x1l0_intc 2>,
296 <0 0 0 4 &pcie2x1l0_intc 3>;
297 linux,pci-domain = <2>;
298 max-link-speed = <2>;
299 msi-map = <0x2000 &its0 0x2000 0x1000>;
300 num-lanes = <1>;
302 phy-names = "pcie-phy";
303 power-domains = <&power RK3588_PD_PCIE>;
310 reg-names = "dbi", "apb", "config";
312 reset-names = "pwr", "pipe";
313 #address-cells = <3>;
314 #size-cells = <2>;
317 pcie2x1l0_intc: legacy-interrupt-controller {
318 interrupt-controller;
319 #address-cells = <0>;
320 #interrupt-cells = <1>;
321 interrupt-parent = <&gic>;
327 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
331 interrupt-names = "macirq", "eth_wake_irq";
335 clock-names = "stmmaceth", "clk_mac_ref",
338 power-domains = <&power RK3588_PD_GMAC>;
340 reset-names = "stmmaceth";
342 rockchip,php-grf = <&php_grf>;
343 snps,axi-config = <&gmac0_stmmac_axi_setup>;
344 snps,mixed-burst;
345 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
346 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
351 compatible = "snps,dwmac-mdio";
352 #address-cells = <0x1>;
353 #size-cells = <0x0>;
356 gmac0_stmmac_axi_setup: stmmac-axi-config {
362 gmac0_mtl_rx_setup: rx-queues-config {
363 snps,rx-queues-to-use = <2>;
368 gmac0_mtl_tx_setup: tx-queues-config {
369 snps,tx-queues-to-use = <2>;
376 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
382 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
383 ports-implemented = <0x1>;
384 #address-cells = <1>;
385 #size-cells = <0>;
388 sata-port@0 {
390 hba-port-cap = <HBA_PORT_FBSCP>;
392 phy-names = "sata-phy";
393 snps,rx-ts-max = <32>;
394 snps,tx-ts-max = <32>;
398 usbdp_phy1: phy@fed90000 {
399 compatible = "rockchip,rk3588-usbdp-phy";
401 #phy-cells = <1>;
406 clock-names = "refclk", "immortal", "pclk", "utmi";
412 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
413 rockchip,u2phy-grf = <&usb2phy1_grf>;
414 rockchip,usb-grf = <&usb_grf>;
415 rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
416 rockchip,vo-grf = <&vo0_grf>;
420 combphy1_ps: phy@fee10000 {
421 compatible = "rockchip,rk3588-naneng-combphy";
425 clock-names = "ref", "apb", "pipe";
426 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
427 assigned-clock-rates = <100000000>;
428 #phy-cells = <1>;
430 reset-names = "phy", "apb";
431 rockchip,pipe-grf = <&php_grf>;
432 rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
436 pcie30phy: phy@fee80000 {
437 compatible = "rockchip,rk3588-pcie3-phy";
439 #phy-cells = <0>;
441 clock-names = "pclk";
443 reset-names = "phy";
444 rockchip,pipe-grf = <&php_grf>;
445 rockchip,phy-grf = <&pcie30_phy_grf>;