Lines Matching +full:num +full:- +full:tx +full:- +full:queues
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "rk3588-base.dtsi"
7 #include "rk3588-extra-pinctrl.dtsi"
10 hdmi1_sound: hdmi1-sound {
11 compatible = "simple-audio-card";
12 simple-audio-card,format = "i2s";
13 simple-audio-card,mclk-fs = <128>;
14 simple-audio-card,name = "hdmi1";
17 simple-audio-card,codec {
18 sound-dai = <&hdmi1>;
21 simple-audio-card,cpu {
22 sound-dai = <&i2s6_8ch>;
26 reserved-memory {
27 #address-cells = <2>;
28 #size-cells = <2>;
37 * To ensure sufficient support for practical use-cases,
40 hdmi_receiver_cma: hdmi-receiver-cma {
41 compatible = "shared-dma-pool";
42 alloc-ranges = <0x0 0x0 0x0 0xffffffff>;
45 no-map;
51 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
56 clock-names = "ref_clk", "suspend_clk", "bus_clk";
59 phy-names = "usb2-phy", "usb3-phy";
61 power-domains = <&power RK3588_PD_USB>;
64 snps,dis-u2-freeclk-exists-quirk;
65 snps,dis-del-phy-power-chg-quirk;
66 snps,dis-tx-ipgap-linecheck-quirk;
71 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
76 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
81 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
86 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
88 #address-cells = <1>;
89 #size-cells = <1>;
92 compatible = "rockchip,rk3588-usb2phy";
94 #clock-cells = <0>;
96 clock-names = "phyclk";
97 clock-output-names = "usb480m_phy1";
100 reset-names = "phy", "apb";
103 u2phy1_otg: otg-port {
104 #phy-cells = <0>;
111 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
115 spdif_tx5: spdif-tx@fddb8000 {
116 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
118 assigned-clock-parents = <&cru PLL_AUPLL>;
119 assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>;
120 clock-names = "mclk", "hclk";
122 dma-names = "tx";
125 power-domains = <&power RK3588_PD_VO0>;
126 #sound-dai-cells = <0>;
131 compatible = "rockchip,rk3588-i2s-tdm";
135 clock-names = "mclk_tx", "mclk_rx", "hclk";
136 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
137 assigned-clock-parents = <&cru PLL_AUPLL>;
139 dma-names = "tx";
140 power-domains = <&power RK3588_PD_VO0>;
142 reset-names = "tx-m";
143 #sound-dai-cells = <0>;
147 spdif_tx4: spdif-tx@fdde8000 {
148 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
150 assigned-clock-parents = <&cru PLL_AUPLL>;
151 assigned-clocks = <&cru CLK_SPDIF4_SRC>;
152 clock-names = "mclk", "hclk";
154 dma-names = "tx";
157 power-domains = <&power RK3588_PD_VO1>;
158 #sound-dai-cells = <0>;
163 compatible = "rockchip,rk3588-i2s-tdm";
167 clock-names = "mclk_tx", "mclk_rx", "hclk";
168 assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
169 assigned-clock-parents = <&cru PLL_AUPLL>;
171 dma-names = "tx";
172 power-domains = <&power RK3588_PD_VO1>;
174 reset-names = "tx-m";
175 #sound-dai-cells = <0>;
180 compatible = "rockchip,rk3588-i2s-tdm";
184 clock-names = "mclk_tx", "mclk_rx", "hclk";
185 assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
186 assigned-clock-parents = <&cru PLL_AUPLL>;
188 dma-names = "rx";
189 power-domains = <&power RK3588_PD_VO1>;
191 reset-names = "rx-m";
192 #sound-dai-cells = <0>;
197 compatible = "rockchip,rk3588-i2s-tdm";
201 clock-names = "mclk_tx", "mclk_rx", "hclk";
202 assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
203 assigned-clock-parents = <&cru PLL_AUPLL>;
205 dma-names = "rx";
206 power-domains = <&power RK3588_PD_VO1>;
208 reset-names = "rx-m";
209 #sound-dai-cells = <0>;
214 compatible = "rockchip,rk3588-dw-hdmi-qp";
222 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
228 interrupt-names = "avp", "cec", "earc", "main", "hpd";
230 pinctrl-names = "default";
231 pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd
233 power-domains = <&power RK3588_PD_VO1>;
235 reset-names = "ref", "hdp";
237 rockchip,vo-grf = <&vo1_grf>;
238 #sound-dai-cells = <0>;
242 #address-cells = <1>;
243 #size-cells = <0>;
256 compatible = "rockchip,rk3588-edp";
259 clock-names = "dp", "pclk";
262 phy-names = "dp";
263 power-domains = <&power RK3588_PD_VO1>;
265 reset-names = "dp", "apb";
270 #address-cells = <1>;
271 #size-cells = <0>;
284 compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx";
289 interrupt-names = "cec", "hdmi", "dma";
297 clock-names = "aclk",
304 memory-region = <&hdmi_receiver_cma>;
305 power-domains = <&power RK3588_PD_VO1>;
308 reset-names = "axi", "apb", "ref", "biu";
310 rockchip,vo1-grf = <&vo1_grf>;
315 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
316 #address-cells = <3>;
317 #size-cells = <2>;
318 bus-range = <0x00 0x0f>;
322 clock-names = "aclk_mst", "aclk_slv",
331 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
332 #interrupt-cells = <1>;
333 interrupt-map-mask = <0 0 0 7>;
334 interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
338 linux,pci-domain = <0>;
339 max-link-speed = <3>;
340 msi-map = <0x0000 &its1 0x0000 0x1000>;
341 iommu-map = <0x0000 &mmu600_pcie 0x0000 0x1000>;
342 num-lanes = <4>;
344 phy-names = "pcie-phy";
345 power-domains = <&power RK3588_PD_PCIE>;
352 reg-names = "dbi", "apb", "config";
354 reset-names = "pwr", "pipe";
357 pcie3x4_intc: legacy-interrupt-controller {
358 interrupt-controller;
359 #address-cells = <0>;
360 #interrupt-cells = <1>;
361 interrupt-parent = <&gic>;
366 pcie3x4_ep: pcie-ep@fe150000 {
367 compatible = "rockchip,rk3588-pcie-ep";
373 reg-names = "dbi", "dbi2", "apb", "addr_space", "atu";
377 clock-names = "aclk_mst", "aclk_slv",
389 interrupt-names = "sys", "pmc", "msg", "legacy", "err",
391 max-link-speed = <3>;
392 num-lanes = <4>;
394 phy-names = "pcie-phy";
395 power-domains = <&power RK3588_PD_PCIE>;
397 reset-names = "pwr", "pipe";
402 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
403 #address-cells = <3>;
404 #size-cells = <2>;
405 bus-range = <0x10 0x1f>;
409 clock-names = "aclk_mst", "aclk_slv",
418 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
419 #interrupt-cells = <1>;
420 interrupt-map-mask = <0 0 0 7>;
421 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
425 linux,pci-domain = <1>;
426 max-link-speed = <3>;
427 msi-map = <0x1000 &its1 0x1000 0x1000>;
428 iommu-map = <0x1000 &mmu600_pcie 0x1000 0x1000>;
429 num-lanes = <2>;
431 phy-names = "pcie-phy";
432 power-domains = <&power RK3588_PD_PCIE>;
439 reg-names = "dbi", "apb", "config";
441 reset-names = "pwr", "pipe";
444 pcie3x2_intc: legacy-interrupt-controller {
445 interrupt-controller;
446 #address-cells = <0>;
447 #interrupt-cells = <1>;
448 interrupt-parent = <&gic>;
454 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
455 bus-range = <0x20 0x2f>;
459 clock-names = "aclk_mst", "aclk_slv",
468 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
469 #interrupt-cells = <1>;
470 interrupt-map-mask = <0 0 0 7>;
471 interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
475 linux,pci-domain = <2>;
476 max-link-speed = <2>;
477 msi-map = <0x2000 &its0 0x2000 0x1000>;
478 iommu-map = <0x2000 &mmu600_pcie 0x2000 0x1000>;
479 num-lanes = <1>;
481 phy-names = "pcie-phy";
482 power-domains = <&power RK3588_PD_PCIE>;
489 reg-names = "dbi", "apb", "config";
491 reset-names = "pwr", "pipe";
492 #address-cells = <3>;
493 #size-cells = <2>;
496 pcie2x1l0_intc: legacy-interrupt-controller {
497 interrupt-controller;
498 #address-cells = <0>;
499 #interrupt-cells = <1>;
500 interrupt-parent = <&gic>;
506 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
510 interrupt-names = "macirq", "eth_wake_irq";
514 clock-names = "stmmaceth", "clk_mac_ref",
517 power-domains = <&power RK3588_PD_GMAC>;
519 reset-names = "stmmaceth";
521 rockchip,php-grf = <&php_grf>;
522 snps,axi-config = <&gmac0_stmmac_axi_setup>;
523 snps,mixed-burst;
524 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
525 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
530 compatible = "snps,dwmac-mdio";
531 #address-cells = <0x1>;
532 #size-cells = <0x0>;
535 gmac0_stmmac_axi_setup: stmmac-axi-config {
541 gmac0_mtl_rx_setup: rx-queues-config {
542 snps,rx-queues-to-use = <2>;
547 gmac0_mtl_tx_setup: tx-queues-config {
548 snps,tx-queues-to-use = <2>;
555 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
561 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
562 ports-implemented = <0x1>;
563 #address-cells = <1>;
564 #size-cells = <0>;
567 sata-port@0 {
569 hba-port-cap = <HBA_PORT_FBSCP>;
571 phy-names = "sata-phy";
572 snps,rx-ts-max = <32>;
573 snps,tx-ts-max = <32>;
578 compatible = "rockchip,rk3588-hdptx-phy";
581 clock-names = "ref", "apb";
582 #clock-cells = <0>;
583 #phy-cells = <0>;
588 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
595 compatible = "rockchip,rk3588-usbdp-phy";
597 #phy-cells = <1>;
602 clock-names = "refclk", "immortal", "pclk", "utmi";
608 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
609 rockchip,u2phy-grf = <&usb2phy1_grf>;
610 rockchip,usb-grf = <&usb_grf>;
611 rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
612 rockchip,vo-grf = <&vo0_grf>;
617 compatible = "rockchip,rk3588-naneng-combphy";
621 clock-names = "ref", "apb", "pipe";
622 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
623 assigned-clock-rates = <100000000>;
624 #phy-cells = <1>;
626 reset-names = "phy", "apb";
627 rockchip,pipe-grf = <&php_grf>;
628 rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
633 compatible = "rockchip,rk3588-pcie3-phy";
635 #phy-cells = <0>;
637 clock-names = "pclk";
639 reset-names = "phy";
640 rockchip,pipe-grf = <&php_grf>;
641 rockchip,phy-grf = <&pcie30_phy_grf>;
656 clock-names = "aclk",