Lines Matching full:cru
54 clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
55 <&cru ACLK_USB3OTG1>;
62 resets = <&cru SRST_A_USB3OTG1>;
95 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
99 resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
118 assigned-clock-parents = <&cru PLL_AUPLL>;
119 assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>;
121 clocks = <&cru MCLK_SPDIF5>, <&cru HCLK_SPDIF5_DP1>;
134 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
136 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
137 assigned-clock-parents = <&cru PLL_AUPLL>;
141 resets = <&cru SRST_M_I2S8_8CH_TX>;
150 assigned-clock-parents = <&cru PLL_AUPLL>;
151 assigned-clocks = <&cru CLK_SPDIF4_SRC>;
153 clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>;
166 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
168 assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
169 assigned-clock-parents = <&cru PLL_AUPLL>;
173 resets = <&cru SRST_M_I2S6_8CH_TX>;
183 clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
185 assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
186 assigned-clock-parents = <&cru PLL_AUPLL>;
190 resets = <&cru SRST_M_I2S7_8CH_RX>;
200 clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
202 assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
203 assigned-clock-parents = <&cru PLL_AUPLL>;
207 resets = <&cru SRST_M_I2S10_8CH_RX>;
216 clocks = <&cru PCLK_HDMITX1>,
217 <&cru CLK_HDMITX1_EARC>,
218 <&cru CLK_HDMITX1_REF>,
219 <&cru MCLK_I2S6_8CH_TX>,
220 <&cru CLK_HDMIHDP1>,
221 <&cru HCLK_VO1>;
234 resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>;
258 clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>;
264 resets = <&cru SRST_EDP1_24M>, <&cru SRST_P_EDP1>;
290 clocks = <&cru ACLK_HDMIRX>,
291 <&cru CLK_HDMIRX_AUD>,
292 <&cru CLK_CR_PARA>,
293 <&cru PCLK_HDMIRX>,
294 <&cru CLK_HDMIRX_REF>,
295 <&cru PCLK_S_HDMIRX>,
296 <&cru HCLK_VO1>;
306 resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>,
307 <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>;
319 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
320 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
321 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
353 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
374 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
375 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
376 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
396 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
406 clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
407 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
408 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
440 resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
456 clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
457 <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
458 <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
490 resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
511 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
512 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
513 <&cru CLK_GMAC0_PTP_REF>;
518 resets = <&cru SRST_A_GMAC0>;
558 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
559 <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
560 <&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
580 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
584 resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
585 <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,
586 <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>,
587 <&cru SRST_HDPTX1_LCPLL>;
598 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
599 <&cru CLK_USBDP_PHY1_IMMORTAL>,
600 <&cru PCLK_USBDPPHY1>,
603 resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
604 <&cru SRST_USBDP_COMBO_PHY1_CMN>,
605 <&cru SRST_USBDP_COMBO_PHY1_LANE>,
606 <&cru SRST_USBDP_COMBO_PHY1_PCS>,
607 <&cru SRST_P_USBDPPHY1>;
619 clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
620 <&cru PCLK_PHP_ROOT>;
622 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
625 resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
636 clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
638 resets = <&cru SRST_PCIE30_PHY>;
647 clocks = <&cru ACLK_VOP>,
648 <&cru HCLK_VOP>,
649 <&cru DCLK_VOP0>,
650 <&cru DCLK_VOP1>,
651 <&cru DCLK_VOP2>,
652 <&cru DCLK_VOP3>,
653 <&cru PCLK_VOP_ROOT>,