Lines Matching +full:tsadc +full:- +full:apb
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/power/rk3588-power.h>
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/ata/ahci.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
55 #address-cells = <1>;
56 #size-cells = <0>;
58 cpu-map {
93 compatible = "arm,cortex-a55";
95 enable-method = "psci";
96 capacity-dmips-mhz = <530>;
98 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
99 assigned-clock-rates = <816000000>;
100 cpu-idle-states = <&CPU_SLEEP>;
101 i-cache-size = <32768>;
102 i-cache-line-size = <64>;
103 i-cache-sets = <128>;
104 d-cache-size = <32768>;
105 d-cache-line-size = <64>;
106 d-cache-sets = <128>;
107 next-level-cache = <&l2_cache_l0>;
108 dynamic-power-coefficient = <228>;
109 #cooling-cells = <2>;
114 compatible = "arm,cortex-a55";
116 enable-method = "psci";
117 capacity-dmips-mhz = <530>;
119 cpu-idle-states = <&CPU_SLEEP>;
120 i-cache-size = <32768>;
121 i-cache-line-size = <64>;
122 i-cache-sets = <128>;
123 d-cache-size = <32768>;
124 d-cache-line-size = <64>;
125 d-cache-sets = <128>;
126 next-level-cache = <&l2_cache_l1>;
127 dynamic-power-coefficient = <228>;
128 #cooling-cells = <2>;
133 compatible = "arm,cortex-a55";
135 enable-method = "psci";
136 capacity-dmips-mhz = <530>;
138 cpu-idle-states = <&CPU_SLEEP>;
139 i-cache-size = <32768>;
140 i-cache-line-size = <64>;
141 i-cache-sets = <128>;
142 d-cache-size = <32768>;
143 d-cache-line-size = <64>;
144 d-cache-sets = <128>;
145 next-level-cache = <&l2_cache_l2>;
146 dynamic-power-coefficient = <228>;
147 #cooling-cells = <2>;
152 compatible = "arm,cortex-a55";
154 enable-method = "psci";
155 capacity-dmips-mhz = <530>;
157 cpu-idle-states = <&CPU_SLEEP>;
158 i-cache-size = <32768>;
159 i-cache-line-size = <64>;
160 i-cache-sets = <128>;
161 d-cache-size = <32768>;
162 d-cache-line-size = <64>;
163 d-cache-sets = <128>;
164 next-level-cache = <&l2_cache_l3>;
165 dynamic-power-coefficient = <228>;
166 #cooling-cells = <2>;
171 compatible = "arm,cortex-a76";
173 enable-method = "psci";
174 capacity-dmips-mhz = <1024>;
176 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
177 assigned-clock-rates = <816000000>;
178 cpu-idle-states = <&CPU_SLEEP>;
179 i-cache-size = <65536>;
180 i-cache-line-size = <64>;
181 i-cache-sets = <256>;
182 d-cache-size = <65536>;
183 d-cache-line-size = <64>;
184 d-cache-sets = <256>;
185 next-level-cache = <&l2_cache_b0>;
186 dynamic-power-coefficient = <416>;
187 #cooling-cells = <2>;
192 compatible = "arm,cortex-a76";
194 enable-method = "psci";
195 capacity-dmips-mhz = <1024>;
197 cpu-idle-states = <&CPU_SLEEP>;
198 i-cache-size = <65536>;
199 i-cache-line-size = <64>;
200 i-cache-sets = <256>;
201 d-cache-size = <65536>;
202 d-cache-line-size = <64>;
203 d-cache-sets = <256>;
204 next-level-cache = <&l2_cache_b1>;
205 dynamic-power-coefficient = <416>;
206 #cooling-cells = <2>;
211 compatible = "arm,cortex-a76";
213 enable-method = "psci";
214 capacity-dmips-mhz = <1024>;
216 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
217 assigned-clock-rates = <816000000>;
218 cpu-idle-states = <&CPU_SLEEP>;
219 i-cache-size = <65536>;
220 i-cache-line-size = <64>;
221 i-cache-sets = <256>;
222 d-cache-size = <65536>;
223 d-cache-line-size = <64>;
224 d-cache-sets = <256>;
225 next-level-cache = <&l2_cache_b2>;
226 dynamic-power-coefficient = <416>;
227 #cooling-cells = <2>;
232 compatible = "arm,cortex-a76";
234 enable-method = "psci";
235 capacity-dmips-mhz = <1024>;
237 cpu-idle-states = <&CPU_SLEEP>;
238 i-cache-size = <65536>;
239 i-cache-line-size = <64>;
240 i-cache-sets = <256>;
241 d-cache-size = <65536>;
242 d-cache-line-size = <64>;
243 d-cache-sets = <256>;
244 next-level-cache = <&l2_cache_b3>;
245 dynamic-power-coefficient = <416>;
246 #cooling-cells = <2>;
249 idle-states {
250 entry-method = "psci";
251 CPU_SLEEP: cpu-sleep {
252 compatible = "arm,idle-state";
253 local-timer-stop;
254 arm,psci-suspend-param = <0x0010000>;
255 entry-latency-us = <100>;
256 exit-latency-us = <120>;
257 min-residency-us = <1000>;
261 l2_cache_l0: l2-cache-l0 {
263 cache-size = <131072>;
264 cache-line-size = <64>;
265 cache-sets = <512>;
266 cache-level = <2>;
267 cache-unified;
268 next-level-cache = <&l3_cache>;
271 l2_cache_l1: l2-cache-l1 {
273 cache-size = <131072>;
274 cache-line-size = <64>;
275 cache-sets = <512>;
276 cache-level = <2>;
277 cache-unified;
278 next-level-cache = <&l3_cache>;
281 l2_cache_l2: l2-cache-l2 {
283 cache-size = <131072>;
284 cache-line-size = <64>;
285 cache-sets = <512>;
286 cache-level = <2>;
287 cache-unified;
288 next-level-cache = <&l3_cache>;
291 l2_cache_l3: l2-cache-l3 {
293 cache-size = <131072>;
294 cache-line-size = <64>;
295 cache-sets = <512>;
296 cache-level = <2>;
297 cache-unified;
298 next-level-cache = <&l3_cache>;
301 l2_cache_b0: l2-cache-b0 {
303 cache-size = <524288>;
304 cache-line-size = <64>;
305 cache-sets = <1024>;
306 cache-level = <2>;
307 cache-unified;
308 next-level-cache = <&l3_cache>;
311 l2_cache_b1: l2-cache-b1 {
313 cache-size = <524288>;
314 cache-line-size = <64>;
315 cache-sets = <1024>;
316 cache-level = <2>;
317 cache-unified;
318 next-level-cache = <&l3_cache>;
321 l2_cache_b2: l2-cache-b2 {
323 cache-size = <524288>;
324 cache-line-size = <64>;
325 cache-sets = <1024>;
326 cache-level = <2>;
327 cache-unified;
328 next-level-cache = <&l3_cache>;
331 l2_cache_b3: l2-cache-b3 {
333 cache-size = <524288>;
334 cache-line-size = <64>;
335 cache-sets = <1024>;
336 cache-level = <2>;
337 cache-unified;
338 next-level-cache = <&l3_cache>;
346 l3_cache: l3-cache {
348 cache-size = <3145728>;
349 cache-line-size = <64>;
350 cache-sets = <4096>;
351 cache-level = <3>;
352 cache-unified;
355 display_subsystem: display-subsystem {
356 compatible = "rockchip,display-subsystem";
362 compatible = "linaro,optee-tz";
367 compatible = "arm,scmi-smc";
368 arm,smc-id = <0x82000010>;
370 #address-cells = <1>;
371 #size-cells = <0>;
375 #clock-cells = <1>;
380 #reset-cells = <1>;
385 pmu-a55 {
386 compatible = "arm,cortex-a55-pmu";
390 pmu-a76 {
391 compatible = "arm,cortex-a76-pmu";
396 compatible = "arm,psci-1.0";
400 spll: clock-0 {
401 compatible = "fixed-clock";
402 clock-frequency = <702000000>;
403 clock-output-names = "spll";
404 #clock-cells = <0>;
408 compatible = "arm,armv8-timer";
414 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
417 xin24m: clock-1 {
418 compatible = "fixed-clock";
419 clock-frequency = <24000000>;
420 clock-output-names = "xin24m";
421 #clock-cells = <0>;
424 xin32k: clock-2 {
425 compatible = "fixed-clock";
426 clock-frequency = <32768>;
427 clock-output-names = "xin32k";
428 #clock-cells = <0>;
432 compatible = "mmio-sram";
435 #address-cells = <1>;
436 #size-cells = <1>;
439 compatible = "arm,scmi-shmem";
445 compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
447 #cooling-cells = <2>;
448 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
449 assigned-clock-rates = <200000000>;
452 clock-names = "core", "coregroup", "stacks";
453 dynamic-power-coefficient = <2982>;
457 interrupt-names = "job", "mmu", "gpu";
458 power-domains = <&power RK3588_PD_GPU>;
463 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
468 clock-names = "ref_clk", "suspend_clk", "bus_clk";
471 phy-names = "usb2-phy", "usb3-phy";
473 power-domains = <&power RK3588_PD_USB>;
476 snps,dis-u1-entry-quirk;
477 snps,dis-u2-entry-quirk;
478 snps,dis-u2-freeclk-exists-quirk;
479 snps,dis-del-phy-power-chg-quirk;
480 snps,dis-tx-ipgap-linecheck-quirk;
485 compatible = "rockchip,rk3588-ehci", "generic-ehci";
490 phy-names = "usb";
491 power-domains = <&power RK3588_PD_USB>;
496 compatible = "rockchip,rk3588-ohci", "generic-ohci";
501 phy-names = "usb";
502 power-domains = <&power RK3588_PD_USB>;
507 compatible = "rockchip,rk3588-ehci", "generic-ehci";
512 phy-names = "usb";
513 power-domains = <&power RK3588_PD_USB>;
518 compatible = "rockchip,rk3588-ohci", "generic-ohci";
523 phy-names = "usb";
524 power-domains = <&power RK3588_PD_USB>;
529 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
535 clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
538 phy-names = "usb3-phy";
542 snps,dis-u2-freeclk-exists-quirk;
543 snps,dis-del-phy-power-chg-quirk;
544 snps,dis-tx-ipgap-linecheck-quirk;
550 compatible = "arm,smmu-v3";
556 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
557 #iommu-cells = <1>;
562 compatible = "arm,smmu-v3";
568 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
569 #iommu-cells = <1>;
574 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
579 compatible = "rockchip,rk3588-sys-grf", "syscon";
584 compatible = "rockchip,rk3588-vop-grf", "syscon";
589 compatible = "rockchip,rk3588-vo0-grf", "syscon";
595 compatible = "rockchip,rk3588-vo1-grf", "syscon";
601 compatible = "rockchip,rk3588-usb-grf", "syscon";
606 compatible = "rockchip,rk3588-php-grf", "syscon";
611 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
616 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
621 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
626 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
628 #address-cells = <1>;
629 #size-cells = <1>;
632 compatible = "rockchip,rk3588-usb2phy";
634 #clock-cells = <0>;
636 clock-names = "phyclk";
637 clock-output-names = "usb480m_phy0";
640 reset-names = "phy", "apb";
643 u2phy0_otg: otg-port {
644 #phy-cells = <0>;
651 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
653 #address-cells = <1>;
654 #size-cells = <1>;
657 compatible = "rockchip,rk3588-usb2phy";
659 #clock-cells = <0>;
661 clock-names = "phyclk";
662 clock-output-names = "usb480m_phy2";
665 reset-names = "phy", "apb";
668 u2phy2_host: host-port {
669 #phy-cells = <0>;
676 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
678 #address-cells = <1>;
679 #size-cells = <1>;
682 compatible = "rockchip,rk3588-usb2phy";
684 #clock-cells = <0>;
686 clock-names = "phyclk";
687 clock-output-names = "usb480m_phy3";
690 reset-names = "phy", "apb";
693 u2phy3_host: host-port {
694 #phy-cells = <0>;
701 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
706 compatible = "rockchip,rk3588-ioc", "syscon";
711 compatible = "mmio-sram";
714 #address-cells = <1>;
715 #size-cells = <1>;
718 cru: clock-controller@fd7c0000 {
719 compatible = "rockchip,rk3588-cru";
721 assigned-clocks =
731 assigned-clock-rates =
742 #clock-cells = <1>;
743 #reset-cells = <1>;
747 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
751 clock-names = "i2c", "pclk";
752 pinctrl-0 = <&i2c0m0_xfer>;
753 pinctrl-names = "default";
754 #address-cells = <1>;
755 #size-cells = <0>;
760 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
764 clock-names = "baudclk", "apb_pclk";
766 dma-names = "tx", "rx";
767 pinctrl-0 = <&uart0m1_xfer>;
768 pinctrl-names = "default";
769 reg-shift = <2>;
770 reg-io-width = <4>;
775 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
778 clock-names = "pwm", "pclk";
779 pinctrl-0 = <&pwm0m0_pins>;
780 pinctrl-names = "default";
781 #pwm-cells = <3>;
786 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
789 clock-names = "pwm", "pclk";
790 pinctrl-0 = <&pwm1m0_pins>;
791 pinctrl-names = "default";
792 #pwm-cells = <3>;
797 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
800 clock-names = "pwm", "pclk";
801 pinctrl-0 = <&pwm2m0_pins>;
802 pinctrl-names = "default";
803 #pwm-cells = <3>;
808 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
811 clock-names = "pwm", "pclk";
812 pinctrl-0 = <&pwm3m0_pins>;
813 pinctrl-names = "default";
814 #pwm-cells = <3>;
818 pmu: power-management@fd8d8000 {
819 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
822 power: power-controller {
823 compatible = "rockchip,rk3588-power-controller";
824 #address-cells = <1>;
825 #power-domain-cells = <1>;
826 #size-cells = <0>;
830 power-domain@RK3588_PD_NPU {
832 #power-domain-cells = <0>;
833 #address-cells = <1>;
834 #size-cells = <0>;
836 power-domain@RK3588_PD_NPUTOP {
845 #power-domain-cells = <0>;
846 #address-cells = <1>;
847 #size-cells = <0>;
849 power-domain@RK3588_PD_NPU1 {
855 #power-domain-cells = <0>;
857 power-domain@RK3588_PD_NPU2 {
863 #power-domain-cells = <0>;
868 power-domain@RK3588_PD_GPU {
877 #power-domain-cells = <0>;
880 power-domain@RK3588_PD_VCODEC {
882 #address-cells = <1>;
883 #size-cells = <0>;
884 #power-domain-cells = <0>;
886 power-domain@RK3588_PD_RKVDEC0 {
894 #power-domain-cells = <0>;
896 power-domain@RK3588_PD_RKVDEC1 {
903 #power-domain-cells = <0>;
905 power-domain@RK3588_PD_VENC0 {
912 #address-cells = <1>;
913 #size-cells = <0>;
914 #power-domain-cells = <0>;
916 power-domain@RK3588_PD_VENC1 {
925 #power-domain-cells = <0>;
930 power-domain@RK3588_PD_VDPU {
958 #address-cells = <1>;
959 #size-cells = <0>;
960 #power-domain-cells = <0>;
963 power-domain@RK3588_PD_AV1 {
969 #power-domain-cells = <0>;
971 power-domain@RK3588_PD_RKVDEC0 {
978 #power-domain-cells = <0>;
980 power-domain@RK3588_PD_RKVDEC1 {
986 #power-domain-cells = <0>;
988 power-domain@RK3588_PD_RGA30 {
993 #power-domain-cells = <0>;
996 power-domain@RK3588_PD_VOP {
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1005 #power-domain-cells = <0>;
1007 power-domain@RK3588_PD_VO0 {
1017 #power-domain-cells = <0>;
1020 power-domain@RK3588_PD_VO1 {
1031 #power-domain-cells = <0>;
1033 power-domain@RK3588_PD_VI {
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1047 #power-domain-cells = <0>;
1049 power-domain@RK3588_PD_ISP1 {
1057 #power-domain-cells = <0>;
1059 power-domain@RK3588_PD_FEC {
1068 #power-domain-cells = <0>;
1071 power-domain@RK3588_PD_RGA31 {
1076 #power-domain-cells = <0>;
1078 power-domain@RK3588_PD_USB {
1092 #power-domain-cells = <0>;
1094 power-domain@RK3588_PD_GMAC {
1099 #power-domain-cells = <0>;
1101 power-domain@RK3588_PD_PCIE {
1106 #power-domain-cells = <0>;
1108 power-domain@RK3588_PD_SDIO {
1113 #power-domain-cells = <0>;
1115 power-domain@RK3588_PD_AUDIO {
1119 #power-domain-cells = <0>;
1121 power-domain@RK3588_PD_SDMMC {
1124 #power-domain-cells = <0>;
1129 vpu121: video-codec@fdb50000 {
1130 compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu";
1133 interrupt-names = "vdpu";
1135 clock-names = "aclk", "hclk";
1137 power-domains = <&power RK3588_PD_VDPU>;
1141 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1144 clock-names = "aclk", "iface";
1146 power-domains = <&power RK3588_PD_VDPU>;
1147 #iommu-cells = <0>;
1151 compatible = "rockchip,rk3588-rga", "rockchip,rk3288-rga";
1155 clock-names = "aclk", "hclk", "sclk";
1157 reset-names = "core", "axi", "ahb";
1158 power-domains = <&power RK3588_PD_VDPU>;
1161 vepu121_0: video-codec@fdba0000 {
1162 compatible = "rockchip,rk3588-vepu121";
1166 clock-names = "aclk", "hclk";
1168 power-domains = <&power RK3588_PD_VDPU>;
1172 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1176 clock-names = "aclk", "iface";
1177 power-domains = <&power RK3588_PD_VDPU>;
1178 #iommu-cells = <0>;
1181 vepu121_1: video-codec@fdba4000 {
1182 compatible = "rockchip,rk3588-vepu121";
1186 clock-names = "aclk", "hclk";
1188 power-domains = <&power RK3588_PD_VDPU>;
1192 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1196 clock-names = "aclk", "iface";
1197 power-domains = <&power RK3588_PD_VDPU>;
1198 #iommu-cells = <0>;
1201 vepu121_2: video-codec@fdba8000 {
1202 compatible = "rockchip,rk3588-vepu121";
1206 clock-names = "aclk", "hclk";
1208 power-domains = <&power RK3588_PD_VDPU>;
1212 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1216 clock-names = "aclk", "iface";
1217 power-domains = <&power RK3588_PD_VDPU>;
1218 #iommu-cells = <0>;
1221 vepu121_3: video-codec@fdbac000 {
1222 compatible = "rockchip,rk3588-vepu121";
1226 clock-names = "aclk", "hclk";
1228 power-domains = <&power RK3588_PD_VDPU>;
1232 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1236 clock-names = "aclk", "iface";
1237 power-domains = <&power RK3588_PD_VDPU>;
1238 #iommu-cells = <0>;
1241 av1d: video-codec@fdc70000 {
1242 compatible = "rockchip,rk3588-av1-vpu";
1245 interrupt-names = "vdpu";
1246 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
1247 assigned-clock-rates = <400000000>, <400000000>;
1249 clock-names = "aclk", "hclk";
1250 power-domains = <&power RK3588_PD_AV1>;
1255 compatible = "rockchip,rk3588-vop";
1257 reg-names = "vop", "gamma-lut";
1266 clock-names = "aclk",
1274 power-domains = <&power RK3588_PD_VOP>;
1276 rockchip,vop-grf = <&vop_grf>;
1277 rockchip,vo1-grf = <&vo1_grf>;
1282 #address-cells = <1>;
1283 #size-cells = <0>;
1286 #address-cells = <1>;
1287 #size-cells = <0>;
1292 #address-cells = <1>;
1293 #size-cells = <0>;
1298 #address-cells = <1>;
1299 #size-cells = <0>;
1304 #address-cells = <1>;
1305 #size-cells = <0>;
1312 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1316 clock-names = "aclk", "iface";
1317 #iommu-cells = <0>;
1318 power-domains = <&power RK3588_PD_VOP>;
1323 compatible = "rockchip,rk3588-i2s-tdm";
1327 clock-names = "mclk_tx", "mclk_rx", "hclk";
1328 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
1329 assigned-clock-parents = <&cru PLL_AUPLL>;
1331 dma-names = "tx";
1332 power-domains = <&power RK3588_PD_VO0>;
1334 reset-names = "tx-m";
1335 #sound-dai-cells = <0>;
1340 compatible = "rockchip,rk3588-i2s-tdm";
1344 clock-names = "mclk_tx", "mclk_rx", "hclk";
1345 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
1346 assigned-clock-parents = <&cru PLL_AUPLL>;
1348 dma-names = "tx";
1349 power-domains = <&power RK3588_PD_VO1>;
1351 reset-names = "tx-m";
1352 #sound-dai-cells = <0>;
1357 compatible = "rockchip,rk3588-i2s-tdm";
1361 clock-names = "mclk_tx", "mclk_rx", "hclk";
1362 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
1363 assigned-clock-parents = <&cru PLL_AUPLL>;
1365 dma-names = "rx";
1366 power-domains = <&power RK3588_PD_VO1>;
1368 reset-names = "rx-m";
1369 #sound-dai-cells = <0>;
1374 compatible = "rockchip,rk3588-dw-hdmi-qp";
1382 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
1388 interrupt-names = "avp", "cec", "earc", "main", "hpd";
1390 pinctrl-names = "default";
1391 pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
1393 power-domains = <&power RK3588_PD_VO1>;
1395 reset-names = "ref", "hdp";
1397 rockchip,vo-grf = <&vo1_grf>;
1401 #address-cells = <1>;
1402 #size-cells = <0>;
1415 compatible = "rockchip,rk3588-qos", "syscon";
1420 compatible = "rockchip,rk3588-qos", "syscon";
1425 compatible = "rockchip,rk3588-qos", "syscon";
1430 compatible = "rockchip,rk3588-qos", "syscon";
1435 compatible = "rockchip,rk3588-qos", "syscon";
1440 compatible = "rockchip,rk3588-qos", "syscon";
1445 compatible = "rockchip,rk3588-qos", "syscon";
1450 compatible = "rockchip,rk3588-qos", "syscon";
1455 compatible = "rockchip,rk3588-qos", "syscon";
1460 compatible = "rockchip,rk3588-qos", "syscon";
1465 compatible = "rockchip,rk3588-qos", "syscon";
1470 compatible = "rockchip,rk3588-qos", "syscon";
1475 compatible = "rockchip,rk3588-qos", "syscon";
1480 compatible = "rockchip,rk3588-qos", "syscon";
1485 compatible = "rockchip,rk3588-qos", "syscon";
1490 compatible = "rockchip,rk3588-qos", "syscon";
1495 compatible = "rockchip,rk3588-qos", "syscon";
1500 compatible = "rockchip,rk3588-qos", "syscon";
1505 compatible = "rockchip,rk3588-qos", "syscon";
1510 compatible = "rockchip,rk3588-qos", "syscon";
1515 compatible = "rockchip,rk3588-qos", "syscon";
1520 compatible = "rockchip,rk3588-qos", "syscon";
1525 compatible = "rockchip,rk3588-qos", "syscon";
1530 compatible = "rockchip,rk3588-qos", "syscon";
1535 compatible = "rockchip,rk3588-qos", "syscon";
1540 compatible = "rockchip,rk3588-qos", "syscon";
1545 compatible = "rockchip,rk3588-qos", "syscon";
1550 compatible = "rockchip,rk3588-qos", "syscon";
1555 compatible = "rockchip,rk3588-qos", "syscon";
1560 compatible = "rockchip,rk3588-qos", "syscon";
1565 compatible = "rockchip,rk3588-qos", "syscon";
1570 compatible = "rockchip,rk3588-qos", "syscon";
1575 compatible = "rockchip,rk3588-qos", "syscon";
1580 compatible = "rockchip,rk3588-qos", "syscon";
1585 compatible = "rockchip,rk3588-qos", "syscon";
1590 compatible = "rockchip,rk3588-qos", "syscon";
1595 compatible = "rockchip,rk3588-qos", "syscon";
1600 compatible = "rockchip,rk3588-qos", "syscon";
1605 compatible = "rockchip,rk3588-qos", "syscon";
1610 compatible = "rockchip,rk3588-qos", "syscon";
1615 compatible = "rockchip,rk3588-qos", "syscon";
1620 compatible = "rockchip,rk3588-qos", "syscon";
1625 compatible = "rockchip,rk3588-qos", "syscon";
1630 compatible = "rockchip,rk3588-qos", "syscon";
1635 compatible = "rockchip,rk3588-qos", "syscon";
1640 compatible = "rockchip,rk3588-qos", "syscon";
1645 compatible = "rockchip,rk3588-qos", "syscon";
1650 compatible = "rockchip,rk3588-qos", "syscon";
1656 compatible = "rockchip,rk3588-dfi";
1665 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1666 bus-range = <0x30 0x3f>;
1670 clock-names = "aclk_mst", "aclk_slv",
1679 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1680 #interrupt-cells = <1>;
1681 interrupt-map-mask = <0 0 0 7>;
1682 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
1686 linux,pci-domain = <3>;
1687 max-link-speed = <2>;
1688 msi-map = <0x3000 &its0 0x3000 0x1000>;
1689 num-lanes = <1>;
1691 phy-names = "pcie-phy";
1692 power-domains = <&power RK3588_PD_PCIE>;
1699 reg-names = "dbi", "apb", "config";
1701 reset-names = "pwr", "pipe";
1702 #address-cells = <3>;
1703 #size-cells = <2>;
1706 pcie2x1l1_intc: legacy-interrupt-controller {
1707 interrupt-controller;
1708 #address-cells = <0>;
1709 #interrupt-cells = <1>;
1710 interrupt-parent = <&gic>;
1716 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1717 bus-range = <0x40 0x4f>;
1721 clock-names = "aclk_mst", "aclk_slv",
1730 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1731 #interrupt-cells = <1>;
1732 interrupt-map-mask = <0 0 0 7>;
1733 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
1737 linux,pci-domain = <4>;
1738 max-link-speed = <2>;
1739 msi-map = <0x4000 &its0 0x4000 0x1000>;
1740 num-lanes = <1>;
1742 phy-names = "pcie-phy";
1743 power-domains = <&power RK3588_PD_PCIE>;
1750 reg-names = "dbi", "apb", "config";
1752 reset-names = "pwr", "pipe";
1753 #address-cells = <3>;
1754 #size-cells = <2>;
1757 pcie2x1l2_intc: legacy-interrupt-controller {
1758 interrupt-controller;
1759 #address-cells = <0>;
1760 #interrupt-cells = <1>;
1761 interrupt-parent = <&gic>;
1767 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
1771 interrupt-names = "macirq", "eth_wake_irq";
1775 clock-names = "stmmaceth", "clk_mac_ref",
1778 power-domains = <&power RK3588_PD_GMAC>;
1780 reset-names = "stmmaceth";
1782 rockchip,php-grf = <&php_grf>;
1783 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1784 snps,mixed-burst;
1785 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1786 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1791 compatible = "snps,dwmac-mdio";
1792 #address-cells = <0x1>;
1793 #size-cells = <0x0>;
1796 gmac1_stmmac_axi_setup: stmmac-axi-config {
1802 gmac1_mtl_rx_setup: rx-queues-config {
1803 snps,rx-queues-to-use = <2>;
1808 gmac1_mtl_tx_setup: tx-queues-config {
1809 snps,tx-queues-to-use = <2>;
1816 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1822 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1823 ports-implemented = <0x1>;
1824 #address-cells = <1>;
1825 #size-cells = <0>;
1828 sata-port@0 {
1830 hba-port-cap = <HBA_PORT_FBSCP>;
1832 phy-names = "sata-phy";
1833 snps,rx-ts-max = <32>;
1834 snps,tx-ts-max = <32>;
1839 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1845 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1846 ports-implemented = <0x1>;
1847 #address-cells = <1>;
1848 #size-cells = <0>;
1851 sata-port@0 {
1853 hba-port-cap = <HBA_PORT_FBSCP>;
1855 phy-names = "sata-phy";
1856 snps,rx-ts-max = <32>;
1857 snps,tx-ts-max = <32>;
1866 clock-names = "clk_sfc", "hclk_sfc";
1867 #address-cells = <1>;
1868 #size-cells = <0>;
1873 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1878 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1879 fifo-depth = <0x100>;
1880 max-frequency = <200000000>;
1881 pinctrl-names = "default";
1882 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1883 power-domains = <&power RK3588_PD_SDMMC>;
1888 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1893 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1894 fifo-depth = <0x100>;
1895 max-frequency = <200000000>;
1896 pinctrl-names = "default";
1897 pinctrl-0 = <&sdiom1_pins>;
1898 power-domains = <&power RK3588_PD_SDIO>;
1903 compatible = "rockchip,rk3588-dwcmshc";
1906 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
1907 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1911 clock-names = "core", "bus", "axi", "block", "timer";
1912 max-frequency = <200000000>;
1913 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1915 pinctrl-names = "default";
1919 reset-names = "core", "bus", "axi", "block", "timer";
1924 compatible = "rockchip,rk3588-i2s-tdm";
1928 clock-names = "mclk_tx", "mclk_rx", "hclk";
1929 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1930 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
1932 dma-names = "tx", "rx";
1933 power-domains = <&power RK3588_PD_AUDIO>;
1935 reset-names = "tx-m", "rx-m";
1936 rockchip,trcm-sync-tx-only;
1937 pinctrl-names = "default";
1938 pinctrl-0 = <&i2s0_lrck
1948 #sound-dai-cells = <0>;
1953 compatible = "rockchip,rk3588-i2s-tdm";
1957 clock-names = "mclk_tx", "mclk_rx", "hclk";
1959 dma-names = "tx", "rx";
1961 reset-names = "tx-m", "rx-m";
1962 rockchip,trcm-sync-tx-only;
1963 pinctrl-names = "default";
1964 pinctrl-0 = <&i2s1m0_lrck
1974 #sound-dai-cells = <0>;
1979 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1983 clock-names = "i2s_clk", "i2s_hclk";
1984 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1985 assigned-clock-parents = <&cru PLL_AUPLL>;
1987 dma-names = "tx", "rx";
1988 power-domains = <&power RK3588_PD_AUDIO>;
1989 pinctrl-names = "default";
1990 pinctrl-0 = <&i2s2m1_lrck
1994 #sound-dai-cells = <0>;
1999 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
2003 clock-names = "i2s_clk", "i2s_hclk";
2004 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
2005 assigned-clock-parents = <&cru PLL_AUPLL>;
2007 dma-names = "tx", "rx";
2008 power-domains = <&power RK3588_PD_AUDIO>;
2009 pinctrl-names = "default";
2010 pinctrl-0 = <&i2s3_lrck
2014 #sound-dai-cells = <0>;
2018 gic: interrupt-controller@fe600000 {
2019 compatible = "arm,gic-v3";
2023 interrupt-controller;
2024 mbi-alias = <0x0 0xfe610000>;
2025 mbi-ranges = <424 56>;
2026 msi-controller;
2028 #address-cells = <2>;
2029 #interrupt-cells = <4>;
2030 #size-cells = <2>;
2032 its0: msi-controller@fe640000 {
2033 compatible = "arm,gic-v3-its";
2035 msi-controller;
2036 #msi-cells = <1>;
2039 its1: msi-controller@fe660000 {
2040 compatible = "arm,gic-v3-its";
2042 msi-controller;
2043 #msi-cells = <1>;
2046 ppi-partitions {
2047 ppi_partition0: interrupt-partition-0 {
2051 ppi_partition1: interrupt-partition-1 {
2057 dmac0: dma-controller@fea10000 {
2062 arm,pl330-periph-burst;
2064 clock-names = "apb_pclk";
2065 #dma-cells = <1>;
2068 dmac1: dma-controller@fea30000 {
2073 arm,pl330-periph-burst;
2075 clock-names = "apb_pclk";
2076 #dma-cells = <1>;
2080 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2083 clock-names = "i2c", "pclk";
2085 pinctrl-0 = <&i2c1m0_xfer>;
2086 pinctrl-names = "default";
2087 #address-cells = <1>;
2088 #size-cells = <0>;
2093 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2096 clock-names = "i2c", "pclk";
2098 pinctrl-0 = <&i2c2m0_xfer>;
2099 pinctrl-names = "default";
2100 #address-cells = <1>;
2101 #size-cells = <0>;
2106 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2109 clock-names = "i2c", "pclk";
2111 pinctrl-0 = <&i2c3m0_xfer>;
2112 pinctrl-names = "default";
2113 #address-cells = <1>;
2114 #size-cells = <0>;
2119 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2122 clock-names = "i2c", "pclk";
2124 pinctrl-0 = <&i2c4m0_xfer>;
2125 pinctrl-names = "default";
2126 #address-cells = <1>;
2127 #size-cells = <0>;
2132 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2135 clock-names = "i2c", "pclk";
2137 pinctrl-0 = <&i2c5m0_xfer>;
2138 pinctrl-names = "default";
2139 #address-cells = <1>;
2140 #size-cells = <0>;
2145 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
2149 clock-names = "pclk", "timer";
2153 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
2156 clock-names = "tclk", "pclk";
2161 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2165 clock-names = "spiclk", "apb_pclk";
2167 dma-names = "tx", "rx";
2168 num-cs = <2>;
2169 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
2170 pinctrl-names = "default";
2171 #address-cells = <1>;
2172 #size-cells = <0>;
2177 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2181 clock-names = "spiclk", "apb_pclk";
2183 dma-names = "tx", "rx";
2184 num-cs = <2>;
2185 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
2186 pinctrl-names = "default";
2187 #address-cells = <1>;
2188 #size-cells = <0>;
2193 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2197 clock-names = "spiclk", "apb_pclk";
2199 dma-names = "tx", "rx";
2200 num-cs = <2>;
2201 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
2202 pinctrl-names = "default";
2203 #address-cells = <1>;
2204 #size-cells = <0>;
2209 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2213 clock-names = "spiclk", "apb_pclk";
2215 dma-names = "tx", "rx";
2216 num-cs = <2>;
2217 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
2218 pinctrl-names = "default";
2219 #address-cells = <1>;
2220 #size-cells = <0>;
2225 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2229 clock-names = "baudclk", "apb_pclk";
2231 dma-names = "tx", "rx";
2232 pinctrl-0 = <&uart1m1_xfer>;
2233 pinctrl-names = "default";
2234 reg-io-width = <4>;
2235 reg-shift = <2>;
2240 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2244 clock-names = "baudclk", "apb_pclk";
2246 dma-names = "tx", "rx";
2247 pinctrl-0 = <&uart2m1_xfer>;
2248 pinctrl-names = "default";
2249 reg-io-width = <4>;
2250 reg-shift = <2>;
2255 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2259 clock-names = "baudclk", "apb_pclk";
2261 dma-names = "tx", "rx";
2262 pinctrl-0 = <&uart3m1_xfer>;
2263 pinctrl-names = "default";
2264 reg-io-width = <4>;
2265 reg-shift = <2>;
2270 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2274 clock-names = "baudclk", "apb_pclk";
2276 dma-names = "tx", "rx";
2277 pinctrl-0 = <&uart4m1_xfer>;
2278 pinctrl-names = "default";
2279 reg-io-width = <4>;
2280 reg-shift = <2>;
2285 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2289 clock-names = "baudclk", "apb_pclk";
2291 dma-names = "tx", "rx";
2292 pinctrl-0 = <&uart5m1_xfer>;
2293 pinctrl-names = "default";
2294 reg-io-width = <4>;
2295 reg-shift = <2>;
2300 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2304 clock-names = "baudclk", "apb_pclk";
2306 dma-names = "tx", "rx";
2307 pinctrl-0 = <&uart6m1_xfer>;
2308 pinctrl-names = "default";
2309 reg-io-width = <4>;
2310 reg-shift = <2>;
2315 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2319 clock-names = "baudclk", "apb_pclk";
2321 dma-names = "tx", "rx";
2322 pinctrl-0 = <&uart7m1_xfer>;
2323 pinctrl-names = "default";
2324 reg-io-width = <4>;
2325 reg-shift = <2>;
2330 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2334 clock-names = "baudclk", "apb_pclk";
2336 dma-names = "tx", "rx";
2337 pinctrl-0 = <&uart8m1_xfer>;
2338 pinctrl-names = "default";
2339 reg-io-width = <4>;
2340 reg-shift = <2>;
2345 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2349 clock-names = "baudclk", "apb_pclk";
2351 dma-names = "tx", "rx";
2352 pinctrl-0 = <&uart9m1_xfer>;
2353 pinctrl-names = "default";
2354 reg-io-width = <4>;
2355 reg-shift = <2>;
2360 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2363 clock-names = "pwm", "pclk";
2364 pinctrl-0 = <&pwm4m0_pins>;
2365 pinctrl-names = "default";
2366 #pwm-cells = <3>;
2371 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2374 clock-names = "pwm", "pclk";
2375 pinctrl-0 = <&pwm5m0_pins>;
2376 pinctrl-names = "default";
2377 #pwm-cells = <3>;
2382 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2385 clock-names = "pwm", "pclk";
2386 pinctrl-0 = <&pwm6m0_pins>;
2387 pinctrl-names = "default";
2388 #pwm-cells = <3>;
2393 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2396 clock-names = "pwm", "pclk";
2397 pinctrl-0 = <&pwm7m0_pins>;
2398 pinctrl-names = "default";
2399 #pwm-cells = <3>;
2404 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2407 clock-names = "pwm", "pclk";
2408 pinctrl-0 = <&pwm8m0_pins>;
2409 pinctrl-names = "default";
2410 #pwm-cells = <3>;
2415 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2418 clock-names = "pwm", "pclk";
2419 pinctrl-0 = <&pwm9m0_pins>;
2420 pinctrl-names = "default";
2421 #pwm-cells = <3>;
2426 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2429 clock-names = "pwm", "pclk";
2430 pinctrl-0 = <&pwm10m0_pins>;
2431 pinctrl-names = "default";
2432 #pwm-cells = <3>;
2437 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2440 clock-names = "pwm", "pclk";
2441 pinctrl-0 = <&pwm11m0_pins>;
2442 pinctrl-names = "default";
2443 #pwm-cells = <3>;
2448 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2451 clock-names = "pwm", "pclk";
2452 pinctrl-0 = <&pwm12m0_pins>;
2453 pinctrl-names = "default";
2454 #pwm-cells = <3>;
2459 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2462 clock-names = "pwm", "pclk";
2463 pinctrl-0 = <&pwm13m0_pins>;
2464 pinctrl-names = "default";
2465 #pwm-cells = <3>;
2470 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2473 clock-names = "pwm", "pclk";
2474 pinctrl-0 = <&pwm14m0_pins>;
2475 pinctrl-names = "default";
2476 #pwm-cells = <3>;
2481 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2484 clock-names = "pwm", "pclk";
2485 pinctrl-0 = <&pwm15m0_pins>;
2486 pinctrl-names = "default";
2487 #pwm-cells = <3>;
2491 thermal_zones: thermal-zones {
2493 package_thermal: package-thermal {
2494 polling-delay-passive = <0>;
2495 polling-delay = <0>;
2496 thermal-sensors = <&tsadc 0>;
2499 package_crit: package-crit {
2508 bigcore0_thermal: bigcore0-thermal {
2509 polling-delay-passive = <100>;
2510 polling-delay = <0>;
2511 thermal-sensors = <&tsadc 1>;
2514 bigcore0_alert: bigcore0-alert {
2520 bigcore0_crit: bigcore0-crit {
2527 cooling-maps {
2530 cooling-device =
2538 bigcore2_thermal: bigcore2-thermal {
2539 polling-delay-passive = <100>;
2540 polling-delay = <0>;
2541 thermal-sensors = <&tsadc 2>;
2544 bigcore2_alert: bigcore2-alert {
2550 bigcore2_crit: bigcore2-crit {
2557 cooling-maps {
2560 cooling-device =
2568 little_core_thermal: littlecore-thermal {
2569 polling-delay-passive = <100>;
2570 polling-delay = <0>;
2571 thermal-sensors = <&tsadc 3>;
2574 littlecore_alert: littlecore-alert {
2580 littlecore_crit: littlecore-crit {
2587 cooling-maps {
2590 cooling-device =
2600 center_thermal: center-thermal {
2601 polling-delay-passive = <0>;
2602 polling-delay = <0>;
2603 thermal-sensors = <&tsadc 4>;
2606 center_crit: center-crit {
2614 gpu_thermal: gpu-thermal {
2615 polling-delay-passive = <100>;
2616 polling-delay = <0>;
2617 thermal-sensors = <&tsadc 5>;
2620 gpu_alert: gpu-alert {
2626 gpu_crit: gpu-crit {
2633 cooling-maps {
2636 cooling-device =
2642 npu_thermal: npu-thermal {
2643 polling-delay-passive = <0>;
2644 polling-delay = <0>;
2645 thermal-sensors = <&tsadc 6>;
2648 npu_crit: npu-crit {
2657 tsadc: tsadc@fec00000 { label
2658 compatible = "rockchip,rk3588-tsadc";
2662 clock-names = "tsadc", "apb_pclk";
2663 assigned-clocks = <&cru CLK_TSADC>;
2664 assigned-clock-rates = <2000000>;
2666 reset-names = "tsadc-apb", "tsadc";
2667 rockchip,hw-tshut-temp = <120000>;
2668 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2669 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2670 pinctrl-0 = <&tsadc_gpio_func>;
2671 pinctrl-1 = <&tsadc_shut>;
2672 pinctrl-names = "gpio", "otpout";
2673 #thermal-sensor-cells = <1>;
2678 compatible = "rockchip,rk3588-saradc";
2681 #io-channel-cells = <1>;
2683 clock-names = "saradc", "apb_pclk";
2685 reset-names = "saradc-apb";
2690 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2693 clock-names = "i2c", "pclk";
2695 pinctrl-0 = <&i2c6m0_xfer>;
2696 pinctrl-names = "default";
2697 #address-cells = <1>;
2698 #size-cells = <0>;
2703 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2706 clock-names = "i2c", "pclk";
2708 pinctrl-0 = <&i2c7m0_xfer>;
2709 pinctrl-names = "default";
2710 #address-cells = <1>;
2711 #size-cells = <0>;
2716 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2719 clock-names = "i2c", "pclk";
2721 pinctrl-0 = <&i2c8m0_xfer>;
2722 pinctrl-names = "default";
2723 #address-cells = <1>;
2724 #size-cells = <0>;
2729 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2733 clock-names = "spiclk", "apb_pclk";
2735 dma-names = "tx", "rx";
2736 num-cs = <2>;
2737 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
2738 pinctrl-names = "default";
2739 #address-cells = <1>;
2740 #size-cells = <0>;
2745 compatible = "rockchip,rk3588-otp";
2749 clock-names = "otp", "apb_pclk", "phy", "arb";
2752 reset-names = "otp", "apb", "arb";
2753 #address-cells = <1>;
2754 #size-cells = <1>;
2756 cpu_code: cpu-code@2 {
2764 cpub0_leakage: cpu-leakage@17 {
2768 cpub1_leakage: cpu-leakage@18 {
2772 cpul_leakage: cpu-leakage@19 {
2776 log_leakage: log-leakage@1a {
2780 gpu_leakage: gpu-leakage@1b {
2784 otp_cpu_version: cpu-version@1c {
2789 npu_leakage: npu-leakage@28 {
2793 codec_leakage: codec-leakage@29 {
2798 dmac2: dma-controller@fed10000 {
2803 arm,pl330-periph-burst;
2805 clock-names = "apb_pclk";
2806 #dma-cells = <1>;
2810 compatible = "rockchip,rk3588-hdptx-phy";
2813 clock-names = "ref", "apb";
2814 #phy-cells = <0>;
2819 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
2826 compatible = "rockchip,rk3588-usbdp-phy";
2828 #phy-cells = <1>;
2833 clock-names = "refclk", "immortal", "pclk", "utmi";
2839 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
2840 rockchip,u2phy-grf = <&usb2phy0_grf>;
2841 rockchip,usb-grf = <&usb_grf>;
2842 rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
2843 rockchip,vo-grf = <&vo0_grf>;
2848 compatible = "rockchip,rk3588-naneng-combphy";
2852 clock-names = "ref", "apb", "pipe";
2853 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
2854 assigned-clock-rates = <100000000>;
2855 #phy-cells = <1>;
2857 reset-names = "phy", "apb";
2858 rockchip,pipe-grf = <&php_grf>;
2859 rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
2864 compatible = "rockchip,rk3588-naneng-combphy";
2868 clock-names = "ref", "apb", "pipe";
2869 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
2870 assigned-clock-rates = <100000000>;
2871 #phy-cells = <1>;
2873 reset-names = "phy", "apb";
2874 rockchip,pipe-grf = <&php_grf>;
2875 rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
2880 compatible = "mmio-sram";
2883 #address-cells = <1>;
2884 #size-cells = <1>;
2888 compatible = "rockchip,rk3588-pinctrl";
2891 #address-cells = <2>;
2892 #size-cells = <2>;
2895 compatible = "rockchip,gpio-bank";
2899 gpio-controller;
2900 gpio-ranges = <&pinctrl 0 0 32>;
2901 interrupt-controller;
2902 #gpio-cells = <2>;
2903 #interrupt-cells = <2>;
2907 compatible = "rockchip,gpio-bank";
2911 gpio-controller;
2912 gpio-ranges = <&pinctrl 0 32 32>;
2913 interrupt-controller;
2914 #gpio-cells = <2>;
2915 #interrupt-cells = <2>;
2919 compatible = "rockchip,gpio-bank";
2923 gpio-controller;
2924 gpio-ranges = <&pinctrl 0 64 32>;
2925 interrupt-controller;
2926 #gpio-cells = <2>;
2927 #interrupt-cells = <2>;
2931 compatible = "rockchip,gpio-bank";
2935 gpio-controller;
2936 gpio-ranges = <&pinctrl 0 96 32>;
2937 interrupt-controller;
2938 #gpio-cells = <2>;
2939 #interrupt-cells = <2>;
2943 compatible = "rockchip,gpio-bank";
2947 gpio-controller;
2948 gpio-ranges = <&pinctrl 0 128 32>;
2949 interrupt-controller;
2950 #gpio-cells = <2>;
2951 #interrupt-cells = <2>;
2956 #include "rk3588-base-pinctrl.dtsi"