Lines Matching +full:rk3288 +full:- +full:efuse
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/power/rk3588-power.h>
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/ata/ahci.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
55 #address-cells = <1>;
56 #size-cells = <0>;
58 cpu-map {
93 compatible = "arm,cortex-a55";
95 enable-method = "psci";
96 capacity-dmips-mhz = <530>;
98 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
99 assigned-clock-rates = <816000000>;
100 cpu-idle-states = <&CPU_SLEEP>;
101 i-cache-size = <32768>;
102 i-cache-line-size = <64>;
103 i-cache-sets = <128>;
104 d-cache-size = <32768>;
105 d-cache-line-size = <64>;
106 d-cache-sets = <128>;
107 next-level-cache = <&l2_cache_l0>;
108 dynamic-power-coefficient = <228>;
109 #cooling-cells = <2>;
114 compatible = "arm,cortex-a55";
116 enable-method = "psci";
117 capacity-dmips-mhz = <530>;
119 cpu-idle-states = <&CPU_SLEEP>;
120 i-cache-size = <32768>;
121 i-cache-line-size = <64>;
122 i-cache-sets = <128>;
123 d-cache-size = <32768>;
124 d-cache-line-size = <64>;
125 d-cache-sets = <128>;
126 next-level-cache = <&l2_cache_l1>;
127 dynamic-power-coefficient = <228>;
128 #cooling-cells = <2>;
133 compatible = "arm,cortex-a55";
135 enable-method = "psci";
136 capacity-dmips-mhz = <530>;
138 cpu-idle-states = <&CPU_SLEEP>;
139 i-cache-size = <32768>;
140 i-cache-line-size = <64>;
141 i-cache-sets = <128>;
142 d-cache-size = <32768>;
143 d-cache-line-size = <64>;
144 d-cache-sets = <128>;
145 next-level-cache = <&l2_cache_l2>;
146 dynamic-power-coefficient = <228>;
147 #cooling-cells = <2>;
152 compatible = "arm,cortex-a55";
154 enable-method = "psci";
155 capacity-dmips-mhz = <530>;
157 cpu-idle-states = <&CPU_SLEEP>;
158 i-cache-size = <32768>;
159 i-cache-line-size = <64>;
160 i-cache-sets = <128>;
161 d-cache-size = <32768>;
162 d-cache-line-size = <64>;
163 d-cache-sets = <128>;
164 next-level-cache = <&l2_cache_l3>;
165 dynamic-power-coefficient = <228>;
166 #cooling-cells = <2>;
171 compatible = "arm,cortex-a76";
173 enable-method = "psci";
174 capacity-dmips-mhz = <1024>;
176 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
177 assigned-clock-rates = <816000000>;
178 cpu-idle-states = <&CPU_SLEEP>;
179 i-cache-size = <65536>;
180 i-cache-line-size = <64>;
181 i-cache-sets = <256>;
182 d-cache-size = <65536>;
183 d-cache-line-size = <64>;
184 d-cache-sets = <256>;
185 next-level-cache = <&l2_cache_b0>;
186 dynamic-power-coefficient = <416>;
187 #cooling-cells = <2>;
192 compatible = "arm,cortex-a76";
194 enable-method = "psci";
195 capacity-dmips-mhz = <1024>;
197 cpu-idle-states = <&CPU_SLEEP>;
198 i-cache-size = <65536>;
199 i-cache-line-size = <64>;
200 i-cache-sets = <256>;
201 d-cache-size = <65536>;
202 d-cache-line-size = <64>;
203 d-cache-sets = <256>;
204 next-level-cache = <&l2_cache_b1>;
205 dynamic-power-coefficient = <416>;
206 #cooling-cells = <2>;
211 compatible = "arm,cortex-a76";
213 enable-method = "psci";
214 capacity-dmips-mhz = <1024>;
216 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
217 assigned-clock-rates = <816000000>;
218 cpu-idle-states = <&CPU_SLEEP>;
219 i-cache-size = <65536>;
220 i-cache-line-size = <64>;
221 i-cache-sets = <256>;
222 d-cache-size = <65536>;
223 d-cache-line-size = <64>;
224 d-cache-sets = <256>;
225 next-level-cache = <&l2_cache_b2>;
226 dynamic-power-coefficient = <416>;
227 #cooling-cells = <2>;
232 compatible = "arm,cortex-a76";
234 enable-method = "psci";
235 capacity-dmips-mhz = <1024>;
237 cpu-idle-states = <&CPU_SLEEP>;
238 i-cache-size = <65536>;
239 i-cache-line-size = <64>;
240 i-cache-sets = <256>;
241 d-cache-size = <65536>;
242 d-cache-line-size = <64>;
243 d-cache-sets = <256>;
244 next-level-cache = <&l2_cache_b3>;
245 dynamic-power-coefficient = <416>;
246 #cooling-cells = <2>;
249 idle-states {
250 entry-method = "psci";
251 CPU_SLEEP: cpu-sleep {
252 compatible = "arm,idle-state";
253 local-timer-stop;
254 arm,psci-suspend-param = <0x0010000>;
255 entry-latency-us = <100>;
256 exit-latency-us = <120>;
257 min-residency-us = <1000>;
261 l2_cache_l0: l2-cache-l0 {
263 cache-size = <131072>;
264 cache-line-size = <64>;
265 cache-sets = <512>;
266 cache-level = <2>;
267 cache-unified;
268 next-level-cache = <&l3_cache>;
271 l2_cache_l1: l2-cache-l1 {
273 cache-size = <131072>;
274 cache-line-size = <64>;
275 cache-sets = <512>;
276 cache-level = <2>;
277 cache-unified;
278 next-level-cache = <&l3_cache>;
281 l2_cache_l2: l2-cache-l2 {
283 cache-size = <131072>;
284 cache-line-size = <64>;
285 cache-sets = <512>;
286 cache-level = <2>;
287 cache-unified;
288 next-level-cache = <&l3_cache>;
291 l2_cache_l3: l2-cache-l3 {
293 cache-size = <131072>;
294 cache-line-size = <64>;
295 cache-sets = <512>;
296 cache-level = <2>;
297 cache-unified;
298 next-level-cache = <&l3_cache>;
301 l2_cache_b0: l2-cache-b0 {
303 cache-size = <524288>;
304 cache-line-size = <64>;
305 cache-sets = <1024>;
306 cache-level = <2>;
307 cache-unified;
308 next-level-cache = <&l3_cache>;
311 l2_cache_b1: l2-cache-b1 {
313 cache-size = <524288>;
314 cache-line-size = <64>;
315 cache-sets = <1024>;
316 cache-level = <2>;
317 cache-unified;
318 next-level-cache = <&l3_cache>;
321 l2_cache_b2: l2-cache-b2 {
323 cache-size = <524288>;
324 cache-line-size = <64>;
325 cache-sets = <1024>;
326 cache-level = <2>;
327 cache-unified;
328 next-level-cache = <&l3_cache>;
331 l2_cache_b3: l2-cache-b3 {
333 cache-size = <524288>;
334 cache-line-size = <64>;
335 cache-sets = <1024>;
336 cache-level = <2>;
337 cache-unified;
338 next-level-cache = <&l3_cache>;
346 l3_cache: l3-cache {
348 cache-size = <3145728>;
349 cache-line-size = <64>;
350 cache-sets = <4096>;
351 cache-level = <3>;
352 cache-unified;
355 display_subsystem: display-subsystem {
356 compatible = "rockchip,display-subsystem";
362 compatible = "linaro,optee-tz";
367 compatible = "arm,scmi-smc";
368 arm,smc-id = <0x82000010>;
370 #address-cells = <1>;
371 #size-cells = <0>;
375 #clock-cells = <1>;
380 #reset-cells = <1>;
385 pmu-a55 {
386 compatible = "arm,cortex-a55-pmu";
390 pmu-a76 {
391 compatible = "arm,cortex-a76-pmu";
396 compatible = "arm,psci-1.0";
400 spll: clock-0 {
401 compatible = "fixed-clock";
402 clock-frequency = <702000000>;
403 clock-output-names = "spll";
404 #clock-cells = <0>;
408 compatible = "arm,armv8-timer";
414 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
417 xin24m: clock-1 {
418 compatible = "fixed-clock";
419 clock-frequency = <24000000>;
420 clock-output-names = "xin24m";
421 #clock-cells = <0>;
424 xin32k: clock-2 {
425 compatible = "fixed-clock";
426 clock-frequency = <32768>;
427 clock-output-names = "xin32k";
428 #clock-cells = <0>;
432 compatible = "mmio-sram";
435 #address-cells = <1>;
436 #size-cells = <1>;
439 compatible = "arm,scmi-shmem";
445 compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
447 #cooling-cells = <2>;
448 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
449 assigned-clock-rates = <200000000>;
452 clock-names = "core", "coregroup", "stacks";
453 dynamic-power-coefficient = <2982>;
457 interrupt-names = "job", "mmu", "gpu";
458 power-domains = <&power RK3588_PD_GPU>;
463 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
468 clock-names = "ref_clk", "suspend_clk", "bus_clk";
471 phy-names = "usb2-phy", "usb3-phy";
473 power-domains = <&power RK3588_PD_USB>;
476 snps,dis-u1-entry-quirk;
477 snps,dis-u2-entry-quirk;
478 snps,dis-u2-freeclk-exists-quirk;
479 snps,dis-del-phy-power-chg-quirk;
480 snps,dis-tx-ipgap-linecheck-quirk;
485 compatible = "rockchip,rk3588-ehci", "generic-ehci";
490 phy-names = "usb";
491 power-domains = <&power RK3588_PD_USB>;
496 compatible = "rockchip,rk3588-ohci", "generic-ohci";
501 phy-names = "usb";
502 power-domains = <&power RK3588_PD_USB>;
507 compatible = "rockchip,rk3588-ehci", "generic-ehci";
512 phy-names = "usb";
513 power-domains = <&power RK3588_PD_USB>;
518 compatible = "rockchip,rk3588-ohci", "generic-ohci";
523 phy-names = "usb";
524 power-domains = <&power RK3588_PD_USB>;
529 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
535 clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
538 phy-names = "usb3-phy";
542 snps,dis-u2-freeclk-exists-quirk;
543 snps,dis-del-phy-power-chg-quirk;
544 snps,dis-tx-ipgap-linecheck-quirk;
550 compatible = "arm,smmu-v3";
556 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
557 #iommu-cells = <1>;
562 compatible = "arm,smmu-v3";
568 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
569 #iommu-cells = <1>;
574 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
579 compatible = "rockchip,rk3588-sys-grf", "syscon";
584 compatible = "rockchip,rk3588-vop-grf", "syscon";
589 compatible = "rockchip,rk3588-vo0-grf", "syscon";
595 compatible = "rockchip,rk3588-vo1-grf", "syscon";
601 compatible = "rockchip,rk3588-usb-grf", "syscon";
606 compatible = "rockchip,rk3588-php-grf", "syscon";
611 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
616 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
621 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
626 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
628 #address-cells = <1>;
629 #size-cells = <1>;
632 compatible = "rockchip,rk3588-usb2phy";
634 #clock-cells = <0>;
636 clock-names = "phyclk";
637 clock-output-names = "usb480m_phy0";
640 reset-names = "phy", "apb";
643 u2phy0_otg: otg-port {
644 #phy-cells = <0>;
651 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
653 #address-cells = <1>;
654 #size-cells = <1>;
657 compatible = "rockchip,rk3588-usb2phy";
659 #clock-cells = <0>;
661 clock-names = "phyclk";
662 clock-output-names = "usb480m_phy2";
665 reset-names = "phy", "apb";
668 u2phy2_host: host-port {
669 #phy-cells = <0>;
676 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
678 #address-cells = <1>;
679 #size-cells = <1>;
682 compatible = "rockchip,rk3588-usb2phy";
684 #clock-cells = <0>;
686 clock-names = "phyclk";
687 clock-output-names = "usb480m_phy3";
690 reset-names = "phy", "apb";
693 u2phy3_host: host-port {
694 #phy-cells = <0>;
701 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
706 compatible = "rockchip,rk3588-ioc", "syscon";
711 compatible = "mmio-sram";
714 #address-cells = <1>;
715 #size-cells = <1>;
718 cru: clock-controller@fd7c0000 {
719 compatible = "rockchip,rk3588-cru";
721 assigned-clocks =
731 assigned-clock-rates =
742 #clock-cells = <1>;
743 #reset-cells = <1>;
747 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
751 clock-names = "i2c", "pclk";
752 pinctrl-0 = <&i2c0m0_xfer>;
753 pinctrl-names = "default";
754 #address-cells = <1>;
755 #size-cells = <0>;
760 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
764 clock-names = "baudclk", "apb_pclk";
766 dma-names = "tx", "rx";
767 pinctrl-0 = <&uart0m1_xfer>;
768 pinctrl-names = "default";
769 reg-shift = <2>;
770 reg-io-width = <4>;
775 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
778 clock-names = "pwm", "pclk";
779 pinctrl-0 = <&pwm0m0_pins>;
780 pinctrl-names = "default";
781 #pwm-cells = <3>;
786 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
789 clock-names = "pwm", "pclk";
790 pinctrl-0 = <&pwm1m0_pins>;
791 pinctrl-names = "default";
792 #pwm-cells = <3>;
797 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
800 clock-names = "pwm", "pclk";
801 pinctrl-0 = <&pwm2m0_pins>;
802 pinctrl-names = "default";
803 #pwm-cells = <3>;
808 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
811 clock-names = "pwm", "pclk";
812 pinctrl-0 = <&pwm3m0_pins>;
813 pinctrl-names = "default";
814 #pwm-cells = <3>;
818 pmu: power-management@fd8d8000 {
819 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
822 power: power-controller {
823 compatible = "rockchip,rk3588-power-controller";
824 #address-cells = <1>;
825 #power-domain-cells = <1>;
826 #size-cells = <0>;
830 power-domain@RK3588_PD_NPU {
832 #power-domain-cells = <0>;
833 #address-cells = <1>;
834 #size-cells = <0>;
836 power-domain@RK3588_PD_NPUTOP {
845 #power-domain-cells = <0>;
846 #address-cells = <1>;
847 #size-cells = <0>;
849 power-domain@RK3588_PD_NPU1 {
855 #power-domain-cells = <0>;
857 power-domain@RK3588_PD_NPU2 {
863 #power-domain-cells = <0>;
868 power-domain@RK3588_PD_GPU {
877 #power-domain-cells = <0>;
880 power-domain@RK3588_PD_VCODEC {
882 #address-cells = <1>;
883 #size-cells = <0>;
884 #power-domain-cells = <0>;
886 power-domain@RK3588_PD_RKVDEC0 {
894 #power-domain-cells = <0>;
896 power-domain@RK3588_PD_RKVDEC1 {
903 #power-domain-cells = <0>;
905 power-domain@RK3588_PD_VENC0 {
912 #address-cells = <1>;
913 #size-cells = <0>;
914 #power-domain-cells = <0>;
916 power-domain@RK3588_PD_VENC1 {
925 #power-domain-cells = <0>;
930 power-domain@RK3588_PD_VDPU {
958 #address-cells = <1>;
959 #size-cells = <0>;
960 #power-domain-cells = <0>;
963 power-domain@RK3588_PD_AV1 {
969 #power-domain-cells = <0>;
971 power-domain@RK3588_PD_RKVDEC0 {
978 #power-domain-cells = <0>;
980 power-domain@RK3588_PD_RKVDEC1 {
986 #power-domain-cells = <0>;
988 power-domain@RK3588_PD_RGA30 {
993 #power-domain-cells = <0>;
996 power-domain@RK3588_PD_VOP {
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1005 #power-domain-cells = <0>;
1007 power-domain@RK3588_PD_VO0 {
1017 #power-domain-cells = <0>;
1020 power-domain@RK3588_PD_VO1 {
1031 #power-domain-cells = <0>;
1033 power-domain@RK3588_PD_VI {
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1047 #power-domain-cells = <0>;
1049 power-domain@RK3588_PD_ISP1 {
1057 #power-domain-cells = <0>;
1059 power-domain@RK3588_PD_FEC {
1068 #power-domain-cells = <0>;
1071 power-domain@RK3588_PD_RGA31 {
1076 #power-domain-cells = <0>;
1078 power-domain@RK3588_PD_USB {
1092 #power-domain-cells = <0>;
1094 power-domain@RK3588_PD_GMAC {
1099 #power-domain-cells = <0>;
1101 power-domain@RK3588_PD_PCIE {
1106 #power-domain-cells = <0>;
1108 power-domain@RK3588_PD_SDIO {
1113 #power-domain-cells = <0>;
1115 power-domain@RK3588_PD_AUDIO {
1119 #power-domain-cells = <0>;
1121 power-domain@RK3588_PD_SDMMC {
1124 #power-domain-cells = <0>;
1129 vpu121: video-codec@fdb50000 {
1130 compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu";
1133 interrupt-names = "vdpu";
1135 clock-names = "aclk", "hclk";
1137 power-domains = <&power RK3588_PD_VDPU>;
1141 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1144 clock-names = "aclk", "iface";
1146 power-domains = <&power RK3588_PD_VDPU>;
1147 #iommu-cells = <0>;
1151 compatible = "rockchip,rk3588-rga", "rockchip,rk3288-rga";
1155 clock-names = "aclk", "hclk", "sclk";
1157 reset-names = "core", "axi", "ahb";
1158 power-domains = <&power RK3588_PD_VDPU>;
1161 vepu121_0: video-codec@fdba0000 {
1162 compatible = "rockchip,rk3588-vepu121";
1166 clock-names = "aclk", "hclk";
1168 power-domains = <&power RK3588_PD_VDPU>;
1172 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1176 clock-names = "aclk", "iface";
1177 power-domains = <&power RK3588_PD_VDPU>;
1178 #iommu-cells = <0>;
1181 vepu121_1: video-codec@fdba4000 {
1182 compatible = "rockchip,rk3588-vepu121";
1186 clock-names = "aclk", "hclk";
1188 power-domains = <&power RK3588_PD_VDPU>;
1192 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1196 clock-names = "aclk", "iface";
1197 power-domains = <&power RK3588_PD_VDPU>;
1198 #iommu-cells = <0>;
1201 vepu121_2: video-codec@fdba8000 {
1202 compatible = "rockchip,rk3588-vepu121";
1206 clock-names = "aclk", "hclk";
1208 power-domains = <&power RK3588_PD_VDPU>;
1212 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1216 clock-names = "aclk", "iface";
1217 power-domains = <&power RK3588_PD_VDPU>;
1218 #iommu-cells = <0>;
1221 vepu121_3: video-codec@fdbac000 {
1222 compatible = "rockchip,rk3588-vepu121";
1226 clock-names = "aclk", "hclk";
1228 power-domains = <&power RK3588_PD_VDPU>;
1232 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1236 clock-names = "aclk", "iface";
1237 power-domains = <&power RK3588_PD_VDPU>;
1238 #iommu-cells = <0>;
1241 av1d: video-codec@fdc70000 {
1242 compatible = "rockchip,rk3588-av1-vpu";
1245 interrupt-names = "vdpu";
1246 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
1247 assigned-clock-rates = <400000000>, <400000000>;
1249 clock-names = "aclk", "hclk";
1250 power-domains = <&power RK3588_PD_AV1>;
1255 compatible = "rockchip,rk3588-vop";
1257 reg-names = "vop", "gamma-lut";
1266 clock-names = "aclk",
1274 power-domains = <&power RK3588_PD_VOP>;
1276 rockchip,vop-grf = <&vop_grf>;
1277 rockchip,vo1-grf = <&vo1_grf>;
1282 #address-cells = <1>;
1283 #size-cells = <0>;
1286 #address-cells = <1>;
1287 #size-cells = <0>;
1292 #address-cells = <1>;
1293 #size-cells = <0>;
1298 #address-cells = <1>;
1299 #size-cells = <0>;
1304 #address-cells = <1>;
1305 #size-cells = <0>;
1312 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1316 clock-names = "aclk", "iface";
1317 #iommu-cells = <0>;
1318 power-domains = <&power RK3588_PD_VOP>;
1323 compatible = "rockchip,rk3588-i2s-tdm";
1327 clock-names = "mclk_tx", "mclk_rx", "hclk";
1328 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
1329 assigned-clock-parents = <&cru PLL_AUPLL>;
1331 dma-names = "tx";
1332 power-domains = <&power RK3588_PD_VO0>;
1334 reset-names = "tx-m";
1335 #sound-dai-cells = <0>;
1340 compatible = "rockchip,rk3588-i2s-tdm";
1344 clock-names = "mclk_tx", "mclk_rx", "hclk";
1345 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
1346 assigned-clock-parents = <&cru PLL_AUPLL>;
1348 dma-names = "tx";
1349 power-domains = <&power RK3588_PD_VO1>;
1351 reset-names = "tx-m";
1352 #sound-dai-cells = <0>;
1357 compatible = "rockchip,rk3588-i2s-tdm";
1361 clock-names = "mclk_tx", "mclk_rx", "hclk";
1362 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
1363 assigned-clock-parents = <&cru PLL_AUPLL>;
1365 dma-names = "rx";
1366 power-domains = <&power RK3588_PD_VO1>;
1368 reset-names = "rx-m";
1369 #sound-dai-cells = <0>;
1374 compatible = "rockchip,rk3588-qos", "syscon";
1379 compatible = "rockchip,rk3588-qos", "syscon";
1384 compatible = "rockchip,rk3588-qos", "syscon";
1389 compatible = "rockchip,rk3588-qos", "syscon";
1394 compatible = "rockchip,rk3588-qos", "syscon";
1399 compatible = "rockchip,rk3588-qos", "syscon";
1404 compatible = "rockchip,rk3588-qos", "syscon";
1409 compatible = "rockchip,rk3588-qos", "syscon";
1414 compatible = "rockchip,rk3588-qos", "syscon";
1419 compatible = "rockchip,rk3588-qos", "syscon";
1424 compatible = "rockchip,rk3588-qos", "syscon";
1429 compatible = "rockchip,rk3588-qos", "syscon";
1434 compatible = "rockchip,rk3588-qos", "syscon";
1439 compatible = "rockchip,rk3588-qos", "syscon";
1444 compatible = "rockchip,rk3588-qos", "syscon";
1449 compatible = "rockchip,rk3588-qos", "syscon";
1454 compatible = "rockchip,rk3588-qos", "syscon";
1459 compatible = "rockchip,rk3588-qos", "syscon";
1464 compatible = "rockchip,rk3588-qos", "syscon";
1469 compatible = "rockchip,rk3588-qos", "syscon";
1474 compatible = "rockchip,rk3588-qos", "syscon";
1479 compatible = "rockchip,rk3588-qos", "syscon";
1484 compatible = "rockchip,rk3588-qos", "syscon";
1489 compatible = "rockchip,rk3588-qos", "syscon";
1494 compatible = "rockchip,rk3588-qos", "syscon";
1499 compatible = "rockchip,rk3588-qos", "syscon";
1504 compatible = "rockchip,rk3588-qos", "syscon";
1509 compatible = "rockchip,rk3588-qos", "syscon";
1514 compatible = "rockchip,rk3588-qos", "syscon";
1519 compatible = "rockchip,rk3588-qos", "syscon";
1524 compatible = "rockchip,rk3588-qos", "syscon";
1529 compatible = "rockchip,rk3588-qos", "syscon";
1534 compatible = "rockchip,rk3588-qos", "syscon";
1539 compatible = "rockchip,rk3588-qos", "syscon";
1544 compatible = "rockchip,rk3588-qos", "syscon";
1549 compatible = "rockchip,rk3588-qos", "syscon";
1554 compatible = "rockchip,rk3588-qos", "syscon";
1559 compatible = "rockchip,rk3588-qos", "syscon";
1564 compatible = "rockchip,rk3588-qos", "syscon";
1569 compatible = "rockchip,rk3588-qos", "syscon";
1574 compatible = "rockchip,rk3588-qos", "syscon";
1579 compatible = "rockchip,rk3588-qos", "syscon";
1584 compatible = "rockchip,rk3588-qos", "syscon";
1589 compatible = "rockchip,rk3588-qos", "syscon";
1594 compatible = "rockchip,rk3588-qos", "syscon";
1599 compatible = "rockchip,rk3588-qos", "syscon";
1604 compatible = "rockchip,rk3588-qos", "syscon";
1609 compatible = "rockchip,rk3588-qos", "syscon";
1615 compatible = "rockchip,rk3588-dfi";
1624 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1625 bus-range = <0x30 0x3f>;
1629 clock-names = "aclk_mst", "aclk_slv",
1638 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1639 #interrupt-cells = <1>;
1640 interrupt-map-mask = <0 0 0 7>;
1641 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
1645 linux,pci-domain = <3>;
1646 max-link-speed = <2>;
1647 msi-map = <0x3000 &its0 0x3000 0x1000>;
1648 num-lanes = <1>;
1650 phy-names = "pcie-phy";
1651 power-domains = <&power RK3588_PD_PCIE>;
1658 reg-names = "dbi", "apb", "config";
1660 reset-names = "pwr", "pipe";
1661 #address-cells = <3>;
1662 #size-cells = <2>;
1665 pcie2x1l1_intc: legacy-interrupt-controller {
1666 interrupt-controller;
1667 #address-cells = <0>;
1668 #interrupt-cells = <1>;
1669 interrupt-parent = <&gic>;
1675 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1676 bus-range = <0x40 0x4f>;
1680 clock-names = "aclk_mst", "aclk_slv",
1689 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1690 #interrupt-cells = <1>;
1691 interrupt-map-mask = <0 0 0 7>;
1692 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
1696 linux,pci-domain = <4>;
1697 max-link-speed = <2>;
1698 msi-map = <0x4000 &its0 0x4000 0x1000>;
1699 num-lanes = <1>;
1701 phy-names = "pcie-phy";
1702 power-domains = <&power RK3588_PD_PCIE>;
1709 reg-names = "dbi", "apb", "config";
1711 reset-names = "pwr", "pipe";
1712 #address-cells = <3>;
1713 #size-cells = <2>;
1716 pcie2x1l2_intc: legacy-interrupt-controller {
1717 interrupt-controller;
1718 #address-cells = <0>;
1719 #interrupt-cells = <1>;
1720 interrupt-parent = <&gic>;
1726 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
1730 interrupt-names = "macirq", "eth_wake_irq";
1734 clock-names = "stmmaceth", "clk_mac_ref",
1737 power-domains = <&power RK3588_PD_GMAC>;
1739 reset-names = "stmmaceth";
1741 rockchip,php-grf = <&php_grf>;
1742 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1743 snps,mixed-burst;
1744 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1745 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1750 compatible = "snps,dwmac-mdio";
1751 #address-cells = <0x1>;
1752 #size-cells = <0x0>;
1755 gmac1_stmmac_axi_setup: stmmac-axi-config {
1761 gmac1_mtl_rx_setup: rx-queues-config {
1762 snps,rx-queues-to-use = <2>;
1767 gmac1_mtl_tx_setup: tx-queues-config {
1768 snps,tx-queues-to-use = <2>;
1775 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1781 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1782 ports-implemented = <0x1>;
1783 #address-cells = <1>;
1784 #size-cells = <0>;
1787 sata-port@0 {
1789 hba-port-cap = <HBA_PORT_FBSCP>;
1791 phy-names = "sata-phy";
1792 snps,rx-ts-max = <32>;
1793 snps,tx-ts-max = <32>;
1798 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1804 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1805 ports-implemented = <0x1>;
1806 #address-cells = <1>;
1807 #size-cells = <0>;
1810 sata-port@0 {
1812 hba-port-cap = <HBA_PORT_FBSCP>;
1814 phy-names = "sata-phy";
1815 snps,rx-ts-max = <32>;
1816 snps,tx-ts-max = <32>;
1825 clock-names = "clk_sfc", "hclk_sfc";
1826 #address-cells = <1>;
1827 #size-cells = <0>;
1832 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1837 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1838 fifo-depth = <0x100>;
1839 max-frequency = <200000000>;
1840 pinctrl-names = "default";
1841 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1842 power-domains = <&power RK3588_PD_SDMMC>;
1847 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1852 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1853 fifo-depth = <0x100>;
1854 max-frequency = <200000000>;
1855 pinctrl-names = "default";
1856 pinctrl-0 = <&sdiom1_pins>;
1857 power-domains = <&power RK3588_PD_SDIO>;
1862 compatible = "rockchip,rk3588-dwcmshc";
1865 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
1866 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1870 clock-names = "core", "bus", "axi", "block", "timer";
1871 max-frequency = <200000000>;
1872 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1874 pinctrl-names = "default";
1878 reset-names = "core", "bus", "axi", "block", "timer";
1883 compatible = "rockchip,rk3588-i2s-tdm";
1887 clock-names = "mclk_tx", "mclk_rx", "hclk";
1888 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1889 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
1891 dma-names = "tx", "rx";
1892 power-domains = <&power RK3588_PD_AUDIO>;
1894 reset-names = "tx-m", "rx-m";
1895 rockchip,trcm-sync-tx-only;
1896 pinctrl-names = "default";
1897 pinctrl-0 = <&i2s0_lrck
1907 #sound-dai-cells = <0>;
1912 compatible = "rockchip,rk3588-i2s-tdm";
1916 clock-names = "mclk_tx", "mclk_rx", "hclk";
1918 dma-names = "tx", "rx";
1920 reset-names = "tx-m", "rx-m";
1921 rockchip,trcm-sync-tx-only;
1922 pinctrl-names = "default";
1923 pinctrl-0 = <&i2s1m0_lrck
1933 #sound-dai-cells = <0>;
1938 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1942 clock-names = "i2s_clk", "i2s_hclk";
1943 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1944 assigned-clock-parents = <&cru PLL_AUPLL>;
1946 dma-names = "tx", "rx";
1947 power-domains = <&power RK3588_PD_AUDIO>;
1948 pinctrl-names = "default";
1949 pinctrl-0 = <&i2s2m1_lrck
1953 #sound-dai-cells = <0>;
1958 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1962 clock-names = "i2s_clk", "i2s_hclk";
1963 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
1964 assigned-clock-parents = <&cru PLL_AUPLL>;
1966 dma-names = "tx", "rx";
1967 power-domains = <&power RK3588_PD_AUDIO>;
1968 pinctrl-names = "default";
1969 pinctrl-0 = <&i2s3_lrck
1973 #sound-dai-cells = <0>;
1977 gic: interrupt-controller@fe600000 {
1978 compatible = "arm,gic-v3";
1982 interrupt-controller;
1983 mbi-alias = <0x0 0xfe610000>;
1984 mbi-ranges = <424 56>;
1985 msi-controller;
1987 #address-cells = <2>;
1988 #interrupt-cells = <4>;
1989 #size-cells = <2>;
1991 its0: msi-controller@fe640000 {
1992 compatible = "arm,gic-v3-its";
1994 msi-controller;
1995 #msi-cells = <1>;
1998 its1: msi-controller@fe660000 {
1999 compatible = "arm,gic-v3-its";
2001 msi-controller;
2002 #msi-cells = <1>;
2005 ppi-partitions {
2006 ppi_partition0: interrupt-partition-0 {
2010 ppi_partition1: interrupt-partition-1 {
2016 dmac0: dma-controller@fea10000 {
2021 arm,pl330-periph-burst;
2023 clock-names = "apb_pclk";
2024 #dma-cells = <1>;
2027 dmac1: dma-controller@fea30000 {
2032 arm,pl330-periph-burst;
2034 clock-names = "apb_pclk";
2035 #dma-cells = <1>;
2039 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2042 clock-names = "i2c", "pclk";
2044 pinctrl-0 = <&i2c1m0_xfer>;
2045 pinctrl-names = "default";
2046 #address-cells = <1>;
2047 #size-cells = <0>;
2052 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2055 clock-names = "i2c", "pclk";
2057 pinctrl-0 = <&i2c2m0_xfer>;
2058 pinctrl-names = "default";
2059 #address-cells = <1>;
2060 #size-cells = <0>;
2065 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2068 clock-names = "i2c", "pclk";
2070 pinctrl-0 = <&i2c3m0_xfer>;
2071 pinctrl-names = "default";
2072 #address-cells = <1>;
2073 #size-cells = <0>;
2078 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2081 clock-names = "i2c", "pclk";
2083 pinctrl-0 = <&i2c4m0_xfer>;
2084 pinctrl-names = "default";
2085 #address-cells = <1>;
2086 #size-cells = <0>;
2091 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2094 clock-names = "i2c", "pclk";
2096 pinctrl-0 = <&i2c5m0_xfer>;
2097 pinctrl-names = "default";
2098 #address-cells = <1>;
2099 #size-cells = <0>;
2104 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
2108 clock-names = "pclk", "timer";
2112 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
2115 clock-names = "tclk", "pclk";
2120 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2124 clock-names = "spiclk", "apb_pclk";
2126 dma-names = "tx", "rx";
2127 num-cs = <2>;
2128 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
2129 pinctrl-names = "default";
2130 #address-cells = <1>;
2131 #size-cells = <0>;
2136 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2140 clock-names = "spiclk", "apb_pclk";
2142 dma-names = "tx", "rx";
2143 num-cs = <2>;
2144 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
2145 pinctrl-names = "default";
2146 #address-cells = <1>;
2147 #size-cells = <0>;
2152 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2156 clock-names = "spiclk", "apb_pclk";
2158 dma-names = "tx", "rx";
2159 num-cs = <2>;
2160 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
2161 pinctrl-names = "default";
2162 #address-cells = <1>;
2163 #size-cells = <0>;
2168 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2172 clock-names = "spiclk", "apb_pclk";
2174 dma-names = "tx", "rx";
2175 num-cs = <2>;
2176 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
2177 pinctrl-names = "default";
2178 #address-cells = <1>;
2179 #size-cells = <0>;
2184 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2188 clock-names = "baudclk", "apb_pclk";
2190 dma-names = "tx", "rx";
2191 pinctrl-0 = <&uart1m1_xfer>;
2192 pinctrl-names = "default";
2193 reg-io-width = <4>;
2194 reg-shift = <2>;
2199 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2203 clock-names = "baudclk", "apb_pclk";
2205 dma-names = "tx", "rx";
2206 pinctrl-0 = <&uart2m1_xfer>;
2207 pinctrl-names = "default";
2208 reg-io-width = <4>;
2209 reg-shift = <2>;
2214 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2218 clock-names = "baudclk", "apb_pclk";
2220 dma-names = "tx", "rx";
2221 pinctrl-0 = <&uart3m1_xfer>;
2222 pinctrl-names = "default";
2223 reg-io-width = <4>;
2224 reg-shift = <2>;
2229 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2233 clock-names = "baudclk", "apb_pclk";
2235 dma-names = "tx", "rx";
2236 pinctrl-0 = <&uart4m1_xfer>;
2237 pinctrl-names = "default";
2238 reg-io-width = <4>;
2239 reg-shift = <2>;
2244 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2248 clock-names = "baudclk", "apb_pclk";
2250 dma-names = "tx", "rx";
2251 pinctrl-0 = <&uart5m1_xfer>;
2252 pinctrl-names = "default";
2253 reg-io-width = <4>;
2254 reg-shift = <2>;
2259 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2263 clock-names = "baudclk", "apb_pclk";
2265 dma-names = "tx", "rx";
2266 pinctrl-0 = <&uart6m1_xfer>;
2267 pinctrl-names = "default";
2268 reg-io-width = <4>;
2269 reg-shift = <2>;
2274 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2278 clock-names = "baudclk", "apb_pclk";
2280 dma-names = "tx", "rx";
2281 pinctrl-0 = <&uart7m1_xfer>;
2282 pinctrl-names = "default";
2283 reg-io-width = <4>;
2284 reg-shift = <2>;
2289 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2293 clock-names = "baudclk", "apb_pclk";
2295 dma-names = "tx", "rx";
2296 pinctrl-0 = <&uart8m1_xfer>;
2297 pinctrl-names = "default";
2298 reg-io-width = <4>;
2299 reg-shift = <2>;
2304 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2308 clock-names = "baudclk", "apb_pclk";
2310 dma-names = "tx", "rx";
2311 pinctrl-0 = <&uart9m1_xfer>;
2312 pinctrl-names = "default";
2313 reg-io-width = <4>;
2314 reg-shift = <2>;
2319 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2322 clock-names = "pwm", "pclk";
2323 pinctrl-0 = <&pwm4m0_pins>;
2324 pinctrl-names = "default";
2325 #pwm-cells = <3>;
2330 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2333 clock-names = "pwm", "pclk";
2334 pinctrl-0 = <&pwm5m0_pins>;
2335 pinctrl-names = "default";
2336 #pwm-cells = <3>;
2341 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2344 clock-names = "pwm", "pclk";
2345 pinctrl-0 = <&pwm6m0_pins>;
2346 pinctrl-names = "default";
2347 #pwm-cells = <3>;
2352 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2355 clock-names = "pwm", "pclk";
2356 pinctrl-0 = <&pwm7m0_pins>;
2357 pinctrl-names = "default";
2358 #pwm-cells = <3>;
2363 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2366 clock-names = "pwm", "pclk";
2367 pinctrl-0 = <&pwm8m0_pins>;
2368 pinctrl-names = "default";
2369 #pwm-cells = <3>;
2374 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2377 clock-names = "pwm", "pclk";
2378 pinctrl-0 = <&pwm9m0_pins>;
2379 pinctrl-names = "default";
2380 #pwm-cells = <3>;
2385 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2388 clock-names = "pwm", "pclk";
2389 pinctrl-0 = <&pwm10m0_pins>;
2390 pinctrl-names = "default";
2391 #pwm-cells = <3>;
2396 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2399 clock-names = "pwm", "pclk";
2400 pinctrl-0 = <&pwm11m0_pins>;
2401 pinctrl-names = "default";
2402 #pwm-cells = <3>;
2407 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2410 clock-names = "pwm", "pclk";
2411 pinctrl-0 = <&pwm12m0_pins>;
2412 pinctrl-names = "default";
2413 #pwm-cells = <3>;
2418 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2421 clock-names = "pwm", "pclk";
2422 pinctrl-0 = <&pwm13m0_pins>;
2423 pinctrl-names = "default";
2424 #pwm-cells = <3>;
2429 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2432 clock-names = "pwm", "pclk";
2433 pinctrl-0 = <&pwm14m0_pins>;
2434 pinctrl-names = "default";
2435 #pwm-cells = <3>;
2440 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2443 clock-names = "pwm", "pclk";
2444 pinctrl-0 = <&pwm15m0_pins>;
2445 pinctrl-names = "default";
2446 #pwm-cells = <3>;
2450 thermal_zones: thermal-zones {
2452 package_thermal: package-thermal {
2453 polling-delay-passive = <0>;
2454 polling-delay = <0>;
2455 thermal-sensors = <&tsadc 0>;
2458 package_crit: package-crit {
2467 bigcore0_thermal: bigcore0-thermal {
2468 polling-delay-passive = <100>;
2469 polling-delay = <0>;
2470 thermal-sensors = <&tsadc 1>;
2473 bigcore0_alert: bigcore0-alert {
2479 bigcore0_crit: bigcore0-crit {
2486 cooling-maps {
2489 cooling-device =
2497 bigcore2_thermal: bigcore2-thermal {
2498 polling-delay-passive = <100>;
2499 polling-delay = <0>;
2500 thermal-sensors = <&tsadc 2>;
2503 bigcore2_alert: bigcore2-alert {
2509 bigcore2_crit: bigcore2-crit {
2516 cooling-maps {
2519 cooling-device =
2527 little_core_thermal: littlecore-thermal {
2528 polling-delay-passive = <100>;
2529 polling-delay = <0>;
2530 thermal-sensors = <&tsadc 3>;
2533 littlecore_alert: littlecore-alert {
2539 littlecore_crit: littlecore-crit {
2546 cooling-maps {
2549 cooling-device =
2559 center_thermal: center-thermal {
2560 polling-delay-passive = <0>;
2561 polling-delay = <0>;
2562 thermal-sensors = <&tsadc 4>;
2565 center_crit: center-crit {
2573 gpu_thermal: gpu-thermal {
2574 polling-delay-passive = <100>;
2575 polling-delay = <0>;
2576 thermal-sensors = <&tsadc 5>;
2579 gpu_alert: gpu-alert {
2585 gpu_crit: gpu-crit {
2592 cooling-maps {
2595 cooling-device =
2601 npu_thermal: npu-thermal {
2602 polling-delay-passive = <0>;
2603 polling-delay = <0>;
2604 thermal-sensors = <&tsadc 6>;
2607 npu_crit: npu-crit {
2617 compatible = "rockchip,rk3588-tsadc";
2621 clock-names = "tsadc", "apb_pclk";
2622 assigned-clocks = <&cru CLK_TSADC>;
2623 assigned-clock-rates = <2000000>;
2625 reset-names = "tsadc-apb", "tsadc";
2626 rockchip,hw-tshut-temp = <120000>;
2627 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2628 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2629 pinctrl-0 = <&tsadc_gpio_func>;
2630 pinctrl-1 = <&tsadc_shut>;
2631 pinctrl-names = "gpio", "otpout";
2632 #thermal-sensor-cells = <1>;
2637 compatible = "rockchip,rk3588-saradc";
2640 #io-channel-cells = <1>;
2642 clock-names = "saradc", "apb_pclk";
2644 reset-names = "saradc-apb";
2649 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2652 clock-names = "i2c", "pclk";
2654 pinctrl-0 = <&i2c6m0_xfer>;
2655 pinctrl-names = "default";
2656 #address-cells = <1>;
2657 #size-cells = <0>;
2662 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2665 clock-names = "i2c", "pclk";
2667 pinctrl-0 = <&i2c7m0_xfer>;
2668 pinctrl-names = "default";
2669 #address-cells = <1>;
2670 #size-cells = <0>;
2675 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2678 clock-names = "i2c", "pclk";
2680 pinctrl-0 = <&i2c8m0_xfer>;
2681 pinctrl-names = "default";
2682 #address-cells = <1>;
2683 #size-cells = <0>;
2688 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2692 clock-names = "spiclk", "apb_pclk";
2694 dma-names = "tx", "rx";
2695 num-cs = <2>;
2696 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
2697 pinctrl-names = "default";
2698 #address-cells = <1>;
2699 #size-cells = <0>;
2703 otp: efuse@fecc0000 {
2704 compatible = "rockchip,rk3588-otp";
2708 clock-names = "otp", "apb_pclk", "phy", "arb";
2711 reset-names = "otp", "apb", "arb";
2712 #address-cells = <1>;
2713 #size-cells = <1>;
2715 cpu_code: cpu-code@2 {
2723 cpub0_leakage: cpu-leakage@17 {
2727 cpub1_leakage: cpu-leakage@18 {
2731 cpul_leakage: cpu-leakage@19 {
2735 log_leakage: log-leakage@1a {
2739 gpu_leakage: gpu-leakage@1b {
2743 otp_cpu_version: cpu-version@1c {
2748 npu_leakage: npu-leakage@28 {
2752 codec_leakage: codec-leakage@29 {
2757 dmac2: dma-controller@fed10000 {
2762 arm,pl330-periph-burst;
2764 clock-names = "apb_pclk";
2765 #dma-cells = <1>;
2769 compatible = "rockchip,rk3588-hdptx-phy";
2772 clock-names = "ref", "apb";
2773 #phy-cells = <0>;
2778 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
2785 compatible = "rockchip,rk3588-usbdp-phy";
2787 #phy-cells = <1>;
2792 clock-names = "refclk", "immortal", "pclk", "utmi";
2798 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
2799 rockchip,u2phy-grf = <&usb2phy0_grf>;
2800 rockchip,usb-grf = <&usb_grf>;
2801 rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
2802 rockchip,vo-grf = <&vo0_grf>;
2807 compatible = "rockchip,rk3588-naneng-combphy";
2811 clock-names = "ref", "apb", "pipe";
2812 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
2813 assigned-clock-rates = <100000000>;
2814 #phy-cells = <1>;
2816 reset-names = "phy", "apb";
2817 rockchip,pipe-grf = <&php_grf>;
2818 rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
2823 compatible = "rockchip,rk3588-naneng-combphy";
2827 clock-names = "ref", "apb", "pipe";
2828 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
2829 assigned-clock-rates = <100000000>;
2830 #phy-cells = <1>;
2832 reset-names = "phy", "apb";
2833 rockchip,pipe-grf = <&php_grf>;
2834 rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
2839 compatible = "mmio-sram";
2842 #address-cells = <1>;
2843 #size-cells = <1>;
2847 compatible = "rockchip,rk3588-pinctrl";
2850 #address-cells = <2>;
2851 #size-cells = <2>;
2854 compatible = "rockchip,gpio-bank";
2858 gpio-controller;
2859 gpio-ranges = <&pinctrl 0 0 32>;
2860 interrupt-controller;
2861 #gpio-cells = <2>;
2862 #interrupt-cells = <2>;
2866 compatible = "rockchip,gpio-bank";
2870 gpio-controller;
2871 gpio-ranges = <&pinctrl 0 32 32>;
2872 interrupt-controller;
2873 #gpio-cells = <2>;
2874 #interrupt-cells = <2>;
2878 compatible = "rockchip,gpio-bank";
2882 gpio-controller;
2883 gpio-ranges = <&pinctrl 0 64 32>;
2884 interrupt-controller;
2885 #gpio-cells = <2>;
2886 #interrupt-cells = <2>;
2890 compatible = "rockchip,gpio-bank";
2894 gpio-controller;
2895 gpio-ranges = <&pinctrl 0 96 32>;
2896 interrupt-controller;
2897 #gpio-cells = <2>;
2898 #interrupt-cells = <2>;
2902 compatible = "rockchip,gpio-bank";
2906 gpio-controller;
2907 gpio-ranges = <&pinctrl 0 128 32>;
2908 interrupt-controller;
2909 #gpio-cells = <2>;
2910 #interrupt-cells = <2>;
2915 #include "rk3588-base-pinctrl.dtsi"