Lines Matching +full:hw +full:- +full:tshut +full:- +full:temp
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/power/rk3588-power.h>
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/ata/ahci.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
55 #address-cells = <1>;
56 #size-cells = <0>;
58 cpu-map {
93 compatible = "arm,cortex-a55";
95 enable-method = "psci";
96 capacity-dmips-mhz = <530>;
98 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
99 assigned-clock-rates = <816000000>;
100 cpu-idle-states = <&CPU_SLEEP>;
101 i-cache-size = <32768>;
102 i-cache-line-size = <64>;
103 i-cache-sets = <128>;
104 d-cache-size = <32768>;
105 d-cache-line-size = <64>;
106 d-cache-sets = <128>;
107 next-level-cache = <&l2_cache_l0>;
108 dynamic-power-coefficient = <228>;
109 #cooling-cells = <2>;
114 compatible = "arm,cortex-a55";
116 enable-method = "psci";
117 capacity-dmips-mhz = <530>;
119 cpu-idle-states = <&CPU_SLEEP>;
120 i-cache-size = <32768>;
121 i-cache-line-size = <64>;
122 i-cache-sets = <128>;
123 d-cache-size = <32768>;
124 d-cache-line-size = <64>;
125 d-cache-sets = <128>;
126 next-level-cache = <&l2_cache_l1>;
127 dynamic-power-coefficient = <228>;
128 #cooling-cells = <2>;
133 compatible = "arm,cortex-a55";
135 enable-method = "psci";
136 capacity-dmips-mhz = <530>;
138 cpu-idle-states = <&CPU_SLEEP>;
139 i-cache-size = <32768>;
140 i-cache-line-size = <64>;
141 i-cache-sets = <128>;
142 d-cache-size = <32768>;
143 d-cache-line-size = <64>;
144 d-cache-sets = <128>;
145 next-level-cache = <&l2_cache_l2>;
146 dynamic-power-coefficient = <228>;
147 #cooling-cells = <2>;
152 compatible = "arm,cortex-a55";
154 enable-method = "psci";
155 capacity-dmips-mhz = <530>;
157 cpu-idle-states = <&CPU_SLEEP>;
158 i-cache-size = <32768>;
159 i-cache-line-size = <64>;
160 i-cache-sets = <128>;
161 d-cache-size = <32768>;
162 d-cache-line-size = <64>;
163 d-cache-sets = <128>;
164 next-level-cache = <&l2_cache_l3>;
165 dynamic-power-coefficient = <228>;
166 #cooling-cells = <2>;
171 compatible = "arm,cortex-a76";
173 enable-method = "psci";
174 capacity-dmips-mhz = <1024>;
176 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
177 assigned-clock-rates = <816000000>;
178 cpu-idle-states = <&CPU_SLEEP>;
179 i-cache-size = <65536>;
180 i-cache-line-size = <64>;
181 i-cache-sets = <256>;
182 d-cache-size = <65536>;
183 d-cache-line-size = <64>;
184 d-cache-sets = <256>;
185 next-level-cache = <&l2_cache_b0>;
186 dynamic-power-coefficient = <416>;
187 #cooling-cells = <2>;
192 compatible = "arm,cortex-a76";
194 enable-method = "psci";
195 capacity-dmips-mhz = <1024>;
197 cpu-idle-states = <&CPU_SLEEP>;
198 i-cache-size = <65536>;
199 i-cache-line-size = <64>;
200 i-cache-sets = <256>;
201 d-cache-size = <65536>;
202 d-cache-line-size = <64>;
203 d-cache-sets = <256>;
204 next-level-cache = <&l2_cache_b1>;
205 dynamic-power-coefficient = <416>;
206 #cooling-cells = <2>;
211 compatible = "arm,cortex-a76";
213 enable-method = "psci";
214 capacity-dmips-mhz = <1024>;
216 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
217 assigned-clock-rates = <816000000>;
218 cpu-idle-states = <&CPU_SLEEP>;
219 i-cache-size = <65536>;
220 i-cache-line-size = <64>;
221 i-cache-sets = <256>;
222 d-cache-size = <65536>;
223 d-cache-line-size = <64>;
224 d-cache-sets = <256>;
225 next-level-cache = <&l2_cache_b2>;
226 dynamic-power-coefficient = <416>;
227 #cooling-cells = <2>;
232 compatible = "arm,cortex-a76";
234 enable-method = "psci";
235 capacity-dmips-mhz = <1024>;
237 cpu-idle-states = <&CPU_SLEEP>;
238 i-cache-size = <65536>;
239 i-cache-line-size = <64>;
240 i-cache-sets = <256>;
241 d-cache-size = <65536>;
242 d-cache-line-size = <64>;
243 d-cache-sets = <256>;
244 next-level-cache = <&l2_cache_b3>;
245 dynamic-power-coefficient = <416>;
246 #cooling-cells = <2>;
249 idle-states {
250 entry-method = "psci";
251 CPU_SLEEP: cpu-sleep {
252 compatible = "arm,idle-state";
253 local-timer-stop;
254 arm,psci-suspend-param = <0x0010000>;
255 entry-latency-us = <100>;
256 exit-latency-us = <120>;
257 min-residency-us = <1000>;
261 l2_cache_l0: l2-cache-l0 {
263 cache-size = <131072>;
264 cache-line-size = <64>;
265 cache-sets = <512>;
266 cache-level = <2>;
267 cache-unified;
268 next-level-cache = <&l3_cache>;
271 l2_cache_l1: l2-cache-l1 {
273 cache-size = <131072>;
274 cache-line-size = <64>;
275 cache-sets = <512>;
276 cache-level = <2>;
277 cache-unified;
278 next-level-cache = <&l3_cache>;
281 l2_cache_l2: l2-cache-l2 {
283 cache-size = <131072>;
284 cache-line-size = <64>;
285 cache-sets = <512>;
286 cache-level = <2>;
287 cache-unified;
288 next-level-cache = <&l3_cache>;
291 l2_cache_l3: l2-cache-l3 {
293 cache-size = <131072>;
294 cache-line-size = <64>;
295 cache-sets = <512>;
296 cache-level = <2>;
297 cache-unified;
298 next-level-cache = <&l3_cache>;
301 l2_cache_b0: l2-cache-b0 {
303 cache-size = <524288>;
304 cache-line-size = <64>;
305 cache-sets = <1024>;
306 cache-level = <2>;
307 cache-unified;
308 next-level-cache = <&l3_cache>;
311 l2_cache_b1: l2-cache-b1 {
313 cache-size = <524288>;
314 cache-line-size = <64>;
315 cache-sets = <1024>;
316 cache-level = <2>;
317 cache-unified;
318 next-level-cache = <&l3_cache>;
321 l2_cache_b2: l2-cache-b2 {
323 cache-size = <524288>;
324 cache-line-size = <64>;
325 cache-sets = <1024>;
326 cache-level = <2>;
327 cache-unified;
328 next-level-cache = <&l3_cache>;
331 l2_cache_b3: l2-cache-b3 {
333 cache-size = <524288>;
334 cache-line-size = <64>;
335 cache-sets = <1024>;
336 cache-level = <2>;
337 cache-unified;
338 next-level-cache = <&l3_cache>;
346 l3_cache: l3-cache {
348 cache-size = <3145728>;
349 cache-line-size = <64>;
350 cache-sets = <4096>;
351 cache-level = <3>;
352 cache-unified;
355 display_subsystem: display-subsystem {
356 compatible = "rockchip,display-subsystem";
362 compatible = "arm,scmi-smc";
363 arm,smc-id = <0x82000010>;
365 #address-cells = <1>;
366 #size-cells = <0>;
370 #clock-cells = <1>;
375 #reset-cells = <1>;
380 hdmi0_sound: hdmi0-sound {
381 compatible = "simple-audio-card";
382 simple-audio-card,format = "i2s";
383 simple-audio-card,mclk-fs = <128>;
384 simple-audio-card,name = "hdmi0";
387 simple-audio-card,codec {
388 sound-dai = <&hdmi0>;
391 simple-audio-card,cpu {
392 sound-dai = <&i2s5_8ch>;
396 pmu-a55 {
397 compatible = "arm,cortex-a55-pmu";
401 pmu-a76 {
402 compatible = "arm,cortex-a76-pmu";
407 compatible = "arm,psci-1.0";
411 spll: clock-0 {
412 compatible = "fixed-clock";
413 clock-frequency = <702000000>;
414 clock-output-names = "spll";
415 #clock-cells = <0>;
419 compatible = "arm,armv8-timer";
425 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
428 xin24m: clock-1 {
429 compatible = "fixed-clock";
430 clock-frequency = <24000000>;
431 clock-output-names = "xin24m";
432 #clock-cells = <0>;
435 xin32k: clock-2 {
436 compatible = "fixed-clock";
437 clock-frequency = <32768>;
438 clock-output-names = "xin32k";
439 #clock-cells = <0>;
443 compatible = "mmio-sram";
446 #address-cells = <1>;
447 #size-cells = <1>;
450 compatible = "arm,scmi-shmem";
456 compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
458 #cooling-cells = <2>;
459 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
460 assigned-clock-rates = <200000000>;
463 clock-names = "core", "coregroup", "stacks";
464 dynamic-power-coefficient = <2982>;
468 interrupt-names = "job", "mmu", "gpu";
469 power-domains = <&power RK3588_PD_GPU>;
474 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
479 clock-names = "ref_clk", "suspend_clk", "bus_clk";
482 phy-names = "usb2-phy", "usb3-phy";
484 power-domains = <&power RK3588_PD_USB>;
487 snps,dis-u1-entry-quirk;
488 snps,dis-u2-entry-quirk;
489 snps,dis-u2-freeclk-exists-quirk;
490 snps,dis-del-phy-power-chg-quirk;
491 snps,dis-tx-ipgap-linecheck-quirk;
496 compatible = "rockchip,rk3588-ehci", "generic-ehci";
501 phy-names = "usb";
502 power-domains = <&power RK3588_PD_USB>;
507 compatible = "rockchip,rk3588-ohci", "generic-ohci";
512 phy-names = "usb";
513 power-domains = <&power RK3588_PD_USB>;
518 compatible = "rockchip,rk3588-ehci", "generic-ehci";
523 phy-names = "usb";
524 power-domains = <&power RK3588_PD_USB>;
529 compatible = "rockchip,rk3588-ohci", "generic-ohci";
534 phy-names = "usb";
535 power-domains = <&power RK3588_PD_USB>;
540 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
546 clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
549 phy-names = "usb3-phy";
553 snps,dis-u2-freeclk-exists-quirk;
554 snps,dis-del-phy-power-chg-quirk;
555 snps,dis-tx-ipgap-linecheck-quirk;
561 compatible = "arm,smmu-v3";
567 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
568 #iommu-cells = <1>;
572 compatible = "arm,smmu-v3";
578 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
579 #iommu-cells = <1>;
584 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
589 compatible = "rockchip,rk3588-sys-grf", "syscon";
594 compatible = "rockchip,rk3588-vop-grf", "syscon";
599 compatible = "rockchip,rk3588-vo0-grf", "syscon";
605 compatible = "rockchip,rk3588-vo1-grf", "syscon";
611 compatible = "rockchip,rk3588-usb-grf", "syscon";
616 compatible = "rockchip,rk3588-php-grf", "syscon";
621 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
626 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
631 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
636 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
638 #address-cells = <1>;
639 #size-cells = <1>;
642 compatible = "rockchip,rk3588-usb2phy";
644 #clock-cells = <0>;
646 clock-names = "phyclk";
647 clock-output-names = "usb480m_phy0";
650 reset-names = "phy", "apb";
653 u2phy0_otg: otg-port {
654 #phy-cells = <0>;
661 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
663 #address-cells = <1>;
664 #size-cells = <1>;
667 compatible = "rockchip,rk3588-usb2phy";
669 #clock-cells = <0>;
671 clock-names = "phyclk";
672 clock-output-names = "usb480m_phy2";
675 reset-names = "phy", "apb";
678 u2phy2_host: host-port {
679 #phy-cells = <0>;
686 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
688 #address-cells = <1>;
689 #size-cells = <1>;
692 compatible = "rockchip,rk3588-usb2phy";
694 #clock-cells = <0>;
696 clock-names = "phyclk";
697 clock-output-names = "usb480m_phy3";
700 reset-names = "phy", "apb";
703 u2phy3_host: host-port {
704 #phy-cells = <0>;
711 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
716 compatible = "rockchip,rk3588-ioc", "syscon";
721 compatible = "mmio-sram";
724 #address-cells = <1>;
725 #size-cells = <1>;
728 cru: clock-controller@fd7c0000 {
729 compatible = "rockchip,rk3588-cru";
731 assigned-clocks =
741 assigned-clock-rates =
752 #clock-cells = <1>;
753 #reset-cells = <1>;
757 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
761 clock-names = "i2c", "pclk";
762 pinctrl-0 = <&i2c0m0_xfer>;
763 pinctrl-names = "default";
764 #address-cells = <1>;
765 #size-cells = <0>;
770 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
774 clock-names = "baudclk", "apb_pclk";
776 dma-names = "tx", "rx";
777 pinctrl-0 = <&uart0m1_xfer>;
778 pinctrl-names = "default";
779 reg-shift = <2>;
780 reg-io-width = <4>;
785 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
788 clock-names = "pwm", "pclk";
789 pinctrl-0 = <&pwm0m0_pins>;
790 pinctrl-names = "default";
791 #pwm-cells = <3>;
796 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
799 clock-names = "pwm", "pclk";
800 pinctrl-0 = <&pwm1m0_pins>;
801 pinctrl-names = "default";
802 #pwm-cells = <3>;
807 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
810 clock-names = "pwm", "pclk";
811 pinctrl-0 = <&pwm2m0_pins>;
812 pinctrl-names = "default";
813 #pwm-cells = <3>;
818 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
821 clock-names = "pwm", "pclk";
822 pinctrl-0 = <&pwm3m0_pins>;
823 pinctrl-names = "default";
824 #pwm-cells = <3>;
828 pmu: power-management@fd8d8000 {
829 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
832 power: power-controller {
833 compatible = "rockchip,rk3588-power-controller";
834 #address-cells = <1>;
835 #power-domain-cells = <1>;
836 #size-cells = <0>;
840 power-domain@RK3588_PD_NPU {
842 #power-domain-cells = <0>;
843 #address-cells = <1>;
844 #size-cells = <0>;
846 power-domain@RK3588_PD_NPUTOP {
855 #power-domain-cells = <0>;
856 #address-cells = <1>;
857 #size-cells = <0>;
859 power-domain@RK3588_PD_NPU1 {
865 #power-domain-cells = <0>;
867 power-domain@RK3588_PD_NPU2 {
873 #power-domain-cells = <0>;
878 pd_gpu: power-domain@RK3588_PD_GPU {
887 #power-domain-cells = <0>;
890 power-domain@RK3588_PD_VCODEC {
892 #address-cells = <1>;
893 #size-cells = <0>;
894 #power-domain-cells = <0>;
896 power-domain@RK3588_PD_RKVDEC0 {
904 #power-domain-cells = <0>;
906 power-domain@RK3588_PD_RKVDEC1 {
913 #power-domain-cells = <0>;
915 power-domain@RK3588_PD_VENC0 {
922 #address-cells = <1>;
923 #size-cells = <0>;
924 #power-domain-cells = <0>;
926 power-domain@RK3588_PD_VENC1 {
935 #power-domain-cells = <0>;
940 power-domain@RK3588_PD_VDPU {
968 #address-cells = <1>;
969 #size-cells = <0>;
970 #power-domain-cells = <0>;
973 power-domain@RK3588_PD_AV1 {
979 #power-domain-cells = <0>;
981 power-domain@RK3588_PD_RKVDEC0 {
988 #power-domain-cells = <0>;
990 power-domain@RK3588_PD_RKVDEC1 {
996 #power-domain-cells = <0>;
998 power-domain@RK3588_PD_RGA30 {
1003 #power-domain-cells = <0>;
1006 power-domain@RK3588_PD_VOP {
1013 #address-cells = <1>;
1014 #size-cells = <0>;
1015 #power-domain-cells = <0>;
1017 power-domain@RK3588_PD_VO0 {
1027 #power-domain-cells = <0>;
1030 power-domain@RK3588_PD_VO1 {
1041 #power-domain-cells = <0>;
1043 power-domain@RK3588_PD_VI {
1055 #address-cells = <1>;
1056 #size-cells = <0>;
1057 #power-domain-cells = <0>;
1059 power-domain@RK3588_PD_ISP1 {
1067 #power-domain-cells = <0>;
1069 power-domain@RK3588_PD_FEC {
1078 #power-domain-cells = <0>;
1081 power-domain@RK3588_PD_RGA31 {
1086 #power-domain-cells = <0>;
1088 power-domain@RK3588_PD_USB {
1102 #power-domain-cells = <0>;
1104 power-domain@RK3588_PD_GMAC {
1109 #power-domain-cells = <0>;
1111 power-domain@RK3588_PD_PCIE {
1116 #power-domain-cells = <0>;
1118 power-domain@RK3588_PD_SDIO {
1123 #power-domain-cells = <0>;
1125 power-domain@RK3588_PD_AUDIO {
1129 #power-domain-cells = <0>;
1131 power-domain@RK3588_PD_SDMMC {
1134 #power-domain-cells = <0>;
1139 vpu121: video-codec@fdb50000 {
1140 compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu";
1143 interrupt-names = "vdpu";
1145 clock-names = "aclk", "hclk";
1147 power-domains = <&power RK3588_PD_VDPU>;
1151 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1154 clock-names = "aclk", "iface";
1156 power-domains = <&power RK3588_PD_VDPU>;
1157 #iommu-cells = <0>;
1161 compatible = "rockchip,rk3588-rga", "rockchip,rk3288-rga";
1165 clock-names = "aclk", "hclk", "sclk";
1167 reset-names = "core", "axi", "ahb";
1168 power-domains = <&power RK3588_PD_VDPU>;
1171 vepu121_0: video-codec@fdba0000 {
1172 compatible = "rockchip,rk3588-vepu121";
1176 clock-names = "aclk", "hclk";
1178 power-domains = <&power RK3588_PD_VDPU>;
1182 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1186 clock-names = "aclk", "iface";
1187 power-domains = <&power RK3588_PD_VDPU>;
1188 #iommu-cells = <0>;
1191 vepu121_1: video-codec@fdba4000 {
1192 compatible = "rockchip,rk3588-vepu121";
1196 clock-names = "aclk", "hclk";
1198 power-domains = <&power RK3588_PD_VDPU>;
1202 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1206 clock-names = "aclk", "iface";
1207 power-domains = <&power RK3588_PD_VDPU>;
1208 #iommu-cells = <0>;
1211 vepu121_2: video-codec@fdba8000 {
1212 compatible = "rockchip,rk3588-vepu121";
1216 clock-names = "aclk", "hclk";
1218 power-domains = <&power RK3588_PD_VDPU>;
1222 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1226 clock-names = "aclk", "iface";
1227 power-domains = <&power RK3588_PD_VDPU>;
1228 #iommu-cells = <0>;
1231 vepu121_3: video-codec@fdbac000 {
1232 compatible = "rockchip,rk3588-vepu121";
1236 clock-names = "aclk", "hclk";
1238 power-domains = <&power RK3588_PD_VDPU>;
1242 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1246 clock-names = "aclk", "iface";
1247 power-domains = <&power RK3588_PD_VDPU>;
1248 #iommu-cells = <0>;
1251 av1d: video-codec@fdc70000 {
1252 compatible = "rockchip,rk3588-av1-vpu";
1255 interrupt-names = "vdpu";
1256 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
1257 assigned-clock-rates = <400000000>, <400000000>;
1259 clock-names = "aclk", "hclk";
1260 power-domains = <&power RK3588_PD_AV1>;
1265 compatible = "rockchip,rk3588-vop";
1267 reg-names = "vop", "gamma-lut";
1277 clock-names = "aclk",
1286 power-domains = <&power RK3588_PD_VOP>;
1288 rockchip,vop-grf = <&vop_grf>;
1289 rockchip,vo1-grf = <&vo1_grf>;
1294 #address-cells = <1>;
1295 #size-cells = <0>;
1298 #address-cells = <1>;
1299 #size-cells = <0>;
1304 #address-cells = <1>;
1305 #size-cells = <0>;
1310 #address-cells = <1>;
1311 #size-cells = <0>;
1316 #address-cells = <1>;
1317 #size-cells = <0>;
1324 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1328 clock-names = "aclk", "iface";
1329 #iommu-cells = <0>;
1330 power-domains = <&power RK3588_PD_VOP>;
1334 spdif_tx2: spdif-tx@fddb0000 {
1335 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
1337 assigned-clock-parents = <&cru PLL_AUPLL>;
1338 assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>;
1339 clock-names = "mclk", "hclk";
1341 dma-names = "tx";
1344 power-domains = <&power RK3588_PD_VO0>;
1345 #sound-dai-cells = <0>;
1350 compatible = "rockchip,rk3588-i2s-tdm";
1354 clock-names = "mclk_tx", "mclk_rx", "hclk";
1355 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
1356 assigned-clock-parents = <&cru PLL_AUPLL>;
1358 dma-names = "tx";
1359 power-domains = <&power RK3588_PD_VO0>;
1361 reset-names = "tx-m";
1362 #sound-dai-cells = <0>;
1366 spdif_tx3: spdif-tx@fdde0000 {
1367 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
1369 assigned-clock-parents = <&cru PLL_AUPLL>;
1370 assigned-clocks = <&cru CLK_SPDIF3_SRC>;
1371 clock-names = "mclk", "hclk";
1373 dma-names = "tx";
1376 power-domains = <&power RK3588_PD_VO1>;
1377 #sound-dai-cells = <0>;
1382 compatible = "rockchip,rk3588-i2s-tdm";
1386 clock-names = "mclk_tx", "mclk_rx", "hclk";
1387 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
1388 assigned-clock-parents = <&cru PLL_AUPLL>;
1390 dma-names = "tx";
1391 power-domains = <&power RK3588_PD_VO1>;
1393 reset-names = "tx-m";
1394 #sound-dai-cells = <0>;
1399 compatible = "rockchip,rk3588-i2s-tdm";
1403 clock-names = "mclk_tx", "mclk_rx", "hclk";
1404 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
1405 assigned-clock-parents = <&cru PLL_AUPLL>;
1407 dma-names = "rx";
1408 power-domains = <&power RK3588_PD_VO1>;
1410 reset-names = "rx-m";
1411 #sound-dai-cells = <0>;
1416 compatible = "rockchip,rk3588-dw-hdmi-qp";
1424 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
1430 interrupt-names = "avp", "cec", "earc", "main", "hpd";
1432 pinctrl-names = "default";
1433 pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
1435 power-domains = <&power RK3588_PD_VO1>;
1437 reset-names = "ref", "hdp";
1439 rockchip,vo-grf = <&vo1_grf>;
1440 #sound-dai-cells = <0>;
1444 #address-cells = <1>;
1445 #size-cells = <0>;
1458 compatible = "rockchip,rk3588-qos", "syscon";
1463 compatible = "rockchip,rk3588-qos", "syscon";
1468 compatible = "rockchip,rk3588-qos", "syscon";
1473 compatible = "rockchip,rk3588-qos", "syscon";
1478 compatible = "rockchip,rk3588-qos", "syscon";
1483 compatible = "rockchip,rk3588-qos", "syscon";
1488 compatible = "rockchip,rk3588-qos", "syscon";
1493 compatible = "rockchip,rk3588-qos", "syscon";
1498 compatible = "rockchip,rk3588-qos", "syscon";
1503 compatible = "rockchip,rk3588-qos", "syscon";
1508 compatible = "rockchip,rk3588-qos", "syscon";
1513 compatible = "rockchip,rk3588-qos", "syscon";
1518 compatible = "rockchip,rk3588-qos", "syscon";
1523 compatible = "rockchip,rk3588-qos", "syscon";
1528 compatible = "rockchip,rk3588-qos", "syscon";
1533 compatible = "rockchip,rk3588-qos", "syscon";
1538 compatible = "rockchip,rk3588-qos", "syscon";
1543 compatible = "rockchip,rk3588-qos", "syscon";
1548 compatible = "rockchip,rk3588-qos", "syscon";
1553 compatible = "rockchip,rk3588-qos", "syscon";
1558 compatible = "rockchip,rk3588-qos", "syscon";
1563 compatible = "rockchip,rk3588-qos", "syscon";
1568 compatible = "rockchip,rk3588-qos", "syscon";
1573 compatible = "rockchip,rk3588-qos", "syscon";
1578 compatible = "rockchip,rk3588-qos", "syscon";
1583 compatible = "rockchip,rk3588-qos", "syscon";
1588 compatible = "rockchip,rk3588-qos", "syscon";
1593 compatible = "rockchip,rk3588-qos", "syscon";
1598 compatible = "rockchip,rk3588-qos", "syscon";
1603 compatible = "rockchip,rk3588-qos", "syscon";
1608 compatible = "rockchip,rk3588-qos", "syscon";
1613 compatible = "rockchip,rk3588-qos", "syscon";
1618 compatible = "rockchip,rk3588-qos", "syscon";
1623 compatible = "rockchip,rk3588-qos", "syscon";
1628 compatible = "rockchip,rk3588-qos", "syscon";
1633 compatible = "rockchip,rk3588-qos", "syscon";
1638 compatible = "rockchip,rk3588-qos", "syscon";
1643 compatible = "rockchip,rk3588-qos", "syscon";
1648 compatible = "rockchip,rk3588-qos", "syscon";
1653 compatible = "rockchip,rk3588-qos", "syscon";
1658 compatible = "rockchip,rk3588-qos", "syscon";
1663 compatible = "rockchip,rk3588-qos", "syscon";
1668 compatible = "rockchip,rk3588-qos", "syscon";
1673 compatible = "rockchip,rk3588-qos", "syscon";
1678 compatible = "rockchip,rk3588-qos", "syscon";
1683 compatible = "rockchip,rk3588-qos", "syscon";
1688 compatible = "rockchip,rk3588-qos", "syscon";
1693 compatible = "rockchip,rk3588-qos", "syscon";
1699 compatible = "rockchip,rk3588-dfi";
1708 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1709 bus-range = <0x30 0x3f>;
1713 clock-names = "aclk_mst", "aclk_slv",
1722 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1723 #interrupt-cells = <1>;
1724 interrupt-map-mask = <0 0 0 7>;
1725 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
1729 linux,pci-domain = <3>;
1730 max-link-speed = <2>;
1731 msi-map = <0x3000 &its0 0x3000 0x1000>;
1732 iommu-map = <0x3000 &mmu600_pcie 0x3000 0x1000>;
1733 num-lanes = <1>;
1735 phy-names = "pcie-phy";
1736 power-domains = <&power RK3588_PD_PCIE>;
1743 reg-names = "dbi", "apb", "config";
1745 reset-names = "pwr", "pipe";
1746 #address-cells = <3>;
1747 #size-cells = <2>;
1750 pcie2x1l1_intc: legacy-interrupt-controller {
1751 interrupt-controller;
1752 #address-cells = <0>;
1753 #interrupt-cells = <1>;
1754 interrupt-parent = <&gic>;
1760 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1761 bus-range = <0x40 0x4f>;
1765 clock-names = "aclk_mst", "aclk_slv",
1774 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1775 #interrupt-cells = <1>;
1776 interrupt-map-mask = <0 0 0 7>;
1777 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
1781 linux,pci-domain = <4>;
1782 max-link-speed = <2>;
1783 msi-map = <0x4000 &its0 0x4000 0x1000>;
1784 iommu-map = <0x4000 &mmu600_pcie 0x4000 0x1000>;
1785 num-lanes = <1>;
1787 phy-names = "pcie-phy";
1788 power-domains = <&power RK3588_PD_PCIE>;
1795 reg-names = "dbi", "apb", "config";
1797 reset-names = "pwr", "pipe";
1798 #address-cells = <3>;
1799 #size-cells = <2>;
1802 pcie2x1l2_intc: legacy-interrupt-controller {
1803 interrupt-controller;
1804 #address-cells = <0>;
1805 #interrupt-cells = <1>;
1806 interrupt-parent = <&gic>;
1812 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
1816 interrupt-names = "macirq", "eth_wake_irq";
1820 clock-names = "stmmaceth", "clk_mac_ref",
1823 power-domains = <&power RK3588_PD_GMAC>;
1825 reset-names = "stmmaceth";
1827 rockchip,php-grf = <&php_grf>;
1828 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1829 snps,mixed-burst;
1830 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1831 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1836 compatible = "snps,dwmac-mdio";
1837 #address-cells = <0x1>;
1838 #size-cells = <0x0>;
1841 gmac1_stmmac_axi_setup: stmmac-axi-config {
1847 gmac1_mtl_rx_setup: rx-queues-config {
1848 snps,rx-queues-to-use = <2>;
1853 gmac1_mtl_tx_setup: tx-queues-config {
1854 snps,tx-queues-to-use = <2>;
1861 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1867 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1868 ports-implemented = <0x1>;
1869 #address-cells = <1>;
1870 #size-cells = <0>;
1873 sata-port@0 {
1875 hba-port-cap = <HBA_PORT_FBSCP>;
1877 phy-names = "sata-phy";
1878 snps,rx-ts-max = <32>;
1879 snps,tx-ts-max = <32>;
1884 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1890 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1891 ports-implemented = <0x1>;
1892 #address-cells = <1>;
1893 #size-cells = <0>;
1896 sata-port@0 {
1898 hba-port-cap = <HBA_PORT_FBSCP>;
1900 phy-names = "sata-phy";
1901 snps,rx-ts-max = <32>;
1902 snps,tx-ts-max = <32>;
1911 clock-names = "clk_sfc", "hclk_sfc";
1912 #address-cells = <1>;
1913 #size-cells = <0>;
1918 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1923 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1924 fifo-depth = <0x100>;
1925 max-frequency = <200000000>;
1926 pinctrl-names = "default";
1927 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1928 power-domains = <&power RK3588_PD_SDMMC>;
1933 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1938 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1939 fifo-depth = <0x100>;
1940 max-frequency = <200000000>;
1941 pinctrl-names = "default";
1942 pinctrl-0 = <&sdiom1_pins>;
1943 power-domains = <&power RK3588_PD_SDIO>;
1948 compatible = "rockchip,rk3588-dwcmshc";
1951 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
1952 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1956 clock-names = "core", "bus", "axi", "block", "timer";
1957 max-frequency = <200000000>;
1958 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1960 pinctrl-names = "default";
1964 reset-names = "core", "bus", "axi", "block", "timer";
1969 compatible = "rockchip,rk3588-rng";
1977 compatible = "rockchip,rk3588-i2s-tdm";
1981 clock-names = "mclk_tx", "mclk_rx", "hclk";
1982 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1983 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
1985 dma-names = "tx", "rx";
1986 power-domains = <&power RK3588_PD_AUDIO>;
1988 reset-names = "tx-m", "rx-m";
1989 rockchip,trcm-sync-tx-only;
1990 pinctrl-names = "default";
1991 pinctrl-0 = <&i2s0_lrck
2001 #sound-dai-cells = <0>;
2006 compatible = "rockchip,rk3588-i2s-tdm";
2010 clock-names = "mclk_tx", "mclk_rx", "hclk";
2012 dma-names = "tx", "rx";
2014 reset-names = "tx-m", "rx-m";
2015 rockchip,trcm-sync-tx-only;
2016 pinctrl-names = "default";
2017 pinctrl-0 = <&i2s1m0_lrck
2027 #sound-dai-cells = <0>;
2032 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
2036 clock-names = "i2s_clk", "i2s_hclk";
2037 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
2038 assigned-clock-parents = <&cru PLL_AUPLL>;
2040 dma-names = "tx", "rx";
2041 power-domains = <&power RK3588_PD_AUDIO>;
2042 pinctrl-names = "default";
2043 pinctrl-0 = <&i2s2m1_lrck
2047 #sound-dai-cells = <0>;
2052 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
2056 clock-names = "i2s_clk", "i2s_hclk";
2057 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
2058 assigned-clock-parents = <&cru PLL_AUPLL>;
2060 dma-names = "tx", "rx";
2061 power-domains = <&power RK3588_PD_AUDIO>;
2062 pinctrl-names = "default";
2063 pinctrl-0 = <&i2s3_lrck
2067 #sound-dai-cells = <0>;
2071 spdif_tx0: spdif-tx@fe4e0000 {
2072 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
2074 assigned-clock-parents = <&cru PLL_AUPLL>;
2075 assigned-clocks = <&cru CLK_SPDIF0_SRC>;
2076 clock-names = "mclk", "hclk";
2078 dma-names = "tx";
2081 pinctrl-0 = <&spdif0m0_tx>;
2082 pinctrl-names = "default";
2083 power-domains = <&power RK3588_PD_AUDIO>;
2084 #sound-dai-cells = <0>;
2088 spdif_tx1: spdif-tx@fe4f0000 {
2089 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
2091 assigned-clock-parents = <&cru PLL_AUPLL>;
2092 assigned-clocks = <&cru CLK_SPDIF1_SRC>;
2093 clock-names = "mclk", "hclk";
2095 dma-names = "tx";
2098 pinctrl-0 = <&spdif1m0_tx>;
2099 pinctrl-names = "default";
2100 power-domains = <&power RK3588_PD_AUDIO>;
2101 #sound-dai-cells = <0>;
2105 gic: interrupt-controller@fe600000 {
2106 compatible = "arm,gic-v3";
2110 interrupt-controller;
2111 dma-noncoherent;
2112 mbi-alias = <0x0 0xfe610000>;
2113 mbi-ranges = <424 56>;
2114 msi-controller;
2116 #address-cells = <2>;
2117 #interrupt-cells = <4>;
2118 #size-cells = <2>;
2120 its0: msi-controller@fe640000 {
2121 compatible = "arm,gic-v3-its";
2123 dma-noncoherent;
2124 msi-controller;
2125 #msi-cells = <1>;
2128 its1: msi-controller@fe660000 {
2129 compatible = "arm,gic-v3-its";
2131 dma-noncoherent;
2132 msi-controller;
2133 #msi-cells = <1>;
2136 ppi-partitions {
2137 ppi_partition0: interrupt-partition-0 {
2141 ppi_partition1: interrupt-partition-1 {
2147 dmac0: dma-controller@fea10000 {
2152 arm,pl330-periph-burst;
2154 clock-names = "apb_pclk";
2155 #dma-cells = <1>;
2158 dmac1: dma-controller@fea30000 {
2163 arm,pl330-periph-burst;
2165 clock-names = "apb_pclk";
2166 #dma-cells = <1>;
2170 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2173 clock-names = "i2c", "pclk";
2175 pinctrl-0 = <&i2c1m0_xfer>;
2176 pinctrl-names = "default";
2177 #address-cells = <1>;
2178 #size-cells = <0>;
2183 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2186 clock-names = "i2c", "pclk";
2188 pinctrl-0 = <&i2c2m0_xfer>;
2189 pinctrl-names = "default";
2190 #address-cells = <1>;
2191 #size-cells = <0>;
2196 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2199 clock-names = "i2c", "pclk";
2201 pinctrl-0 = <&i2c3m0_xfer>;
2202 pinctrl-names = "default";
2203 #address-cells = <1>;
2204 #size-cells = <0>;
2209 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2212 clock-names = "i2c", "pclk";
2214 pinctrl-0 = <&i2c4m0_xfer>;
2215 pinctrl-names = "default";
2216 #address-cells = <1>;
2217 #size-cells = <0>;
2222 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2225 clock-names = "i2c", "pclk";
2227 pinctrl-0 = <&i2c5m0_xfer>;
2228 pinctrl-names = "default";
2229 #address-cells = <1>;
2230 #size-cells = <0>;
2235 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
2239 clock-names = "pclk", "timer";
2243 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
2246 clock-names = "tclk", "pclk";
2251 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2255 clock-names = "spiclk", "apb_pclk";
2257 dma-names = "tx", "rx";
2258 num-cs = <2>;
2259 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
2260 pinctrl-names = "default";
2261 #address-cells = <1>;
2262 #size-cells = <0>;
2267 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2271 clock-names = "spiclk", "apb_pclk";
2273 dma-names = "tx", "rx";
2274 num-cs = <2>;
2275 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
2276 pinctrl-names = "default";
2277 #address-cells = <1>;
2278 #size-cells = <0>;
2283 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2287 clock-names = "spiclk", "apb_pclk";
2289 dma-names = "tx", "rx";
2290 num-cs = <2>;
2291 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
2292 pinctrl-names = "default";
2293 #address-cells = <1>;
2294 #size-cells = <0>;
2299 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2303 clock-names = "spiclk", "apb_pclk";
2305 dma-names = "tx", "rx";
2306 num-cs = <2>;
2307 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
2308 pinctrl-names = "default";
2309 #address-cells = <1>;
2310 #size-cells = <0>;
2315 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2319 clock-names = "baudclk", "apb_pclk";
2321 dma-names = "tx", "rx";
2322 pinctrl-0 = <&uart1m1_xfer>;
2323 pinctrl-names = "default";
2324 reg-io-width = <4>;
2325 reg-shift = <2>;
2330 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2334 clock-names = "baudclk", "apb_pclk";
2336 dma-names = "tx", "rx";
2337 pinctrl-0 = <&uart2m1_xfer>;
2338 pinctrl-names = "default";
2339 reg-io-width = <4>;
2340 reg-shift = <2>;
2345 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2349 clock-names = "baudclk", "apb_pclk";
2351 dma-names = "tx", "rx";
2352 pinctrl-0 = <&uart3m1_xfer>;
2353 pinctrl-names = "default";
2354 reg-io-width = <4>;
2355 reg-shift = <2>;
2360 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2364 clock-names = "baudclk", "apb_pclk";
2366 dma-names = "tx", "rx";
2367 pinctrl-0 = <&uart4m1_xfer>;
2368 pinctrl-names = "default";
2369 reg-io-width = <4>;
2370 reg-shift = <2>;
2375 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2379 clock-names = "baudclk", "apb_pclk";
2381 dma-names = "tx", "rx";
2382 pinctrl-0 = <&uart5m1_xfer>;
2383 pinctrl-names = "default";
2384 reg-io-width = <4>;
2385 reg-shift = <2>;
2390 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2394 clock-names = "baudclk", "apb_pclk";
2396 dma-names = "tx", "rx";
2397 pinctrl-0 = <&uart6m1_xfer>;
2398 pinctrl-names = "default";
2399 reg-io-width = <4>;
2400 reg-shift = <2>;
2405 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2409 clock-names = "baudclk", "apb_pclk";
2411 dma-names = "tx", "rx";
2412 pinctrl-0 = <&uart7m1_xfer>;
2413 pinctrl-names = "default";
2414 reg-io-width = <4>;
2415 reg-shift = <2>;
2420 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2424 clock-names = "baudclk", "apb_pclk";
2426 dma-names = "tx", "rx";
2427 pinctrl-0 = <&uart8m1_xfer>;
2428 pinctrl-names = "default";
2429 reg-io-width = <4>;
2430 reg-shift = <2>;
2435 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2439 clock-names = "baudclk", "apb_pclk";
2441 dma-names = "tx", "rx";
2442 pinctrl-0 = <&uart9m1_xfer>;
2443 pinctrl-names = "default";
2444 reg-io-width = <4>;
2445 reg-shift = <2>;
2450 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2453 clock-names = "pwm", "pclk";
2454 pinctrl-0 = <&pwm4m0_pins>;
2455 pinctrl-names = "default";
2456 #pwm-cells = <3>;
2461 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2464 clock-names = "pwm", "pclk";
2465 pinctrl-0 = <&pwm5m0_pins>;
2466 pinctrl-names = "default";
2467 #pwm-cells = <3>;
2472 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2475 clock-names = "pwm", "pclk";
2476 pinctrl-0 = <&pwm6m0_pins>;
2477 pinctrl-names = "default";
2478 #pwm-cells = <3>;
2483 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2486 clock-names = "pwm", "pclk";
2487 pinctrl-0 = <&pwm7m0_pins>;
2488 pinctrl-names = "default";
2489 #pwm-cells = <3>;
2494 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2497 clock-names = "pwm", "pclk";
2498 pinctrl-0 = <&pwm8m0_pins>;
2499 pinctrl-names = "default";
2500 #pwm-cells = <3>;
2505 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2508 clock-names = "pwm", "pclk";
2509 pinctrl-0 = <&pwm9m0_pins>;
2510 pinctrl-names = "default";
2511 #pwm-cells = <3>;
2516 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2519 clock-names = "pwm", "pclk";
2520 pinctrl-0 = <&pwm10m0_pins>;
2521 pinctrl-names = "default";
2522 #pwm-cells = <3>;
2527 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2530 clock-names = "pwm", "pclk";
2531 pinctrl-0 = <&pwm11m0_pins>;
2532 pinctrl-names = "default";
2533 #pwm-cells = <3>;
2538 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2541 clock-names = "pwm", "pclk";
2542 pinctrl-0 = <&pwm12m0_pins>;
2543 pinctrl-names = "default";
2544 #pwm-cells = <3>;
2549 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2552 clock-names = "pwm", "pclk";
2553 pinctrl-0 = <&pwm13m0_pins>;
2554 pinctrl-names = "default";
2555 #pwm-cells = <3>;
2560 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2563 clock-names = "pwm", "pclk";
2564 pinctrl-0 = <&pwm14m0_pins>;
2565 pinctrl-names = "default";
2566 #pwm-cells = <3>;
2571 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2574 clock-names = "pwm", "pclk";
2575 pinctrl-0 = <&pwm15m0_pins>;
2576 pinctrl-names = "default";
2577 #pwm-cells = <3>;
2581 thermal_zones: thermal-zones {
2583 package_thermal: package-thermal {
2584 polling-delay-passive = <0>;
2585 polling-delay = <0>;
2586 thermal-sensors = <&tsadc 0>;
2589 package_crit: package-crit {
2598 bigcore0_thermal: bigcore0-thermal {
2599 polling-delay-passive = <100>;
2600 polling-delay = <0>;
2601 thermal-sensors = <&tsadc 1>;
2604 bigcore0_alert: bigcore0-alert {
2610 bigcore0_crit: bigcore0-crit {
2617 cooling-maps {
2620 cooling-device =
2628 bigcore2_thermal: bigcore2-thermal {
2629 polling-delay-passive = <100>;
2630 polling-delay = <0>;
2631 thermal-sensors = <&tsadc 2>;
2634 bigcore2_alert: bigcore2-alert {
2640 bigcore2_crit: bigcore2-crit {
2647 cooling-maps {
2650 cooling-device =
2658 little_core_thermal: littlecore-thermal {
2659 polling-delay-passive = <100>;
2660 polling-delay = <0>;
2661 thermal-sensors = <&tsadc 3>;
2664 littlecore_alert: littlecore-alert {
2670 littlecore_crit: littlecore-crit {
2677 cooling-maps {
2680 cooling-device =
2690 center_thermal: center-thermal {
2691 polling-delay-passive = <0>;
2692 polling-delay = <0>;
2693 thermal-sensors = <&tsadc 4>;
2696 center_crit: center-crit {
2704 gpu_thermal: gpu-thermal {
2705 polling-delay-passive = <100>;
2706 polling-delay = <0>;
2707 thermal-sensors = <&tsadc 5>;
2710 gpu_alert: gpu-alert {
2716 gpu_crit: gpu-crit {
2723 cooling-maps {
2726 cooling-device =
2732 npu_thermal: npu-thermal {
2733 polling-delay-passive = <0>;
2734 polling-delay = <0>;
2735 thermal-sensors = <&tsadc 6>;
2738 npu_crit: npu-crit {
2748 compatible = "rockchip,rk3588-tsadc";
2752 clock-names = "tsadc", "apb_pclk";
2753 assigned-clocks = <&cru CLK_TSADC>;
2754 assigned-clock-rates = <2000000>;
2756 reset-names = "tsadc-apb", "tsadc";
2757 rockchip,hw-tshut-temp = <120000>;
2758 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2759 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2760 pinctrl-0 = <&tsadc_shut_org>;
2761 pinctrl-1 = <&tsadc_gpio_func>;
2762 pinctrl-names = "default", "sleep";
2763 #thermal-sensor-cells = <1>;
2768 compatible = "rockchip,rk3588-saradc";
2771 #io-channel-cells = <1>;
2773 clock-names = "saradc", "apb_pclk";
2775 reset-names = "saradc-apb";
2780 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2783 clock-names = "i2c", "pclk";
2785 pinctrl-0 = <&i2c6m0_xfer>;
2786 pinctrl-names = "default";
2787 #address-cells = <1>;
2788 #size-cells = <0>;
2793 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2796 clock-names = "i2c", "pclk";
2798 pinctrl-0 = <&i2c7m0_xfer>;
2799 pinctrl-names = "default";
2800 #address-cells = <1>;
2801 #size-cells = <0>;
2806 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2809 clock-names = "i2c", "pclk";
2811 pinctrl-0 = <&i2c8m0_xfer>;
2812 pinctrl-names = "default";
2813 #address-cells = <1>;
2814 #size-cells = <0>;
2819 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2823 clock-names = "spiclk", "apb_pclk";
2825 dma-names = "tx", "rx";
2826 num-cs = <2>;
2827 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
2828 pinctrl-names = "default";
2829 #address-cells = <1>;
2830 #size-cells = <0>;
2835 compatible = "rockchip,rk3588-otp";
2839 clock-names = "otp", "apb_pclk", "phy", "arb";
2842 reset-names = "otp", "apb", "arb";
2843 #address-cells = <1>;
2844 #size-cells = <1>;
2846 cpu_code: cpu-code@2 {
2854 cpub0_leakage: cpu-leakage@17 {
2858 cpub1_leakage: cpu-leakage@18 {
2862 cpul_leakage: cpu-leakage@19 {
2866 log_leakage: log-leakage@1a {
2870 gpu_leakage: gpu-leakage@1b {
2874 otp_cpu_version: cpu-version@1c {
2879 npu_leakage: npu-leakage@28 {
2883 codec_leakage: codec-leakage@29 {
2888 dmac2: dma-controller@fed10000 {
2893 arm,pl330-periph-burst;
2895 clock-names = "apb_pclk";
2896 #dma-cells = <1>;
2900 compatible = "rockchip,rk3588-hdptx-phy";
2903 clock-names = "ref", "apb";
2904 #clock-cells = <0>;
2905 #phy-cells = <0>;
2910 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
2917 compatible = "rockchip,rk3588-usbdp-phy";
2919 #phy-cells = <1>;
2924 clock-names = "refclk", "immortal", "pclk", "utmi";
2930 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
2931 rockchip,u2phy-grf = <&usb2phy0_grf>;
2932 rockchip,usb-grf = <&usb_grf>;
2933 rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
2934 rockchip,vo-grf = <&vo0_grf>;
2939 compatible = "rockchip,rk3588-naneng-combphy";
2943 clock-names = "ref", "apb", "pipe";
2944 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
2945 assigned-clock-rates = <100000000>;
2946 #phy-cells = <1>;
2948 reset-names = "phy", "apb";
2949 rockchip,pipe-grf = <&php_grf>;
2950 rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
2955 compatible = "rockchip,rk3588-naneng-combphy";
2959 clock-names = "ref", "apb", "pipe";
2960 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
2961 assigned-clock-rates = <100000000>;
2962 #phy-cells = <1>;
2964 reset-names = "phy", "apb";
2965 rockchip,pipe-grf = <&php_grf>;
2966 rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
2971 compatible = "mmio-sram";
2974 #address-cells = <1>;
2975 #size-cells = <1>;
2979 compatible = "rockchip,rk3588-pinctrl";
2982 #address-cells = <2>;
2983 #size-cells = <2>;
2986 compatible = "rockchip,gpio-bank";
2990 gpio-controller;
2991 gpio-ranges = <&pinctrl 0 0 32>;
2992 interrupt-controller;
2993 #gpio-cells = <2>;
2994 #interrupt-cells = <2>;
2998 compatible = "rockchip,gpio-bank";
3002 gpio-controller;
3003 gpio-ranges = <&pinctrl 0 32 32>;
3004 interrupt-controller;
3005 #gpio-cells = <2>;
3006 #interrupt-cells = <2>;
3010 compatible = "rockchip,gpio-bank";
3014 gpio-controller;
3015 gpio-ranges = <&pinctrl 0 64 32>;
3016 interrupt-controller;
3017 #gpio-cells = <2>;
3018 #interrupt-cells = <2>;
3022 compatible = "rockchip,gpio-bank";
3026 gpio-controller;
3027 gpio-ranges = <&pinctrl 0 96 32>;
3028 interrupt-controller;
3029 #gpio-cells = <2>;
3030 #interrupt-cells = <2>;
3034 compatible = "rockchip,gpio-bank";
3038 gpio-controller;
3039 gpio-ranges = <&pinctrl 0 128 32>;
3040 interrupt-controller;
3041 #gpio-cells = <2>;
3042 #interrupt-cells = <2>;
3047 #include "rk3588-base-pinctrl.dtsi"