Lines Matching full:cru
6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
11 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
455 clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
456 <&cru CLK_GPU_STACKS>;
471 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
472 <&cru ACLK_USB3OTG0>;
479 resets = <&cru SRST_A_USB3OTG0>;
493 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
504 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
515 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
526 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
537 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
538 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
539 <&cru CLK_PIPEPHY2_PIPE_U3_G>;
545 resets = <&cru SRST_A_USB3OTG2>;
605 clocks = <&cru PCLK_VO0GRF>;
611 clocks = <&cru PCLK_VO1GRF>;
649 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
653 resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
674 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
678 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
699 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
703 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
732 cru: clock-controller@fd7c0000 { label
733 compatible = "rockchip,rk3588-cru";
736 <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
737 <&cru PLL_NPLL>, <&cru PLL_GPLL>,
738 <&cru ACLK_CENTER_ROOT>,
739 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
740 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
741 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
742 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
743 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
744 <&cru CLK_GPU>;
764 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
777 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
791 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
802 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
813 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
824 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
852 clocks = <&cru HCLK_NPU_ROOT>,
853 <&cru PCLK_NPU_ROOT>,
854 <&cru CLK_NPU_DSU0>,
855 <&cru HCLK_NPU_CM0_ROOT>;
865 clocks = <&cru HCLK_NPU_ROOT>,
866 <&cru PCLK_NPU_ROOT>,
867 <&cru CLK_NPU_DSU0>;
873 clocks = <&cru HCLK_NPU_ROOT>,
874 <&cru PCLK_NPU_ROOT>,
875 <&cru CLK_NPU_DSU0>;
884 clocks = <&cru CLK_GPU>,
885 <&cru CLK_GPU_COREGROUP>,
886 <&cru CLK_GPU_STACKS>;
902 clocks = <&cru HCLK_RKVDEC0>,
903 <&cru HCLK_VDPU_ROOT>,
904 <&cru ACLK_VDPU_ROOT>,
905 <&cru ACLK_RKVDEC0>,
906 <&cru ACLK_RKVDEC_CCU>;
912 clocks = <&cru HCLK_RKVDEC1>,
913 <&cru HCLK_VDPU_ROOT>,
914 <&cru ACLK_VDPU_ROOT>,
915 <&cru ACLK_RKVDEC1>;
921 clocks = <&cru HCLK_RKVENC0>,
922 <&cru ACLK_RKVENC0>;
932 clocks = <&cru HCLK_RKVENC1>,
933 <&cru HCLK_RKVENC0>,
934 <&cru ACLK_RKVENC0>,
935 <&cru ACLK_RKVENC1>;
946 clocks = <&cru HCLK_VDPU_ROOT>,
947 <&cru ACLK_VDPU_LOW_ROOT>,
948 <&cru ACLK_VDPU_ROOT>,
949 <&cru ACLK_JPEG_DECODER_ROOT>,
950 <&cru ACLK_IEP2P0>,
951 <&cru HCLK_IEP2P0>,
952 <&cru ACLK_JPEG_ENCODER0>,
953 <&cru HCLK_JPEG_ENCODER0>,
954 <&cru ACLK_JPEG_ENCODER1>,
955 <&cru HCLK_JPEG_ENCODER1>,
956 <&cru ACLK_JPEG_ENCODER2>,
957 <&cru HCLK_JPEG_ENCODER2>,
958 <&cru ACLK_JPEG_ENCODER3>,
959 <&cru HCLK_JPEG_ENCODER3>,
960 <&cru ACLK_JPEG_DECODER>,
961 <&cru HCLK_JPEG_DECODER>,
962 <&cru ACLK_RGA2>,
963 <&cru HCLK_RGA2>;
979 clocks = <&cru PCLK_AV1>,
980 <&cru ACLK_AV1>,
981 <&cru HCLK_VDPU_ROOT>;
987 clocks = <&cru HCLK_RKVDEC0>,
988 <&cru HCLK_VDPU_ROOT>,
989 <&cru ACLK_VDPU_ROOT>,
990 <&cru ACLK_RKVDEC0>;
996 clocks = <&cru HCLK_RKVDEC1>,
997 <&cru HCLK_VDPU_ROOT>,
998 <&cru ACLK_VDPU_ROOT>;
1004 clocks = <&cru ACLK_RGA3_0>,
1005 <&cru HCLK_RGA3_0>;
1012 clocks = <&cru PCLK_VOP_ROOT>,
1013 <&cru HCLK_VOP_ROOT>,
1014 <&cru ACLK_VOP>;
1023 clocks = <&cru PCLK_VO0_ROOT>,
1024 <&cru PCLK_VO0_S_ROOT>,
1025 <&cru HCLK_VO0_S_ROOT>,
1026 <&cru ACLK_VO0_ROOT>,
1027 <&cru HCLK_HDCP0>,
1028 <&cru ACLK_HDCP0>,
1029 <&cru HCLK_VOP_ROOT>;
1036 clocks = <&cru PCLK_VO1_ROOT>,
1037 <&cru PCLK_VO1_S_ROOT>,
1038 <&cru HCLK_VO1_S_ROOT>,
1039 <&cru HCLK_HDCP1>,
1040 <&cru ACLK_HDCP1>,
1041 <&cru ACLK_HDMIRX_ROOT>,
1042 <&cru HCLK_VO1USB_TOP_ROOT>;
1049 clocks = <&cru HCLK_VI_ROOT>,
1050 <&cru PCLK_VI_ROOT>,
1051 <&cru HCLK_ISP0>,
1052 <&cru ACLK_ISP0>,
1053 <&cru HCLK_VICAP>,
1054 <&cru ACLK_VICAP>;
1065 clocks = <&cru HCLK_ISP1>,
1066 <&cru ACLK_ISP1>,
1067 <&cru HCLK_VI_ROOT>,
1068 <&cru PCLK_VI_ROOT>;
1075 clocks = <&cru HCLK_FISHEYE0>,
1076 <&cru ACLK_FISHEYE0>,
1077 <&cru HCLK_FISHEYE1>,
1078 <&cru ACLK_FISHEYE1>,
1079 <&cru PCLK_VI_ROOT>;
1087 clocks = <&cru HCLK_RGA3_1>,
1088 <&cru ACLK_RGA3_1>;
1094 clocks = <&cru PCLK_PHP_ROOT>,
1095 <&cru ACLK_USB_ROOT>,
1096 <&cru ACLK_USB>,
1097 <&cru HCLK_USB_ROOT>,
1098 <&cru HCLK_HOST0>,
1099 <&cru HCLK_HOST_ARB0>,
1100 <&cru HCLK_HOST1>,
1101 <&cru HCLK_HOST_ARB1>;
1110 clocks = <&cru PCLK_PHP_ROOT>,
1111 <&cru ACLK_PCIE_ROOT>,
1112 <&cru ACLK_PHP_ROOT>;
1117 clocks = <&cru PCLK_PHP_ROOT>,
1118 <&cru ACLK_PCIE_ROOT>,
1119 <&cru ACLK_PHP_ROOT>;
1124 clocks = <&cru HCLK_SDIO>,
1125 <&cru HCLK_NVM_ROOT>;
1131 clocks = <&cru HCLK_AUDIO_ROOT>,
1132 <&cru PCLK_AUDIO_ROOT>;
1148 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1159 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1168 clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>;
1170 resets = <&cru SRST_RGA2_CORE>, <&cru SRST_A_RGA2>, <&cru SRST_H_RGA2>;
1179 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
1189 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
1199 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
1209 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
1219 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
1229 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
1239 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
1249 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
1260 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
1262 clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
1265 resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
1273 clocks = <&cru ACLK_VOP>,
1274 <&cru HCLK_VOP>,
1275 <&cru DCLK_VOP0>,
1276 <&cru DCLK_VOP1>,
1277 <&cru DCLK_VOP2>,
1278 <&cru DCLK_VOP3>,
1279 <&cru PCLK_VOP_ROOT>,
1331 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1341 assigned-clock-parents = <&cru PLL_AUPLL>;
1342 assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>;
1344 clocks = <&cru MCLK_SPDIF2>, <&cru HCLK_SPDIF2_DP0>;
1357 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
1359 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
1360 assigned-clock-parents = <&cru PLL_AUPLL>;
1364 resets = <&cru SRST_M_I2S4_8CH_TX>;
1373 assigned-clock-parents = <&cru PLL_AUPLL>;
1374 assigned-clocks = <&cru CLK_SPDIF3_SRC>;
1376 clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>;
1389 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
1391 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
1392 assigned-clock-parents = <&cru PLL_AUPLL>;
1396 resets = <&cru SRST_M_I2S5_8CH_TX>;
1406 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
1408 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
1409 assigned-clock-parents = <&cru PLL_AUPLL>;
1413 resets = <&cru SRST_M_I2S9_8CH_RX>;
1423 clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>;
1425 resets = <&cru SRST_P_DSIHOST0>;
1451 clocks = <&cru PCLK_DSIHOST1>, <&cru CLK_DSIHOST1>;
1453 resets = <&cru SRST_P_DSIHOST1>;
1478 clocks = <&cru PCLK_HDMITX0>,
1479 <&cru CLK_HDMITX0_EARC>,
1480 <&cru CLK_HDMITX0_REF>,
1481 <&cru MCLK_I2S5_8CH_TX>,
1482 <&cru CLK_HDMIHDP0>,
1483 <&cru HCLK_VO1>;
1496 resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
1520 clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>;
1526 resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>;
1798 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
1799 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
1800 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
1832 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
1850 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
1851 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
1852 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
1884 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
1905 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
1906 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
1907 <&cru CLK_GMAC1_PTP_REF>;
1912 resets = <&cru SRST_A_GMAC1>;
1952 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
1953 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
1954 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
1975 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
1976 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
1977 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
1998 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
2010 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
2024 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
2025 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
2039 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
2041 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
2042 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
2043 <&cru TMCLK_EMMC>;
2049 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
2050 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
2051 <&cru SRST_T_EMMC>;
2068 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
2070 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
2071 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
2075 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
2097 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
2101 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
2123 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
2125 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
2126 assigned-clock-parents = <&cru PLL_AUPLL>;
2143 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
2145 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
2146 assigned-clock-parents = <&cru PLL_AUPLL>;
2162 assigned-clock-parents = <&cru PLL_AUPLL>;
2163 assigned-clocks = <&cru CLK_SPDIF0_SRC>;
2165 clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>;
2179 assigned-clock-parents = <&cru PLL_AUPLL>;
2180 assigned-clocks = <&cru CLK_SPDIF1_SRC>;
2182 clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>;
2241 clocks = <&cru ACLK_DMAC0>;
2252 clocks = <&cru ACLK_DMAC1>;
2260 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
2273 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
2286 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
2299 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
2312 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
2326 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
2333 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
2342 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
2358 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
2374 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
2390 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
2406 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
2421 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
2436 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
2451 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
2466 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
2481 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
2496 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
2511 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
2526 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
2540 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2551 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2562 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2573 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2584 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2595 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2606 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2617 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2628 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2639 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2650 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2661 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2839 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
2841 assigned-clocks = <&cru CLK_TSADC>;
2843 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
2846 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2860 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
2862 resets = <&cru SRST_P_SARADC>;
2870 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
2883 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
2896 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
2910 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
2925 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
2926 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
2928 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
2929 <&cru SRST_OTPC_ARB>;
2982 clocks = <&cru ACLK_DMAC2>;
2990 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
2994 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
2995 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
2996 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
2997 <&cru SRST_HDPTX0_LCPLL>;
3008 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
3009 <&cru CLK_USBDP_PHY0_IMMORTAL>,
3010 <&cru PCLK_USBDPPHY0>,
3013 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
3014 <&cru SRST_USBDP_COMBO_PHY0_CMN>,
3015 <&cru SRST_USBDP_COMBO_PHY0_LANE>,
3016 <&cru SRST_USBDP_COMBO_PHY0_PCS>,
3017 <&cru SRST_P_USBDPPHY0>;
3030 clocks = <&cru PCLK_MIPI_DCPHY0>,
3031 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
3033 resets = <&cru SRST_M_MIPI_DCPHY0>,
3034 <&cru SRST_P_MIPI_DCPHY0>,
3035 <&cru SRST_P_MIPI_DCPHY0_GRF>,
3036 <&cru SRST_S_MIPI_DCPHY0>;
3046 clocks = <&cru PCLK_MIPI_DCPHY1>,
3047 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
3049 resets = <&cru SRST_M_MIPI_DCPHY1>,
3050 <&cru SRST_P_MIPI_DCPHY1>,
3051 <&cru SRST_P_MIPI_DCPHY1_GRF>,
3052 <&cru SRST_S_MIPI_DCPHY1>;
3061 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
3062 <&cru PCLK_PHP_ROOT>;
3064 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
3067 resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
3077 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
3078 <&cru PCLK_PHP_ROOT>;
3080 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
3083 resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
3109 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
3121 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
3133 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
3145 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
3157 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;