Lines Matching +full:crit +full:- +full:soc +full:- +full:level
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/rk3588-power.h>
11 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/ata/ahci.h>
14 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
56 #address-cells = <1>;
57 #size-cells = <0>;
59 cpu-map {
94 compatible = "arm,cortex-a55";
96 enable-method = "psci";
97 capacity-dmips-mhz = <530>;
99 cpu-idle-states = <&CPU_SLEEP>;
100 i-cache-size = <32768>;
101 i-cache-line-size = <64>;
102 i-cache-sets = <128>;
103 d-cache-size = <32768>;
104 d-cache-line-size = <64>;
105 d-cache-sets = <128>;
106 next-level-cache = <&l2_cache_l0>;
107 dynamic-power-coefficient = <228>;
108 #cooling-cells = <2>;
113 compatible = "arm,cortex-a55";
115 enable-method = "psci";
116 capacity-dmips-mhz = <530>;
118 cpu-idle-states = <&CPU_SLEEP>;
119 i-cache-size = <32768>;
120 i-cache-line-size = <64>;
121 i-cache-sets = <128>;
122 d-cache-size = <32768>;
123 d-cache-line-size = <64>;
124 d-cache-sets = <128>;
125 next-level-cache = <&l2_cache_l1>;
126 dynamic-power-coefficient = <228>;
127 #cooling-cells = <2>;
132 compatible = "arm,cortex-a55";
134 enable-method = "psci";
135 capacity-dmips-mhz = <530>;
137 cpu-idle-states = <&CPU_SLEEP>;
138 i-cache-size = <32768>;
139 i-cache-line-size = <64>;
140 i-cache-sets = <128>;
141 d-cache-size = <32768>;
142 d-cache-line-size = <64>;
143 d-cache-sets = <128>;
144 next-level-cache = <&l2_cache_l2>;
145 dynamic-power-coefficient = <228>;
146 #cooling-cells = <2>;
151 compatible = "arm,cortex-a55";
153 enable-method = "psci";
154 capacity-dmips-mhz = <530>;
156 cpu-idle-states = <&CPU_SLEEP>;
157 i-cache-size = <32768>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <128>;
160 d-cache-size = <32768>;
161 d-cache-line-size = <64>;
162 d-cache-sets = <128>;
163 next-level-cache = <&l2_cache_l3>;
164 dynamic-power-coefficient = <228>;
165 #cooling-cells = <2>;
170 compatible = "arm,cortex-a76";
172 enable-method = "psci";
173 capacity-dmips-mhz = <1024>;
175 cpu-idle-states = <&CPU_SLEEP>;
176 i-cache-size = <65536>;
177 i-cache-line-size = <64>;
178 i-cache-sets = <256>;
179 d-cache-size = <65536>;
180 d-cache-line-size = <64>;
181 d-cache-sets = <256>;
182 next-level-cache = <&l2_cache_b0>;
183 dynamic-power-coefficient = <416>;
184 #cooling-cells = <2>;
189 compatible = "arm,cortex-a76";
191 enable-method = "psci";
192 capacity-dmips-mhz = <1024>;
194 cpu-idle-states = <&CPU_SLEEP>;
195 i-cache-size = <65536>;
196 i-cache-line-size = <64>;
197 i-cache-sets = <256>;
198 d-cache-size = <65536>;
199 d-cache-line-size = <64>;
200 d-cache-sets = <256>;
201 next-level-cache = <&l2_cache_b1>;
202 dynamic-power-coefficient = <416>;
203 #cooling-cells = <2>;
208 compatible = "arm,cortex-a76";
210 enable-method = "psci";
211 capacity-dmips-mhz = <1024>;
213 cpu-idle-states = <&CPU_SLEEP>;
214 i-cache-size = <65536>;
215 i-cache-line-size = <64>;
216 i-cache-sets = <256>;
217 d-cache-size = <65536>;
218 d-cache-line-size = <64>;
219 d-cache-sets = <256>;
220 next-level-cache = <&l2_cache_b2>;
221 dynamic-power-coefficient = <416>;
222 #cooling-cells = <2>;
227 compatible = "arm,cortex-a76";
229 enable-method = "psci";
230 capacity-dmips-mhz = <1024>;
232 cpu-idle-states = <&CPU_SLEEP>;
233 i-cache-size = <65536>;
234 i-cache-line-size = <64>;
235 i-cache-sets = <256>;
236 d-cache-size = <65536>;
237 d-cache-line-size = <64>;
238 d-cache-sets = <256>;
239 next-level-cache = <&l2_cache_b3>;
240 dynamic-power-coefficient = <416>;
241 #cooling-cells = <2>;
244 idle-states {
245 entry-method = "psci";
246 CPU_SLEEP: cpu-sleep {
247 compatible = "arm,idle-state";
248 local-timer-stop;
249 arm,psci-suspend-param = <0x0010000>;
250 entry-latency-us = <100>;
251 exit-latency-us = <120>;
252 min-residency-us = <1000>;
256 l2_cache_l0: l2-cache-l0 {
258 cache-size = <131072>;
259 cache-line-size = <64>;
260 cache-sets = <512>;
261 cache-level = <2>;
262 cache-unified;
263 next-level-cache = <&l3_cache>;
266 l2_cache_l1: l2-cache-l1 {
268 cache-size = <131072>;
269 cache-line-size = <64>;
270 cache-sets = <512>;
271 cache-level = <2>;
272 cache-unified;
273 next-level-cache = <&l3_cache>;
276 l2_cache_l2: l2-cache-l2 {
278 cache-size = <131072>;
279 cache-line-size = <64>;
280 cache-sets = <512>;
281 cache-level = <2>;
282 cache-unified;
283 next-level-cache = <&l3_cache>;
286 l2_cache_l3: l2-cache-l3 {
288 cache-size = <131072>;
289 cache-line-size = <64>;
290 cache-sets = <512>;
291 cache-level = <2>;
292 cache-unified;
293 next-level-cache = <&l3_cache>;
296 l2_cache_b0: l2-cache-b0 {
298 cache-size = <524288>;
299 cache-line-size = <64>;
300 cache-sets = <1024>;
301 cache-level = <2>;
302 cache-unified;
303 next-level-cache = <&l3_cache>;
306 l2_cache_b1: l2-cache-b1 {
308 cache-size = <524288>;
309 cache-line-size = <64>;
310 cache-sets = <1024>;
311 cache-level = <2>;
312 cache-unified;
313 next-level-cache = <&l3_cache>;
316 l2_cache_b2: l2-cache-b2 {
318 cache-size = <524288>;
319 cache-line-size = <64>;
320 cache-sets = <1024>;
321 cache-level = <2>;
322 cache-unified;
323 next-level-cache = <&l3_cache>;
326 l2_cache_b3: l2-cache-b3 {
328 cache-size = <524288>;
329 cache-line-size = <64>;
330 cache-sets = <1024>;
331 cache-level = <2>;
332 cache-unified;
333 next-level-cache = <&l3_cache>;
341 l3_cache: l3-cache {
343 cache-size = <3145728>;
344 cache-line-size = <64>;
345 cache-sets = <4096>;
346 cache-level = <3>;
347 cache-unified;
350 display_subsystem: display-subsystem {
351 compatible = "rockchip,display-subsystem";
357 compatible = "arm,scmi-smc";
358 arm,smc-id = <0x82000010>;
360 #address-cells = <1>;
361 #size-cells = <0>;
365 #clock-cells = <1>;
370 #reset-cells = <1>;
375 hdmi0_sound: hdmi0-sound {
376 compatible = "simple-audio-card";
377 simple-audio-card,format = "i2s";
378 simple-audio-card,mclk-fs = <128>;
379 simple-audio-card,name = "hdmi0";
382 simple-audio-card,codec {
383 sound-dai = <&hdmi0>;
386 simple-audio-card,cpu {
387 sound-dai = <&i2s5_8ch>;
391 pmu-a55 {
392 compatible = "arm,cortex-a55-pmu";
396 pmu-a76 {
397 compatible = "arm,cortex-a76-pmu";
402 compatible = "arm,psci-1.0";
406 spll: clock-0 {
407 compatible = "fixed-clock";
408 clock-frequency = <702000000>;
409 clock-output-names = "spll";
410 #clock-cells = <0>;
414 compatible = "arm,armv8-timer";
420 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
423 xin24m: clock-1 {
424 compatible = "fixed-clock";
425 clock-frequency = <24000000>;
426 clock-output-names = "xin24m";
427 #clock-cells = <0>;
430 xin32k: clock-2 {
431 compatible = "fixed-clock";
432 clock-frequency = <32768>;
433 clock-output-names = "xin32k";
434 #clock-cells = <0>;
437 reserved-memory {
438 #address-cells = <2>;
439 #size-cells = <2>;
443 compatible = "arm,scmi-shmem";
445 no-map;
450 compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
452 #cooling-cells = <2>;
453 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
454 assigned-clock-rates = <200000000>;
457 clock-names = "core", "coregroup", "stacks";
458 dynamic-power-coefficient = <2982>;
462 interrupt-names = "job", "mmu", "gpu";
463 power-domains = <&power RK3588_PD_GPU>;
468 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
473 clock-names = "ref_clk", "suspend_clk", "bus_clk";
476 phy-names = "usb2-phy", "usb3-phy";
478 power-domains = <&power RK3588_PD_USB>;
481 snps,dis-u1-entry-quirk;
482 snps,dis-u2-entry-quirk;
483 snps,dis-u2-freeclk-exists-quirk;
484 snps,dis-del-phy-power-chg-quirk;
485 snps,dis-tx-ipgap-linecheck-quirk;
490 compatible = "rockchip,rk3588-ehci", "generic-ehci";
495 phy-names = "usb";
496 power-domains = <&power RK3588_PD_USB>;
501 compatible = "rockchip,rk3588-ohci", "generic-ohci";
506 phy-names = "usb";
507 power-domains = <&power RK3588_PD_USB>;
512 compatible = "rockchip,rk3588-ehci", "generic-ehci";
517 phy-names = "usb";
518 power-domains = <&power RK3588_PD_USB>;
523 compatible = "rockchip,rk3588-ohci", "generic-ohci";
528 phy-names = "usb";
529 power-domains = <&power RK3588_PD_USB>;
534 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
540 clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
543 phy-names = "usb3-phy";
547 snps,dis-u2-freeclk-exists-quirk;
548 snps,dis-del-phy-power-chg-quirk;
549 snps,dis-tx-ipgap-linecheck-quirk;
555 compatible = "arm,smmu-v3";
561 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
562 #iommu-cells = <1>;
566 compatible = "arm,smmu-v3";
572 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
573 #iommu-cells = <1>;
578 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
583 compatible = "rockchip,rk3588-sys-grf", "syscon";
588 compatible = "rockchip,rk3588-dcphy-grf", "syscon";
593 compatible = "rockchip,rk3588-dcphy-grf", "syscon";
598 compatible = "rockchip,rk3588-vop-grf", "syscon";
603 compatible = "rockchip,rk3588-vo0-grf", "syscon";
609 compatible = "rockchip,rk3588-vo1-grf", "syscon";
615 compatible = "rockchip,rk3588-usb-grf", "syscon";
620 compatible = "rockchip,rk3588-php-grf", "syscon";
625 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
630 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
635 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
640 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
642 #address-cells = <1>;
643 #size-cells = <1>;
646 compatible = "rockchip,rk3588-usb2phy";
648 #clock-cells = <0>;
650 clock-names = "phyclk";
651 clock-output-names = "usb480m_phy0";
654 reset-names = "phy", "apb";
657 u2phy0_otg: otg-port {
658 #phy-cells = <0>;
665 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
667 #address-cells = <1>;
668 #size-cells = <1>;
671 compatible = "rockchip,rk3588-usb2phy";
673 #clock-cells = <0>;
675 clock-names = "phyclk";
676 clock-output-names = "usb480m_phy2";
679 reset-names = "phy", "apb";
682 u2phy2_host: host-port {
683 #phy-cells = <0>;
690 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
692 #address-cells = <1>;
693 #size-cells = <1>;
696 compatible = "rockchip,rk3588-usb2phy";
698 #clock-cells = <0>;
700 clock-names = "phyclk";
701 clock-output-names = "usb480m_phy3";
704 reset-names = "phy", "apb";
707 u2phy3_host: host-port {
708 #phy-cells = <0>;
715 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
720 compatible = "rockchip,rk3588-ioc", "syscon";
725 compatible = "mmio-sram";
728 #address-cells = <1>;
729 #size-cells = <1>;
732 cru: clock-controller@fd7c0000 {
733 compatible = "rockchip,rk3588-cru";
735 assigned-clocks =
745 assigned-clock-rates =
756 #clock-cells = <1>;
757 #reset-cells = <1>;
761 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
765 clock-names = "i2c", "pclk";
766 pinctrl-0 = <&i2c0m0_xfer>;
767 pinctrl-names = "default";
768 #address-cells = <1>;
769 #size-cells = <0>;
774 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
778 clock-names = "baudclk", "apb_pclk";
780 dma-names = "tx", "rx";
781 pinctrl-0 = <&uart0m1_xfer>;
782 pinctrl-names = "default";
783 reg-shift = <2>;
784 reg-io-width = <4>;
789 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
792 clock-names = "pwm", "pclk";
793 pinctrl-0 = <&pwm0m0_pins>;
794 pinctrl-names = "default";
795 #pwm-cells = <3>;
800 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
803 clock-names = "pwm", "pclk";
804 pinctrl-0 = <&pwm1m0_pins>;
805 pinctrl-names = "default";
806 #pwm-cells = <3>;
811 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
814 clock-names = "pwm", "pclk";
815 pinctrl-0 = <&pwm2m0_pins>;
816 pinctrl-names = "default";
817 #pwm-cells = <3>;
822 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
825 clock-names = "pwm", "pclk";
826 pinctrl-0 = <&pwm3m0_pins>;
827 pinctrl-names = "default";
828 #pwm-cells = <3>;
832 pmu: power-management@fd8d8000 {
833 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
836 power: power-controller {
837 compatible = "rockchip,rk3588-power-controller";
838 #address-cells = <1>;
839 #power-domain-cells = <1>;
840 #size-cells = <0>;
844 power-domain@RK3588_PD_NPU {
846 #power-domain-cells = <0>;
847 #address-cells = <1>;
848 #size-cells = <0>;
850 power-domain@RK3588_PD_NPUTOP {
859 #power-domain-cells = <0>;
860 #address-cells = <1>;
861 #size-cells = <0>;
863 power-domain@RK3588_PD_NPU1 {
869 #power-domain-cells = <0>;
871 power-domain@RK3588_PD_NPU2 {
877 #power-domain-cells = <0>;
882 pd_gpu: power-domain@RK3588_PD_GPU {
891 #power-domain-cells = <0>;
894 power-domain@RK3588_PD_VCODEC {
896 #address-cells = <1>;
897 #size-cells = <0>;
898 #power-domain-cells = <0>;
900 power-domain@RK3588_PD_RKVDEC0 {
908 #power-domain-cells = <0>;
910 power-domain@RK3588_PD_RKVDEC1 {
917 #power-domain-cells = <0>;
919 power-domain@RK3588_PD_VENC0 {
926 #address-cells = <1>;
927 #size-cells = <0>;
928 #power-domain-cells = <0>;
930 power-domain@RK3588_PD_VENC1 {
939 #power-domain-cells = <0>;
944 power-domain@RK3588_PD_VDPU {
972 #address-cells = <1>;
973 #size-cells = <0>;
974 #power-domain-cells = <0>;
977 power-domain@RK3588_PD_AV1 {
983 #power-domain-cells = <0>;
985 power-domain@RK3588_PD_RKVDEC0 {
992 #power-domain-cells = <0>;
994 power-domain@RK3588_PD_RKVDEC1 {
1000 #power-domain-cells = <0>;
1002 power-domain@RK3588_PD_RGA30 {
1007 #power-domain-cells = <0>;
1010 power-domain@RK3588_PD_VOP {
1017 #address-cells = <1>;
1018 #size-cells = <0>;
1019 #power-domain-cells = <0>;
1021 power-domain@RK3588_PD_VO0 {
1031 #power-domain-cells = <0>;
1034 power-domain@RK3588_PD_VO1 {
1045 #power-domain-cells = <0>;
1047 power-domain@RK3588_PD_VI {
1059 #address-cells = <1>;
1060 #size-cells = <0>;
1061 #power-domain-cells = <0>;
1063 power-domain@RK3588_PD_ISP1 {
1071 #power-domain-cells = <0>;
1073 power-domain@RK3588_PD_FEC {
1082 #power-domain-cells = <0>;
1085 power-domain@RK3588_PD_RGA31 {
1090 #power-domain-cells = <0>;
1092 power-domain@RK3588_PD_USB {
1106 #power-domain-cells = <0>;
1108 power-domain@RK3588_PD_GMAC {
1113 #power-domain-cells = <0>;
1115 power-domain@RK3588_PD_PCIE {
1120 #power-domain-cells = <0>;
1122 power-domain@RK3588_PD_SDIO {
1127 #power-domain-cells = <0>;
1129 power-domain@RK3588_PD_AUDIO {
1133 #power-domain-cells = <0>;
1135 power-domain@RK3588_PD_SDMMC {
1138 #power-domain-cells = <0>;
1143 vpu121: video-codec@fdb50000 {
1144 compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu";
1147 interrupt-names = "vdpu";
1149 clock-names = "aclk", "hclk";
1151 power-domains = <&power RK3588_PD_VDPU>;
1155 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1158 clock-names = "aclk", "iface";
1160 power-domains = <&power RK3588_PD_VDPU>;
1161 #iommu-cells = <0>;
1165 compatible = "rockchip,rk3588-rga", "rockchip,rk3288-rga";
1169 clock-names = "aclk", "hclk", "sclk";
1171 reset-names = "core", "axi", "ahb";
1172 power-domains = <&power RK3588_PD_VDPU>;
1175 vepu121_0: video-codec@fdba0000 {
1176 compatible = "rockchip,rk3588-vepu121";
1180 clock-names = "aclk", "hclk";
1182 power-domains = <&power RK3588_PD_VDPU>;
1186 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1190 clock-names = "aclk", "iface";
1191 power-domains = <&power RK3588_PD_VDPU>;
1192 #iommu-cells = <0>;
1195 vepu121_1: video-codec@fdba4000 {
1196 compatible = "rockchip,rk3588-vepu121";
1200 clock-names = "aclk", "hclk";
1202 power-domains = <&power RK3588_PD_VDPU>;
1206 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1210 clock-names = "aclk", "iface";
1211 power-domains = <&power RK3588_PD_VDPU>;
1212 #iommu-cells = <0>;
1215 vepu121_2: video-codec@fdba8000 {
1216 compatible = "rockchip,rk3588-vepu121";
1220 clock-names = "aclk", "hclk";
1222 power-domains = <&power RK3588_PD_VDPU>;
1226 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1230 clock-names = "aclk", "iface";
1231 power-domains = <&power RK3588_PD_VDPU>;
1232 #iommu-cells = <0>;
1235 vepu121_3: video-codec@fdbac000 {
1236 compatible = "rockchip,rk3588-vepu121";
1240 clock-names = "aclk", "hclk";
1242 power-domains = <&power RK3588_PD_VDPU>;
1246 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1250 clock-names = "aclk", "iface";
1251 power-domains = <&power RK3588_PD_VDPU>;
1252 #iommu-cells = <0>;
1255 av1d: video-codec@fdc70000 {
1256 compatible = "rockchip,rk3588-av1-vpu";
1259 interrupt-names = "vdpu";
1260 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
1261 assigned-clock-rates = <400000000>, <400000000>;
1263 clock-names = "aclk", "hclk";
1264 power-domains = <&power RK3588_PD_AV1>;
1269 compatible = "rockchip,rk3588-vop";
1271 reg-names = "vop", "gamma-lut";
1281 clock-names = "aclk",
1290 power-domains = <&power RK3588_PD_VOP>;
1292 rockchip,vop-grf = <&vop_grf>;
1293 rockchip,vo1-grf = <&vo1_grf>;
1298 #address-cells = <1>;
1299 #size-cells = <0>;
1302 #address-cells = <1>;
1303 #size-cells = <0>;
1308 #address-cells = <1>;
1309 #size-cells = <0>;
1314 #address-cells = <1>;
1315 #size-cells = <0>;
1320 #address-cells = <1>;
1321 #size-cells = <0>;
1328 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1332 clock-names = "aclk", "iface";
1333 #iommu-cells = <0>;
1334 power-domains = <&power RK3588_PD_VOP>;
1338 spdif_tx2: spdif-tx@fddb0000 {
1339 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
1341 assigned-clock-parents = <&cru PLL_AUPLL>;
1342 assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>;
1343 clock-names = "mclk", "hclk";
1345 dma-names = "tx";
1348 power-domains = <&power RK3588_PD_VO0>;
1349 #sound-dai-cells = <0>;
1354 compatible = "rockchip,rk3588-i2s-tdm";
1358 clock-names = "mclk_tx", "mclk_rx", "hclk";
1359 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
1360 assigned-clock-parents = <&cru PLL_AUPLL>;
1362 dma-names = "tx";
1363 power-domains = <&power RK3588_PD_VO0>;
1365 reset-names = "tx-m";
1366 #sound-dai-cells = <0>;
1370 spdif_tx3: spdif-tx@fdde0000 {
1371 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
1373 assigned-clock-parents = <&cru PLL_AUPLL>;
1374 assigned-clocks = <&cru CLK_SPDIF3_SRC>;
1375 clock-names = "mclk", "hclk";
1377 dma-names = "tx";
1380 power-domains = <&power RK3588_PD_VO1>;
1381 #sound-dai-cells = <0>;
1386 compatible = "rockchip,rk3588-i2s-tdm";
1390 clock-names = "mclk_tx", "mclk_rx", "hclk";
1391 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
1392 assigned-clock-parents = <&cru PLL_AUPLL>;
1394 dma-names = "tx";
1395 power-domains = <&power RK3588_PD_VO1>;
1397 reset-names = "tx-m";
1398 #sound-dai-cells = <0>;
1403 compatible = "rockchip,rk3588-i2s-tdm";
1407 clock-names = "mclk_tx", "mclk_rx", "hclk";
1408 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
1409 assigned-clock-parents = <&cru PLL_AUPLL>;
1411 dma-names = "rx";
1412 power-domains = <&power RK3588_PD_VO1>;
1414 reset-names = "rx-m";
1415 #sound-dai-cells = <0>;
1420 compatible = "rockchip,rk3588-mipi-dsi2";
1424 clock-names = "pclk", "sys";
1426 reset-names = "apb";
1427 power-domains = <&power RK3588_PD_VOP>;
1429 phy-names = "dcphy";
1434 #address-cells = <1>;
1435 #size-cells = <0>;
1448 compatible = "rockchip,rk3588-mipi-dsi2";
1452 clock-names = "pclk", "sys";
1454 reset-names = "apb";
1455 power-domains = <&power RK3588_PD_VOP>;
1457 phy-names = "dcphy";
1462 #address-cells = <1>;
1463 #size-cells = <0>;
1476 compatible = "rockchip,rk3588-dw-hdmi-qp";
1484 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
1490 interrupt-names = "avp", "cec", "earc", "main", "hpd";
1492 pinctrl-names = "default";
1493 pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
1495 power-domains = <&power RK3588_PD_VO1>;
1497 reset-names = "ref", "hdp";
1499 rockchip,vo-grf = <&vo1_grf>;
1500 #sound-dai-cells = <0>;
1504 #address-cells = <1>;
1505 #size-cells = <0>;
1518 compatible = "rockchip,rk3588-edp";
1521 clock-names = "dp", "pclk";
1524 phy-names = "dp";
1525 power-domains = <&power RK3588_PD_VO1>;
1527 reset-names = "dp", "apb";
1532 #address-cells = <1>;
1533 #size-cells = <0>;
1546 compatible = "rockchip,rk3588-qos", "syscon";
1551 compatible = "rockchip,rk3588-qos", "syscon";
1556 compatible = "rockchip,rk3588-qos", "syscon";
1561 compatible = "rockchip,rk3588-qos", "syscon";
1566 compatible = "rockchip,rk3588-qos", "syscon";
1571 compatible = "rockchip,rk3588-qos", "syscon";
1576 compatible = "rockchip,rk3588-qos", "syscon";
1581 compatible = "rockchip,rk3588-qos", "syscon";
1586 compatible = "rockchip,rk3588-qos", "syscon";
1591 compatible = "rockchip,rk3588-qos", "syscon";
1596 compatible = "rockchip,rk3588-qos", "syscon";
1601 compatible = "rockchip,rk3588-qos", "syscon";
1606 compatible = "rockchip,rk3588-qos", "syscon";
1611 compatible = "rockchip,rk3588-qos", "syscon";
1616 compatible = "rockchip,rk3588-qos", "syscon";
1621 compatible = "rockchip,rk3588-qos", "syscon";
1626 compatible = "rockchip,rk3588-qos", "syscon";
1631 compatible = "rockchip,rk3588-qos", "syscon";
1636 compatible = "rockchip,rk3588-qos", "syscon";
1641 compatible = "rockchip,rk3588-qos", "syscon";
1646 compatible = "rockchip,rk3588-qos", "syscon";
1651 compatible = "rockchip,rk3588-qos", "syscon";
1656 compatible = "rockchip,rk3588-qos", "syscon";
1661 compatible = "rockchip,rk3588-qos", "syscon";
1666 compatible = "rockchip,rk3588-qos", "syscon";
1671 compatible = "rockchip,rk3588-qos", "syscon";
1676 compatible = "rockchip,rk3588-qos", "syscon";
1681 compatible = "rockchip,rk3588-qos", "syscon";
1686 compatible = "rockchip,rk3588-qos", "syscon";
1691 compatible = "rockchip,rk3588-qos", "syscon";
1696 compatible = "rockchip,rk3588-qos", "syscon";
1701 compatible = "rockchip,rk3588-qos", "syscon";
1706 compatible = "rockchip,rk3588-qos", "syscon";
1711 compatible = "rockchip,rk3588-qos", "syscon";
1716 compatible = "rockchip,rk3588-qos", "syscon";
1721 compatible = "rockchip,rk3588-qos", "syscon";
1726 compatible = "rockchip,rk3588-qos", "syscon";
1731 compatible = "rockchip,rk3588-qos", "syscon";
1736 compatible = "rockchip,rk3588-qos", "syscon";
1741 compatible = "rockchip,rk3588-qos", "syscon";
1746 compatible = "rockchip,rk3588-qos", "syscon";
1751 compatible = "rockchip,rk3588-qos", "syscon";
1756 compatible = "rockchip,rk3588-qos", "syscon";
1761 compatible = "rockchip,rk3588-qos", "syscon";
1766 compatible = "rockchip,rk3588-qos", "syscon";
1771 compatible = "rockchip,rk3588-qos", "syscon";
1776 compatible = "rockchip,rk3588-qos", "syscon";
1781 compatible = "rockchip,rk3588-qos", "syscon";
1787 compatible = "rockchip,rk3588-dfi";
1796 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1797 bus-range = <0x30 0x3f>;
1801 clock-names = "aclk_mst", "aclk_slv",
1810 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1811 #interrupt-cells = <1>;
1812 interrupt-map-mask = <0 0 0 7>;
1813 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
1817 linux,pci-domain = <3>;
1818 max-link-speed = <2>;
1819 msi-map = <0x3000 &its0 0x3000 0x1000>;
1820 iommu-map = <0x3000 &mmu600_pcie 0x3000 0x1000>;
1821 num-lanes = <1>;
1823 phy-names = "pcie-phy";
1824 power-domains = <&power RK3588_PD_PCIE>;
1831 reg-names = "dbi", "apb", "config";
1833 reset-names = "pwr", "pipe";
1834 #address-cells = <3>;
1835 #size-cells = <2>;
1838 pcie2x1l1_intc: legacy-interrupt-controller {
1839 interrupt-controller;
1840 #address-cells = <0>;
1841 #interrupt-cells = <1>;
1842 interrupt-parent = <&gic>;
1848 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1849 bus-range = <0x40 0x4f>;
1853 clock-names = "aclk_mst", "aclk_slv",
1862 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1863 #interrupt-cells = <1>;
1864 interrupt-map-mask = <0 0 0 7>;
1865 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
1869 linux,pci-domain = <4>;
1870 max-link-speed = <2>;
1871 msi-map = <0x4000 &its0 0x4000 0x1000>;
1872 iommu-map = <0x4000 &mmu600_pcie 0x4000 0x1000>;
1873 num-lanes = <1>;
1875 phy-names = "pcie-phy";
1876 power-domains = <&power RK3588_PD_PCIE>;
1883 reg-names = "dbi", "apb", "config";
1885 reset-names = "pwr", "pipe";
1886 #address-cells = <3>;
1887 #size-cells = <2>;
1890 pcie2x1l2_intc: legacy-interrupt-controller {
1891 interrupt-controller;
1892 #address-cells = <0>;
1893 #interrupt-cells = <1>;
1894 interrupt-parent = <&gic>;
1900 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
1904 interrupt-names = "macirq", "eth_wake_irq";
1908 clock-names = "stmmaceth", "clk_mac_ref",
1911 power-domains = <&power RK3588_PD_GMAC>;
1913 reset-names = "stmmaceth";
1915 rockchip,php-grf = <&php_grf>;
1916 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1917 snps,mixed-burst;
1918 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1919 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1924 compatible = "snps,dwmac-mdio";
1925 #address-cells = <0x1>;
1926 #size-cells = <0x0>;
1929 gmac1_stmmac_axi_setup: stmmac-axi-config {
1935 gmac1_mtl_rx_setup: rx-queues-config {
1936 snps,rx-queues-to-use = <2>;
1941 gmac1_mtl_tx_setup: tx-queues-config {
1942 snps,tx-queues-to-use = <2>;
1949 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1955 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1956 ports-implemented = <0x1>;
1957 #address-cells = <1>;
1958 #size-cells = <0>;
1961 sata-port@0 {
1963 hba-port-cap = <HBA_PORT_FBSCP>;
1965 phy-names = "sata-phy";
1966 snps,rx-ts-max = <32>;
1967 snps,tx-ts-max = <32>;
1972 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1978 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1979 ports-implemented = <0x1>;
1980 #address-cells = <1>;
1981 #size-cells = <0>;
1984 sata-port@0 {
1986 hba-port-cap = <HBA_PORT_FBSCP>;
1988 phy-names = "sata-phy";
1989 snps,rx-ts-max = <32>;
1990 snps,tx-ts-max = <32>;
1999 clock-names = "clk_sfc", "hclk_sfc";
2000 #address-cells = <1>;
2001 #size-cells = <0>;
2006 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
2011 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
2012 fifo-depth = <0x100>;
2013 max-frequency = <200000000>;
2014 pinctrl-names = "default";
2015 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
2016 power-domains = <&power RK3588_PD_SDMMC>;
2021 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
2026 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
2027 fifo-depth = <0x100>;
2028 max-frequency = <200000000>;
2029 pinctrl-names = "default";
2030 pinctrl-0 = <&sdiom1_pins>;
2031 power-domains = <&power RK3588_PD_SDIO>;
2036 compatible = "rockchip,rk3588-dwcmshc";
2039 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
2040 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
2044 clock-names = "core", "bus", "axi", "block", "timer";
2045 max-frequency = <200000000>;
2046 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
2048 pinctrl-names = "default";
2052 reset-names = "core", "bus", "axi", "block", "timer";
2057 compatible = "rockchip,rk3588-rng";
2065 compatible = "rockchip,rk3588-i2s-tdm";
2069 clock-names = "mclk_tx", "mclk_rx", "hclk";
2070 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
2071 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
2073 dma-names = "tx", "rx";
2074 power-domains = <&power RK3588_PD_AUDIO>;
2076 reset-names = "tx-m", "rx-m";
2077 rockchip,trcm-sync-tx-only;
2078 pinctrl-names = "default";
2079 pinctrl-0 = <&i2s0_lrck
2089 #sound-dai-cells = <0>;
2094 compatible = "rockchip,rk3588-i2s-tdm";
2098 clock-names = "mclk_tx", "mclk_rx", "hclk";
2100 dma-names = "tx", "rx";
2102 reset-names = "tx-m", "rx-m";
2103 rockchip,trcm-sync-tx-only;
2104 pinctrl-names = "default";
2105 pinctrl-0 = <&i2s1m0_lrck
2115 #sound-dai-cells = <0>;
2120 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
2124 clock-names = "i2s_clk", "i2s_hclk";
2125 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
2126 assigned-clock-parents = <&cru PLL_AUPLL>;
2128 dma-names = "tx", "rx";
2129 power-domains = <&power RK3588_PD_AUDIO>;
2130 pinctrl-names = "default";
2131 pinctrl-0 = <&i2s2m1_lrck
2135 #sound-dai-cells = <0>;
2140 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
2144 clock-names = "i2s_clk", "i2s_hclk";
2145 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
2146 assigned-clock-parents = <&cru PLL_AUPLL>;
2148 dma-names = "tx", "rx";
2149 power-domains = <&power RK3588_PD_AUDIO>;
2150 pinctrl-names = "default";
2151 pinctrl-0 = <&i2s3_lrck
2155 #sound-dai-cells = <0>;
2159 spdif_tx0: spdif-tx@fe4e0000 {
2160 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
2162 assigned-clock-parents = <&cru PLL_AUPLL>;
2163 assigned-clocks = <&cru CLK_SPDIF0_SRC>;
2164 clock-names = "mclk", "hclk";
2166 dma-names = "tx";
2169 pinctrl-0 = <&spdif0m0_tx>;
2170 pinctrl-names = "default";
2171 power-domains = <&power RK3588_PD_AUDIO>;
2172 #sound-dai-cells = <0>;
2176 spdif_tx1: spdif-tx@fe4f0000 {
2177 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
2179 assigned-clock-parents = <&cru PLL_AUPLL>;
2180 assigned-clocks = <&cru CLK_SPDIF1_SRC>;
2181 clock-names = "mclk", "hclk";
2183 dma-names = "tx";
2186 pinctrl-0 = <&spdif1m0_tx>;
2187 pinctrl-names = "default";
2188 power-domains = <&power RK3588_PD_AUDIO>;
2189 #sound-dai-cells = <0>;
2193 gic: interrupt-controller@fe600000 {
2194 compatible = "arm,gic-v3";
2198 interrupt-controller;
2199 dma-noncoherent;
2200 mbi-alias = <0x0 0xfe610000>;
2201 mbi-ranges = <424 56>;
2202 msi-controller;
2204 #address-cells = <2>;
2205 #interrupt-cells = <4>;
2206 #size-cells = <2>;
2208 its0: msi-controller@fe640000 {
2209 compatible = "arm,gic-v3-its";
2211 dma-noncoherent;
2212 msi-controller;
2213 #msi-cells = <1>;
2216 its1: msi-controller@fe660000 {
2217 compatible = "arm,gic-v3-its";
2219 dma-noncoherent;
2220 msi-controller;
2221 #msi-cells = <1>;
2224 ppi-partitions {
2225 ppi_partition0: interrupt-partition-0 {
2229 ppi_partition1: interrupt-partition-1 {
2235 dmac0: dma-controller@fea10000 {
2240 arm,pl330-periph-burst;
2242 clock-names = "apb_pclk";
2243 #dma-cells = <1>;
2246 dmac1: dma-controller@fea30000 {
2251 arm,pl330-periph-burst;
2253 clock-names = "apb_pclk";
2254 #dma-cells = <1>;
2258 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2261 clock-names = "i2c", "pclk";
2263 pinctrl-0 = <&i2c1m0_xfer>;
2264 pinctrl-names = "default";
2265 #address-cells = <1>;
2266 #size-cells = <0>;
2271 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2274 clock-names = "i2c", "pclk";
2276 pinctrl-0 = <&i2c2m0_xfer>;
2277 pinctrl-names = "default";
2278 #address-cells = <1>;
2279 #size-cells = <0>;
2284 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2287 clock-names = "i2c", "pclk";
2289 pinctrl-0 = <&i2c3m0_xfer>;
2290 pinctrl-names = "default";
2291 #address-cells = <1>;
2292 #size-cells = <0>;
2297 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2300 clock-names = "i2c", "pclk";
2302 pinctrl-0 = <&i2c4m0_xfer>;
2303 pinctrl-names = "default";
2304 #address-cells = <1>;
2305 #size-cells = <0>;
2310 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2313 clock-names = "i2c", "pclk";
2315 pinctrl-0 = <&i2c5m0_xfer>;
2316 pinctrl-names = "default";
2317 #address-cells = <1>;
2318 #size-cells = <0>;
2323 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
2327 clock-names = "pclk", "timer";
2331 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
2334 clock-names = "tclk", "pclk";
2339 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2343 clock-names = "spiclk", "apb_pclk";
2345 dma-names = "tx", "rx";
2346 num-cs = <2>;
2347 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
2348 pinctrl-names = "default";
2349 #address-cells = <1>;
2350 #size-cells = <0>;
2355 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2359 clock-names = "spiclk", "apb_pclk";
2361 dma-names = "tx", "rx";
2362 num-cs = <2>;
2363 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
2364 pinctrl-names = "default";
2365 #address-cells = <1>;
2366 #size-cells = <0>;
2371 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2375 clock-names = "spiclk", "apb_pclk";
2377 dma-names = "tx", "rx";
2378 num-cs = <2>;
2379 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
2380 pinctrl-names = "default";
2381 #address-cells = <1>;
2382 #size-cells = <0>;
2387 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2391 clock-names = "spiclk", "apb_pclk";
2393 dma-names = "tx", "rx";
2394 num-cs = <2>;
2395 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
2396 pinctrl-names = "default";
2397 #address-cells = <1>;
2398 #size-cells = <0>;
2403 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2407 clock-names = "baudclk", "apb_pclk";
2409 dma-names = "tx", "rx";
2410 pinctrl-0 = <&uart1m1_xfer>;
2411 pinctrl-names = "default";
2412 reg-io-width = <4>;
2413 reg-shift = <2>;
2418 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2422 clock-names = "baudclk", "apb_pclk";
2424 dma-names = "tx", "rx";
2425 pinctrl-0 = <&uart2m1_xfer>;
2426 pinctrl-names = "default";
2427 reg-io-width = <4>;
2428 reg-shift = <2>;
2433 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2437 clock-names = "baudclk", "apb_pclk";
2439 dma-names = "tx", "rx";
2440 pinctrl-0 = <&uart3m1_xfer>;
2441 pinctrl-names = "default";
2442 reg-io-width = <4>;
2443 reg-shift = <2>;
2448 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2452 clock-names = "baudclk", "apb_pclk";
2454 dma-names = "tx", "rx";
2455 pinctrl-0 = <&uart4m1_xfer>;
2456 pinctrl-names = "default";
2457 reg-io-width = <4>;
2458 reg-shift = <2>;
2463 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2467 clock-names = "baudclk", "apb_pclk";
2469 dma-names = "tx", "rx";
2470 pinctrl-0 = <&uart5m1_xfer>;
2471 pinctrl-names = "default";
2472 reg-io-width = <4>;
2473 reg-shift = <2>;
2478 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2482 clock-names = "baudclk", "apb_pclk";
2484 dma-names = "tx", "rx";
2485 pinctrl-0 = <&uart6m1_xfer>;
2486 pinctrl-names = "default";
2487 reg-io-width = <4>;
2488 reg-shift = <2>;
2493 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2497 clock-names = "baudclk", "apb_pclk";
2499 dma-names = "tx", "rx";
2500 pinctrl-0 = <&uart7m1_xfer>;
2501 pinctrl-names = "default";
2502 reg-io-width = <4>;
2503 reg-shift = <2>;
2508 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2512 clock-names = "baudclk", "apb_pclk";
2514 dma-names = "tx", "rx";
2515 pinctrl-0 = <&uart8m1_xfer>;
2516 pinctrl-names = "default";
2517 reg-io-width = <4>;
2518 reg-shift = <2>;
2523 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2527 clock-names = "baudclk", "apb_pclk";
2529 dma-names = "tx", "rx";
2530 pinctrl-0 = <&uart9m1_xfer>;
2531 pinctrl-names = "default";
2532 reg-io-width = <4>;
2533 reg-shift = <2>;
2538 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2541 clock-names = "pwm", "pclk";
2542 pinctrl-0 = <&pwm4m0_pins>;
2543 pinctrl-names = "default";
2544 #pwm-cells = <3>;
2549 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2552 clock-names = "pwm", "pclk";
2553 pinctrl-0 = <&pwm5m0_pins>;
2554 pinctrl-names = "default";
2555 #pwm-cells = <3>;
2560 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2563 clock-names = "pwm", "pclk";
2564 pinctrl-0 = <&pwm6m0_pins>;
2565 pinctrl-names = "default";
2566 #pwm-cells = <3>;
2571 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2574 clock-names = "pwm", "pclk";
2575 pinctrl-0 = <&pwm7m0_pins>;
2576 pinctrl-names = "default";
2577 #pwm-cells = <3>;
2582 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2585 clock-names = "pwm", "pclk";
2586 pinctrl-0 = <&pwm8m0_pins>;
2587 pinctrl-names = "default";
2588 #pwm-cells = <3>;
2593 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2596 clock-names = "pwm", "pclk";
2597 pinctrl-0 = <&pwm9m0_pins>;
2598 pinctrl-names = "default";
2599 #pwm-cells = <3>;
2604 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2607 clock-names = "pwm", "pclk";
2608 pinctrl-0 = <&pwm10m0_pins>;
2609 pinctrl-names = "default";
2610 #pwm-cells = <3>;
2615 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2618 clock-names = "pwm", "pclk";
2619 pinctrl-0 = <&pwm11m0_pins>;
2620 pinctrl-names = "default";
2621 #pwm-cells = <3>;
2626 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2629 clock-names = "pwm", "pclk";
2630 pinctrl-0 = <&pwm12m0_pins>;
2631 pinctrl-names = "default";
2632 #pwm-cells = <3>;
2637 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2640 clock-names = "pwm", "pclk";
2641 pinctrl-0 = <&pwm13m0_pins>;
2642 pinctrl-names = "default";
2643 #pwm-cells = <3>;
2648 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2651 clock-names = "pwm", "pclk";
2652 pinctrl-0 = <&pwm14m0_pins>;
2653 pinctrl-names = "default";
2654 #pwm-cells = <3>;
2659 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2662 clock-names = "pwm", "pclk";
2663 pinctrl-0 = <&pwm15m0_pins>;
2664 pinctrl-names = "default";
2665 #pwm-cells = <3>;
2669 thermal_zones: thermal-zones {
2670 /* sensor near the center of the SoC */
2671 package_thermal: package-thermal {
2672 polling-delay-passive = <0>;
2673 polling-delay = <0>;
2674 thermal-sensors = <&tsadc 0>;
2677 package_crit: package-crit {
2686 bigcore0_thermal: bigcore0-thermal {
2687 polling-delay-passive = <100>;
2688 polling-delay = <0>;
2689 thermal-sensors = <&tsadc 1>;
2692 bigcore0_alert: bigcore0-alert {
2698 bigcore0_crit: bigcore0-crit {
2705 cooling-maps {
2708 cooling-device =
2716 bigcore2_thermal: bigcore2-thermal {
2717 polling-delay-passive = <100>;
2718 polling-delay = <0>;
2719 thermal-sensors = <&tsadc 2>;
2722 bigcore2_alert: bigcore2-alert {
2728 bigcore2_crit: bigcore2-crit {
2735 cooling-maps {
2738 cooling-device =
2746 little_core_thermal: littlecore-thermal {
2747 polling-delay-passive = <100>;
2748 polling-delay = <0>;
2749 thermal-sensors = <&tsadc 3>;
2752 littlecore_alert: littlecore-alert {
2758 littlecore_crit: littlecore-crit {
2765 cooling-maps {
2768 cooling-device =
2778 center_thermal: center-thermal {
2779 polling-delay-passive = <0>;
2780 polling-delay = <0>;
2781 thermal-sensors = <&tsadc 4>;
2784 center_crit: center-crit {
2792 gpu_thermal: gpu-thermal {
2793 polling-delay-passive = <100>;
2794 polling-delay = <0>;
2795 thermal-sensors = <&tsadc 5>;
2798 gpu_alert: gpu-alert {
2804 gpu_crit: gpu-crit {
2811 cooling-maps {
2814 cooling-device =
2820 npu_thermal: npu-thermal {
2821 polling-delay-passive = <0>;
2822 polling-delay = <0>;
2823 thermal-sensors = <&tsadc 6>;
2826 npu_crit: npu-crit {
2836 compatible = "rockchip,rk3588-tsadc";
2840 clock-names = "tsadc", "apb_pclk";
2841 assigned-clocks = <&cru CLK_TSADC>;
2842 assigned-clock-rates = <2000000>;
2844 reset-names = "tsadc-apb", "tsadc";
2845 rockchip,hw-tshut-temp = <120000>;
2846 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2847 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2848 pinctrl-0 = <&tsadc_shut_org>;
2849 pinctrl-1 = <&tsadc_gpio_func>;
2850 pinctrl-names = "default", "sleep";
2851 #thermal-sensor-cells = <1>;
2856 compatible = "rockchip,rk3588-saradc";
2859 #io-channel-cells = <1>;
2861 clock-names = "saradc", "apb_pclk";
2863 reset-names = "saradc-apb";
2868 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2871 clock-names = "i2c", "pclk";
2873 pinctrl-0 = <&i2c6m0_xfer>;
2874 pinctrl-names = "default";
2875 #address-cells = <1>;
2876 #size-cells = <0>;
2881 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2884 clock-names = "i2c", "pclk";
2886 pinctrl-0 = <&i2c7m0_xfer>;
2887 pinctrl-names = "default";
2888 #address-cells = <1>;
2889 #size-cells = <0>;
2894 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2897 clock-names = "i2c", "pclk";
2899 pinctrl-0 = <&i2c8m0_xfer>;
2900 pinctrl-names = "default";
2901 #address-cells = <1>;
2902 #size-cells = <0>;
2907 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2911 clock-names = "spiclk", "apb_pclk";
2913 dma-names = "tx", "rx";
2914 num-cs = <2>;
2915 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
2916 pinctrl-names = "default";
2917 #address-cells = <1>;
2918 #size-cells = <0>;
2923 compatible = "rockchip,rk3588-otp";
2927 clock-names = "otp", "apb_pclk", "phy", "arb";
2930 reset-names = "otp", "apb", "arb";
2931 #address-cells = <1>;
2932 #size-cells = <1>;
2934 cpu_code: cpu-code@2 {
2942 cpub0_leakage: cpu-leakage@17 {
2946 cpub1_leakage: cpu-leakage@18 {
2950 cpul_leakage: cpu-leakage@19 {
2954 log_leakage: log-leakage@1a {
2958 gpu_leakage: gpu-leakage@1b {
2962 otp_cpu_version: cpu-version@1c {
2967 npu_leakage: npu-leakage@28 {
2971 codec_leakage: codec-leakage@29 {
2976 dmac2: dma-controller@fed10000 {
2981 arm,pl330-periph-burst;
2983 clock-names = "apb_pclk";
2984 #dma-cells = <1>;
2988 compatible = "rockchip,rk3588-hdptx-phy";
2991 clock-names = "ref", "apb";
2992 #clock-cells = <0>;
2993 #phy-cells = <0>;
2998 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
3005 compatible = "rockchip,rk3588-usbdp-phy";
3007 #phy-cells = <1>;
3012 clock-names = "refclk", "immortal", "pclk", "utmi";
3018 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
3019 rockchip,u2phy-grf = <&usb2phy0_grf>;
3020 rockchip,usb-grf = <&usb_grf>;
3021 rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
3022 rockchip,vo-grf = <&vo0_grf>;
3027 compatible = "rockchip,rk3588-mipi-dcphy";
3032 clock-names = "pclk", "ref";
3037 reset-names = "m_phy", "apb", "grf", "s_phy";
3038 #phy-cells = <1>;
3043 compatible = "rockchip,rk3588-mipi-dcphy";
3048 clock-names = "pclk", "ref";
3053 reset-names = "m_phy", "apb", "grf", "s_phy";
3054 #phy-cells = <1>;
3059 compatible = "rockchip,rk3588-naneng-combphy";
3063 clock-names = "ref", "apb", "pipe";
3064 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
3065 assigned-clock-rates = <100000000>;
3066 #phy-cells = <1>;
3068 reset-names = "phy", "apb";
3069 rockchip,pipe-grf = <&php_grf>;
3070 rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
3075 compatible = "rockchip,rk3588-naneng-combphy";
3079 clock-names = "ref", "apb", "pipe";
3080 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
3081 assigned-clock-rates = <100000000>;
3082 #phy-cells = <1>;
3084 reset-names = "phy", "apb";
3085 rockchip,pipe-grf = <&php_grf>;
3086 rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
3091 compatible = "mmio-sram";
3094 #address-cells = <1>;
3095 #size-cells = <1>;
3099 compatible = "rockchip,rk3588-pinctrl";
3102 #address-cells = <2>;
3103 #size-cells = <2>;
3106 compatible = "rockchip,gpio-bank";
3110 gpio-controller;
3111 gpio-ranges = <&pinctrl 0 0 32>;
3112 interrupt-controller;
3113 #gpio-cells = <2>;
3114 #interrupt-cells = <2>;
3118 compatible = "rockchip,gpio-bank";
3122 gpio-controller;
3123 gpio-ranges = <&pinctrl 0 32 32>;
3124 interrupt-controller;
3125 #gpio-cells = <2>;
3126 #interrupt-cells = <2>;
3130 compatible = "rockchip,gpio-bank";
3134 gpio-controller;
3135 gpio-ranges = <&pinctrl 0 64 32>;
3136 interrupt-controller;
3137 #gpio-cells = <2>;
3138 #interrupt-cells = <2>;
3142 compatible = "rockchip,gpio-bank";
3146 gpio-controller;
3147 gpio-ranges = <&pinctrl 0 96 32>;
3148 interrupt-controller;
3149 #gpio-cells = <2>;
3150 #interrupt-cells = <2>;
3154 compatible = "rockchip,gpio-bank";
3158 gpio-controller;
3159 gpio-ranges = <&pinctrl 0 128 32>;
3160 interrupt-controller;
3161 #gpio-cells = <2>;
3162 #interrupt-cells = <2>;
3167 #include "rk3588-base-pinctrl.dtsi"