Lines Matching +full:0 +full:xfeb90000
56 #size-cells = <0>;
91 cpu_l0: cpu@0 {
94 reg = <0x0>;
115 reg = <0x100>;
134 reg = <0x200>;
153 reg = <0x300>;
172 reg = <0x400>;
193 reg = <0x500>;
212 reg = <0x600>;
233 reg = <0x700>;
254 arm,psci-suspend-param = <0x0010000>;
368 arm,smc-id = <0x82000010>;
371 #size-cells = <0>;
374 reg = <0x14>;
379 reg = <0x16>;
400 spll: clock-0 {
404 #clock-cells = <0>;
409 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
410 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
411 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
412 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
413 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
421 #clock-cells = <0>;
428 #clock-cells = <0>;
433 reg = <0x0 0x0010f000 0x0 0x100>;
434 ranges = <0 0x0 0x0010f000 0x100>;
438 scmi_shmem: sram@0 {
440 reg = <0x0 0x100>;
446 reg = <0x0 0xfb000000 0x0 0x200000>;
454 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
455 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
456 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
464 reg = <0x0 0xfc000000 0x0 0x400000>;
465 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
486 reg = <0x0 0xfc800000 0x0 0x40000>;
487 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
497 reg = <0x0 0xfc840000 0x0 0x40000>;
498 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
508 reg = <0x0 0xfc880000 0x0 0x40000>;
509 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
519 reg = <0x0 0xfc8c0000 0x0 0x40000>;
520 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
530 reg = <0x0 0xfcd00000 0x0 0x400000>;
531 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
551 reg = <0x0 0xfc900000 0x0 0x200000>;
552 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>,
553 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>,
554 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
555 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
562 reg = <0x0 0xfcb00000 0x0 0x200000>;
563 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>,
564 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
565 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>,
566 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
574 reg = <0x0 0xfd58a000 0x0 0x10000>;
579 reg = <0x0 0xfd58c000 0x0 0x1000>;
584 reg = <0x0 0xfd5a4000 0x0 0x2000>;
589 reg = <0x0 0xfd5a6000 0x0 0x2000>;
595 reg = <0x0 0xfd5a8000 0x0 0x4000>;
601 reg = <0x0 0xfd5ac000 0x0 0x4000>;
606 reg = <0x0 0xfd5b0000 0x0 0x1000>;
611 reg = <0x0 0xfd5bc000 0x0 0x100>;
616 reg = <0x0 0xfd5c4000 0x0 0x100>;
621 reg = <0x0 0xfd5c8000 0x0 0x4000>;
626 reg = <0x0 0xfd5d0000 0x0 0x4000>;
630 u2phy0: usb2phy@0 {
632 reg = <0x0 0x10>;
633 #clock-cells = <0>;
637 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
643 #phy-cells = <0>;
651 reg = <0x0 0xfd5d8000 0x0 0x4000>;
657 reg = <0x8000 0x10>;
658 #clock-cells = <0>;
662 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
668 #phy-cells = <0>;
676 reg = <0x0 0xfd5dc000 0x0 0x4000>;
682 reg = <0xc000 0x10>;
683 #clock-cells = <0>;
687 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
693 #phy-cells = <0>;
701 reg = <0x0 0xfd5e0000 0x0 0x100>;
706 reg = <0x0 0xfd5f0000 0x0 0x10000>;
711 reg = <0x0 0xfd600000 0x0 0x100000>;
712 ranges = <0x0 0x0 0xfd600000 0x100000>;
719 reg = <0x0 0xfd7c0000 0x0 0x5c000>;
747 reg = <0x0 0xfd880000 0x0 0x1000>;
748 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;
751 pinctrl-0 = <&i2c0m0_xfer>;
754 #size-cells = <0>;
760 reg = <0x0 0xfd890000 0x0 0x100>;
761 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
766 pinctrl-0 = <&uart0m1_xfer>;
775 reg = <0x0 0xfd8b0000 0x0 0x10>;
778 pinctrl-0 = <&pwm0m0_pins>;
786 reg = <0x0 0xfd8b0010 0x0 0x10>;
789 pinctrl-0 = <&pwm1m0_pins>;
797 reg = <0x0 0xfd8b0020 0x0 0x10>;
800 pinctrl-0 = <&pwm2m0_pins>;
808 reg = <0x0 0xfd8b0030 0x0 0x10>;
811 pinctrl-0 = <&pwm3m0_pins>;
819 reg = <0x0 0xfd8d8000 0x0 0x400>;
825 #size-cells = <0>;
831 #power-domain-cells = <0>;
833 #size-cells = <0>;
844 #power-domain-cells = <0>;
846 #size-cells = <0>;
854 #power-domain-cells = <0>;
862 #power-domain-cells = <0>;
876 #power-domain-cells = <0>;
882 #size-cells = <0>;
883 #power-domain-cells = <0>;
893 #power-domain-cells = <0>;
902 #power-domain-cells = <0>;
912 #size-cells = <0>;
913 #power-domain-cells = <0>;
924 #power-domain-cells = <0>;
958 #size-cells = <0>;
959 #power-domain-cells = <0>;
968 #power-domain-cells = <0>;
977 #power-domain-cells = <0>;
985 #power-domain-cells = <0>;
992 #power-domain-cells = <0>;
1003 #size-cells = <0>;
1004 #power-domain-cells = <0>;
1016 #power-domain-cells = <0>;
1030 #power-domain-cells = <0>;
1045 #size-cells = <0>;
1046 #power-domain-cells = <0>;
1056 #power-domain-cells = <0>;
1067 #power-domain-cells = <0>;
1075 #power-domain-cells = <0>;
1091 #power-domain-cells = <0>;
1098 #power-domain-cells = <0>;
1105 #power-domain-cells = <0>;
1112 #power-domain-cells = <0>;
1118 #power-domain-cells = <0>;
1123 #power-domain-cells = <0>;
1130 reg = <0x0 0xfdb50000 0x0 0x800>;
1131 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1141 reg = <0x0 0xfdb50800 0x0 0x40>;
1142 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1146 #iommu-cells = <0>;
1151 reg = <0x0 0xfdb80000 0x0 0x180>;
1152 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1162 reg = <0x0 0xfdba0000 0x0 0x800>;
1163 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>;
1172 reg = <0x0 0xfdba0800 0x0 0x40>;
1173 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
1177 #iommu-cells = <0>;
1182 reg = <0x0 0xfdba4000 0x0 0x800>;
1183 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>;
1192 reg = <0x0 0xfdba4800 0x0 0x40>;
1193 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>;
1197 #iommu-cells = <0>;
1202 reg = <0x0 0xfdba8000 0x0 0x800>;
1203 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>;
1212 reg = <0x0 0xfdba8800 0x0 0x40>;
1213 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>;
1217 #iommu-cells = <0>;
1222 reg = <0x0 0xfdbac000 0x0 0x800>;
1223 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
1232 reg = <0x0 0xfdbac800 0x0 0x40>;
1233 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>;
1237 #iommu-cells = <0>;
1242 reg = <0x0 0xfdc70000 0x0 0x800>;
1243 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
1255 reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
1257 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
1282 #size-cells = <0>;
1284 vp0: port@0 {
1286 #size-cells = <0>;
1287 reg = <0>;
1292 #size-cells = <0>;
1298 #size-cells = <0>;
1304 #size-cells = <0>;
1312 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
1313 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
1316 #iommu-cells = <0>;
1323 reg = <0x0 0xfddc0000 0x0 0x1000>;
1324 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;
1329 dmas = <&dmac2 0>;
1334 #sound-dai-cells = <0>;
1340 reg = <0x0 0xfddf0000 0x0 0x1000>;
1341 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
1351 #sound-dai-cells = <0>;
1357 reg = <0x0 0xfddfc000 0x0 0x1000>;
1358 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
1368 #sound-dai-cells = <0>;
1374 reg = <0x0 0xfde80000 0x0 0x20000>;
1382 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
1383 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
1384 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
1385 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
1386 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
1390 pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
1401 #size-cells = <0>;
1403 hdmi0_in: port@0 {
1404 reg = <0>;
1415 reg = <0x0 0xfdf35000 0x0 0x20>;
1420 reg = <0x0 0xfdf35200 0x0 0x20>;
1425 reg = <0x0 0xfdf35400 0x0 0x20>;
1430 reg = <0x0 0xfdf35600 0x0 0x20>;
1435 reg = <0x0 0xfdf36000 0x0 0x20>;
1440 reg = <0x0 0xfdf39000 0x0 0x20>;
1445 reg = <0x0 0xfdf3d800 0x0 0x20>;
1450 reg = <0x0 0xfdf3e000 0x0 0x20>;
1455 reg = <0x0 0xfdf3e200 0x0 0x20>;
1460 reg = <0x0 0xfdf3e400 0x0 0x20>;
1465 reg = <0x0 0xfdf3e600 0x0 0x20>;
1470 reg = <0x0 0xfdf40000 0x0 0x20>;
1475 reg = <0x0 0xfdf40200 0x0 0x20>;
1480 reg = <0x0 0xfdf40400 0x0 0x20>;
1485 reg = <0x0 0xfdf40500 0x0 0x20>;
1490 reg = <0x0 0xfdf40600 0x0 0x20>;
1495 reg = <0x0 0xfdf40800 0x0 0x20>;
1500 reg = <0x0 0xfdf41000 0x0 0x20>;
1505 reg = <0x0 0xfdf41100 0x0 0x20>;
1510 reg = <0x0 0xfdf60000 0x0 0x20>;
1515 reg = <0x0 0xfdf60200 0x0 0x20>;
1520 reg = <0x0 0xfdf60400 0x0 0x20>;
1525 reg = <0x0 0xfdf61000 0x0 0x20>;
1530 reg = <0x0 0xfdf61200 0x0 0x20>;
1535 reg = <0x0 0xfdf61400 0x0 0x20>;
1540 reg = <0x0 0xfdf62000 0x0 0x20>;
1545 reg = <0x0 0xfdf63000 0x0 0x20>;
1550 reg = <0x0 0xfdf64000 0x0 0x20>;
1555 reg = <0x0 0xfdf66000 0x0 0x20>;
1560 reg = <0x0 0xfdf66200 0x0 0x20>;
1565 reg = <0x0 0xfdf66400 0x0 0x20>;
1570 reg = <0x0 0xfdf66600 0x0 0x20>;
1575 reg = <0x0 0xfdf66800 0x0 0x20>;
1580 reg = <0x0 0xfdf66a00 0x0 0x20>;
1585 reg = <0x0 0xfdf66c00 0x0 0x20>;
1590 reg = <0x0 0xfdf66e00 0x0 0x20>;
1595 reg = <0x0 0xfdf67000 0x0 0x20>;
1600 reg = <0x0 0xfdf67200 0x0 0x20>;
1605 reg = <0x0 0xfdf70000 0x0 0x20>;
1610 reg = <0x0 0xfdf71000 0x0 0x20>;
1615 reg = <0x0 0xfdf72000 0x0 0x20>;
1620 reg = <0x0 0xfdf72200 0x0 0x20>;
1625 reg = <0x0 0xfdf72400 0x0 0x20>;
1630 reg = <0x0 0xfdf80000 0x0 0x20>;
1635 reg = <0x0 0xfdf81000 0x0 0x20>;
1640 reg = <0x0 0xfdf81200 0x0 0x20>;
1645 reg = <0x0 0xfdf82000 0x0 0x20>;
1650 reg = <0x0 0xfdf82200 0x0 0x20>;
1654 reg = <0x00 0xfe060000 0x00 0x10000>;
1656 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
1657 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
1658 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
1659 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1665 bus-range = <0x30 0x3f>;
1673 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
1674 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
1675 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
1676 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
1677 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>;
1680 interrupt-map-mask = <0 0 0 7>;
1681 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
1682 <0 0 0 2 &pcie2x1l1_intc 1>,
1683 <0 0 0 3 &pcie2x1l1_intc 2>,
1684 <0 0 0 4 &pcie2x1l1_intc 3>;
1687 msi-map = <0x3000 &its0 0x3000 0x1000>;
1688 iommu-map = <0x3000 &mmu600_pcie 0x3000 0x1000>;
1693 ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
1694 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
1695 <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
1696 reg = <0xa 0x40c00000 0x0 0x00400000>,
1697 <0x0 0xfe180000 0x0 0x00010000>,
1698 <0x0 0xf3000000 0x0 0x00100000>;
1708 #address-cells = <0>;
1711 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>;
1717 bus-range = <0x40 0x4f>;
1725 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
1726 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
1727 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
1728 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
1729 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
1732 interrupt-map-mask = <0 0 0 7>;
1733 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
1734 <0 0 0 2 &pcie2x1l2_intc 1>,
1735 <0 0 0 3 &pcie2x1l2_intc 2>,
1736 <0 0 0 4 &pcie2x1l2_intc 3>;
1739 msi-map = <0x4000 &its0 0x4000 0x1000>;
1740 iommu-map = <0x4000 &mmu600_pcie 0x4000 0x1000>;
1745 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
1746 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
1747 <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
1748 reg = <0xa 0x41000000 0x0 0x00400000>,
1749 <0x0 0xfe190000 0x0 0x00010000>,
1750 <0x0 0xf4000000 0x0 0x00100000>;
1760 #address-cells = <0>;
1763 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
1769 reg = <0x0 0xfe1c0000 0x0 0x10000>;
1770 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
1771 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
1793 #address-cells = <0x1>;
1794 #size-cells = <0x0>;
1798 snps,blen = <0 0 0 0 16 8 4>;
1818 reg = <0 0xfe210000 0 0x1000>;
1819 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
1824 ports-implemented = <0x1>;
1826 #size-cells = <0>;
1829 sata-port@0 {
1830 reg = <0>;
1841 reg = <0 0xfe230000 0 0x1000>;
1842 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
1847 ports-implemented = <0x1>;
1849 #size-cells = <0>;
1852 sata-port@0 {
1853 reg = <0>;
1864 reg = <0x0 0xfe2b0000 0x0 0x4000>;
1865 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
1869 #size-cells = <0>;
1875 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1876 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
1880 fifo-depth = <0x100>;
1883 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1890 reg = <0x00 0xfe2d0000 0x00 0x4000>;
1891 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
1895 fifo-depth = <0x100>;
1898 pinctrl-0 = <&sdiom1_pins>;
1905 reg = <0x0 0xfe2e0000 0x0 0x10000>;
1906 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
1914 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1926 reg = <0x0 0xfe470000 0x0 0x1000>;
1927 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
1932 dmas = <&dmac0 0>, <&dmac0 1>;
1939 pinctrl-0 = <&i2s0_lrck
1949 #sound-dai-cells = <0>;
1955 reg = <0x0 0xfe480000 0x0 0x1000>;
1956 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
1965 pinctrl-0 = <&i2s1m0_lrck
1975 #sound-dai-cells = <0>;
1981 reg = <0x0 0xfe490000 0x0 0x1000>;
1982 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
1987 dmas = <&dmac1 0>, <&dmac1 1>;
1991 pinctrl-0 = <&i2s2m1_lrck
1995 #sound-dai-cells = <0>;
2001 reg = <0x0 0xfe4a0000 0x0 0x1000>;
2002 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
2011 pinctrl-0 = <&i2s3_lrck
2015 #sound-dai-cells = <0>;
2021 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
2022 <0x0 0xfe680000 0 0x100000>; /* GICR */
2023 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
2025 mbi-alias = <0x0 0xfe610000>;
2035 reg = <0x0 0xfe640000 0x0 0x20000>;
2042 reg = <0x0 0xfe660000 0x0 0x20000>;
2048 ppi_partition0: interrupt-partition-0 {
2060 reg = <0x0 0xfea10000 0x0 0x4000>;
2061 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>,
2062 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>;
2071 reg = <0x0 0xfea30000 0x0 0x4000>;
2072 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
2073 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>;
2082 reg = <0x0 0xfea90000 0x0 0x1000>;
2085 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>;
2086 pinctrl-0 = <&i2c1m0_xfer>;
2089 #size-cells = <0>;
2095 reg = <0x0 0xfeaa0000 0x0 0x1000>;
2098 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
2099 pinctrl-0 = <&i2c2m0_xfer>;
2102 #size-cells = <0>;
2108 reg = <0x0 0xfeab0000 0x0 0x1000>;
2111 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
2112 pinctrl-0 = <&i2c3m0_xfer>;
2115 #size-cells = <0>;
2121 reg = <0x0 0xfeac0000 0x0 0x1000>;
2124 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
2125 pinctrl-0 = <&i2c4m0_xfer>;
2128 #size-cells = <0>;
2134 reg = <0x0 0xfead0000 0x0 0x1000>;
2137 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>;
2138 pinctrl-0 = <&i2c5m0_xfer>;
2141 #size-cells = <0>;
2147 reg = <0x0 0xfeae0000 0x0 0x20>;
2148 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
2155 reg = <0x0 0xfeaf0000 0x0 0x100>;
2158 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
2163 reg = <0x0 0xfeb00000 0x0 0x1000>;
2164 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;
2170 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
2173 #size-cells = <0>;
2179 reg = <0x0 0xfeb10000 0x0 0x1000>;
2180 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
2186 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
2189 #size-cells = <0>;
2195 reg = <0x0 0xfeb20000 0x0 0x1000>;
2196 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>;
2202 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
2205 #size-cells = <0>;
2211 reg = <0x0 0xfeb30000 0x0 0x1000>;
2212 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>;
2218 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
2221 #size-cells = <0>;
2227 reg = <0x0 0xfeb40000 0x0 0x100>;
2228 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>;
2233 pinctrl-0 = <&uart1m1_xfer>;
2242 reg = <0x0 0xfeb50000 0x0 0x100>;
2243 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>;
2248 pinctrl-0 = <&uart2m1_xfer>;
2257 reg = <0x0 0xfeb60000 0x0 0x100>;
2258 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>;
2263 pinctrl-0 = <&uart3m1_xfer>;
2272 reg = <0x0 0xfeb70000 0x0 0x100>;
2273 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>;
2278 pinctrl-0 = <&uart4m1_xfer>;
2287 reg = <0x0 0xfeb80000 0x0 0x100>;
2288 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>;
2293 pinctrl-0 = <&uart5m1_xfer>;
2302 reg = <0x0 0xfeb90000 0x0 0x100>;
2303 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>;
2308 pinctrl-0 = <&uart6m1_xfer>;
2317 reg = <0x0 0xfeba0000 0x0 0x100>;
2318 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>;
2323 pinctrl-0 = <&uart7m1_xfer>;
2332 reg = <0x0 0xfebb0000 0x0 0x100>;
2333 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>;
2338 pinctrl-0 = <&uart8m1_xfer>;
2347 reg = <0x0 0xfebc0000 0x0 0x100>;
2348 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>;
2353 pinctrl-0 = <&uart9m1_xfer>;
2362 reg = <0x0 0xfebd0000 0x0 0x10>;
2365 pinctrl-0 = <&pwm4m0_pins>;
2373 reg = <0x0 0xfebd0010 0x0 0x10>;
2376 pinctrl-0 = <&pwm5m0_pins>;
2384 reg = <0x0 0xfebd0020 0x0 0x10>;
2387 pinctrl-0 = <&pwm6m0_pins>;
2395 reg = <0x0 0xfebd0030 0x0 0x10>;
2398 pinctrl-0 = <&pwm7m0_pins>;
2406 reg = <0x0 0xfebe0000 0x0 0x10>;
2409 pinctrl-0 = <&pwm8m0_pins>;
2417 reg = <0x0 0xfebe0010 0x0 0x10>;
2420 pinctrl-0 = <&pwm9m0_pins>;
2428 reg = <0x0 0xfebe0020 0x0 0x10>;
2431 pinctrl-0 = <&pwm10m0_pins>;
2439 reg = <0x0 0xfebe0030 0x0 0x10>;
2442 pinctrl-0 = <&pwm11m0_pins>;
2450 reg = <0x0 0xfebf0000 0x0 0x10>;
2453 pinctrl-0 = <&pwm12m0_pins>;
2461 reg = <0x0 0xfebf0010 0x0 0x10>;
2464 pinctrl-0 = <&pwm13m0_pins>;
2472 reg = <0x0 0xfebf0020 0x0 0x10>;
2475 pinctrl-0 = <&pwm14m0_pins>;
2483 reg = <0x0 0xfebf0030 0x0 0x10>;
2486 pinctrl-0 = <&pwm15m0_pins>;
2495 polling-delay-passive = <0>;
2496 polling-delay = <0>;
2497 thermal-sensors = <&tsadc 0>;
2502 hysteresis = <0>;
2508 /* sensor between A76 cores 0 and 1 */
2511 polling-delay = <0>;
2523 hysteresis = <0>;
2541 polling-delay = <0>;
2553 hysteresis = <0>;
2571 polling-delay = <0>;
2583 hysteresis = <0>;
2602 polling-delay-passive = <0>;
2603 polling-delay = <0>;
2609 hysteresis = <0>;
2617 polling-delay = <0>;
2629 hysteresis = <0>;
2644 polling-delay-passive = <0>;
2645 polling-delay = <0>;
2651 hysteresis = <0>;
2660 reg = <0x0 0xfec00000 0x0 0x400>;
2661 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
2669 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2670 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2671 pinctrl-0 = <&tsadc_gpio_func>;
2680 reg = <0x0 0xfec10000 0x0 0x10000>;
2681 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
2692 reg = <0x0 0xfec80000 0x0 0x1000>;
2695 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>;
2696 pinctrl-0 = <&i2c6m0_xfer>;
2699 #size-cells = <0>;
2705 reg = <0x0 0xfec90000 0x0 0x1000>;
2708 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
2709 pinctrl-0 = <&i2c7m0_xfer>;
2712 #size-cells = <0>;
2718 reg = <0x0 0xfeca0000 0x0 0x1000>;
2721 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;
2722 pinctrl-0 = <&i2c8m0_xfer>;
2725 #size-cells = <0>;
2731 reg = <0x0 0xfecb0000 0x0 0x1000>;
2732 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
2738 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
2741 #size-cells = <0>;
2747 reg = <0x0 0xfecc0000 0x0 0x400>;
2758 reg = <0x02 0x2>;
2762 reg = <0x07 0x10>;
2766 reg = <0x17 0x1>;
2770 reg = <0x18 0x1>;
2774 reg = <0x19 0x1>;
2778 reg = <0x1a 0x1>;
2782 reg = <0x1b 0x1>;
2786 reg = <0x1c 0x1>;
2791 reg = <0x28 0x1>;
2795 reg = <0x29 0x1>;
2801 reg = <0x0 0xfed10000 0x0 0x4000>;
2802 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
2803 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
2812 reg = <0x0 0xfed60000 0x0 0x2000>;
2815 #phy-cells = <0>;
2828 reg = <0x0 0xfed80000 0x0 0x10000>;
2850 reg = <0x0 0xfee00000 0x0 0x100>;
2866 reg = <0x0 0xfee20000 0x0 0x100>;
2882 reg = <0x0 0xff001000 0x0 0xef000>;
2883 ranges = <0x0 0x0 0xff001000 0xef000>;
2897 reg = <0x0 0xfd8a0000 0x0 0x100>;
2898 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
2901 gpio-ranges = <&pinctrl 0 0 32>;
2909 reg = <0x0 0xfec20000 0x0 0x100>;
2910 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
2913 gpio-ranges = <&pinctrl 0 32 32>;
2921 reg = <0x0 0xfec30000 0x0 0x100>;
2922 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>;
2925 gpio-ranges = <&pinctrl 0 64 32>;
2933 reg = <0x0 0xfec40000 0x0 0x100>;
2934 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
2937 gpio-ranges = <&pinctrl 0 96 32>;
2945 reg = <0x0 0xfec50000 0x0 0x100>;
2946 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>;
2949 gpio-ranges = <&pinctrl 0 128 32>;