Lines Matching +full:0 +full:xfead0000
56 #size-cells = <0>;
91 cpu_l0: cpu@0 {
94 reg = <0x0>;
115 reg = <0x100>;
134 reg = <0x200>;
153 reg = <0x300>;
172 reg = <0x400>;
193 reg = <0x500>;
212 reg = <0x600>;
233 reg = <0x700>;
254 arm,psci-suspend-param = <0x0010000>;
368 arm,smc-id = <0x82000010>;
371 #size-cells = <0>;
374 reg = <0x14>;
379 reg = <0x16>;
400 spll: clock-0 {
404 #clock-cells = <0>;
409 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
410 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
411 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
412 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
413 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
421 #clock-cells = <0>;
428 #clock-cells = <0>;
433 reg = <0x0 0x0010f000 0x0 0x100>;
434 ranges = <0 0x0 0x0010f000 0x100>;
438 scmi_shmem: sram@0 {
440 reg = <0x0 0x100>;
446 reg = <0x0 0xfb000000 0x0 0x200000>;
454 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
455 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
456 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
464 reg = <0x0 0xfc000000 0x0 0x400000>;
465 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
486 reg = <0x0 0xfc800000 0x0 0x40000>;
487 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
497 reg = <0x0 0xfc840000 0x0 0x40000>;
498 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
508 reg = <0x0 0xfc880000 0x0 0x40000>;
509 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
519 reg = <0x0 0xfc8c0000 0x0 0x40000>;
520 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
530 reg = <0x0 0xfcd00000 0x0 0x400000>;
531 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
551 reg = <0x0 0xfc900000 0x0 0x200000>;
552 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>,
553 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>,
554 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
555 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
563 reg = <0x0 0xfcb00000 0x0 0x200000>;
564 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>,
565 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
566 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>,
567 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
575 reg = <0x0 0xfd58a000 0x0 0x10000>;
580 reg = <0x0 0xfd58c000 0x0 0x1000>;
585 reg = <0x0 0xfd5a4000 0x0 0x2000>;
590 reg = <0x0 0xfd5a6000 0x0 0x2000>;
596 reg = <0x0 0xfd5a8000 0x0 0x4000>;
602 reg = <0x0 0xfd5ac000 0x0 0x4000>;
607 reg = <0x0 0xfd5b0000 0x0 0x1000>;
612 reg = <0x0 0xfd5bc000 0x0 0x100>;
617 reg = <0x0 0xfd5c4000 0x0 0x100>;
622 reg = <0x0 0xfd5c8000 0x0 0x4000>;
627 reg = <0x0 0xfd5d0000 0x0 0x4000>;
631 u2phy0: usb2phy@0 {
633 reg = <0x0 0x10>;
634 #clock-cells = <0>;
638 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
644 #phy-cells = <0>;
652 reg = <0x0 0xfd5d8000 0x0 0x4000>;
658 reg = <0x8000 0x10>;
659 #clock-cells = <0>;
663 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
669 #phy-cells = <0>;
677 reg = <0x0 0xfd5dc000 0x0 0x4000>;
683 reg = <0xc000 0x10>;
684 #clock-cells = <0>;
688 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
694 #phy-cells = <0>;
702 reg = <0x0 0xfd5e0000 0x0 0x100>;
707 reg = <0x0 0xfd5f0000 0x0 0x10000>;
712 reg = <0x0 0xfd600000 0x0 0x100000>;
713 ranges = <0x0 0x0 0xfd600000 0x100000>;
720 reg = <0x0 0xfd7c0000 0x0 0x5c000>;
748 reg = <0x0 0xfd880000 0x0 0x1000>;
749 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;
752 pinctrl-0 = <&i2c0m0_xfer>;
755 #size-cells = <0>;
761 reg = <0x0 0xfd890000 0x0 0x100>;
762 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
767 pinctrl-0 = <&uart0m1_xfer>;
776 reg = <0x0 0xfd8b0000 0x0 0x10>;
779 pinctrl-0 = <&pwm0m0_pins>;
787 reg = <0x0 0xfd8b0010 0x0 0x10>;
790 pinctrl-0 = <&pwm1m0_pins>;
798 reg = <0x0 0xfd8b0020 0x0 0x10>;
801 pinctrl-0 = <&pwm2m0_pins>;
809 reg = <0x0 0xfd8b0030 0x0 0x10>;
812 pinctrl-0 = <&pwm3m0_pins>;
820 reg = <0x0 0xfd8d8000 0x0 0x400>;
826 #size-cells = <0>;
832 #power-domain-cells = <0>;
834 #size-cells = <0>;
845 #power-domain-cells = <0>;
847 #size-cells = <0>;
855 #power-domain-cells = <0>;
863 #power-domain-cells = <0>;
877 #power-domain-cells = <0>;
883 #size-cells = <0>;
884 #power-domain-cells = <0>;
894 #power-domain-cells = <0>;
903 #power-domain-cells = <0>;
913 #size-cells = <0>;
914 #power-domain-cells = <0>;
925 #power-domain-cells = <0>;
959 #size-cells = <0>;
960 #power-domain-cells = <0>;
969 #power-domain-cells = <0>;
978 #power-domain-cells = <0>;
986 #power-domain-cells = <0>;
993 #power-domain-cells = <0>;
1004 #size-cells = <0>;
1005 #power-domain-cells = <0>;
1017 #power-domain-cells = <0>;
1031 #power-domain-cells = <0>;
1046 #size-cells = <0>;
1047 #power-domain-cells = <0>;
1057 #power-domain-cells = <0>;
1068 #power-domain-cells = <0>;
1076 #power-domain-cells = <0>;
1092 #power-domain-cells = <0>;
1099 #power-domain-cells = <0>;
1106 #power-domain-cells = <0>;
1113 #power-domain-cells = <0>;
1119 #power-domain-cells = <0>;
1124 #power-domain-cells = <0>;
1131 reg = <0x0 0xfdb50000 0x0 0x800>;
1132 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1142 reg = <0x0 0xfdb50800 0x0 0x40>;
1143 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1147 #iommu-cells = <0>;
1152 reg = <0x0 0xfdb80000 0x0 0x180>;
1153 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1163 reg = <0x0 0xfdba0000 0x0 0x800>;
1164 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>;
1173 reg = <0x0 0xfdba0800 0x0 0x40>;
1174 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
1178 #iommu-cells = <0>;
1183 reg = <0x0 0xfdba4000 0x0 0x800>;
1184 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>;
1193 reg = <0x0 0xfdba4800 0x0 0x40>;
1194 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>;
1198 #iommu-cells = <0>;
1203 reg = <0x0 0xfdba8000 0x0 0x800>;
1204 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>;
1213 reg = <0x0 0xfdba8800 0x0 0x40>;
1214 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>;
1218 #iommu-cells = <0>;
1223 reg = <0x0 0xfdbac000 0x0 0x800>;
1224 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
1233 reg = <0x0 0xfdbac800 0x0 0x40>;
1234 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>;
1238 #iommu-cells = <0>;
1243 reg = <0x0 0xfdc70000 0x0 0x800>;
1244 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
1256 reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
1258 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
1283 #size-cells = <0>;
1285 vp0: port@0 {
1287 #size-cells = <0>;
1288 reg = <0>;
1293 #size-cells = <0>;
1299 #size-cells = <0>;
1305 #size-cells = <0>;
1313 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
1314 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
1317 #iommu-cells = <0>;
1324 reg = <0x0 0xfddc0000 0x0 0x1000>;
1325 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;
1330 dmas = <&dmac2 0>;
1335 #sound-dai-cells = <0>;
1341 reg = <0x0 0xfddf0000 0x0 0x1000>;
1342 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
1352 #sound-dai-cells = <0>;
1358 reg = <0x0 0xfddfc000 0x0 0x1000>;
1359 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
1369 #sound-dai-cells = <0>;
1375 reg = <0x0 0xfde80000 0x0 0x20000>;
1383 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
1384 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
1385 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
1386 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
1387 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
1391 pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
1402 #size-cells = <0>;
1404 hdmi0_in: port@0 {
1405 reg = <0>;
1416 reg = <0x0 0xfdf35000 0x0 0x20>;
1421 reg = <0x0 0xfdf35200 0x0 0x20>;
1426 reg = <0x0 0xfdf35400 0x0 0x20>;
1431 reg = <0x0 0xfdf35600 0x0 0x20>;
1436 reg = <0x0 0xfdf36000 0x0 0x20>;
1441 reg = <0x0 0xfdf39000 0x0 0x20>;
1446 reg = <0x0 0xfdf3d800 0x0 0x20>;
1451 reg = <0x0 0xfdf3e000 0x0 0x20>;
1456 reg = <0x0 0xfdf3e200 0x0 0x20>;
1461 reg = <0x0 0xfdf3e400 0x0 0x20>;
1466 reg = <0x0 0xfdf3e600 0x0 0x20>;
1471 reg = <0x0 0xfdf40000 0x0 0x20>;
1476 reg = <0x0 0xfdf40200 0x0 0x20>;
1481 reg = <0x0 0xfdf40400 0x0 0x20>;
1486 reg = <0x0 0xfdf40500 0x0 0x20>;
1491 reg = <0x0 0xfdf40600 0x0 0x20>;
1496 reg = <0x0 0xfdf40800 0x0 0x20>;
1501 reg = <0x0 0xfdf41000 0x0 0x20>;
1506 reg = <0x0 0xfdf41100 0x0 0x20>;
1511 reg = <0x0 0xfdf60000 0x0 0x20>;
1516 reg = <0x0 0xfdf60200 0x0 0x20>;
1521 reg = <0x0 0xfdf60400 0x0 0x20>;
1526 reg = <0x0 0xfdf61000 0x0 0x20>;
1531 reg = <0x0 0xfdf61200 0x0 0x20>;
1536 reg = <0x0 0xfdf61400 0x0 0x20>;
1541 reg = <0x0 0xfdf62000 0x0 0x20>;
1546 reg = <0x0 0xfdf63000 0x0 0x20>;
1551 reg = <0x0 0xfdf64000 0x0 0x20>;
1556 reg = <0x0 0xfdf66000 0x0 0x20>;
1561 reg = <0x0 0xfdf66200 0x0 0x20>;
1566 reg = <0x0 0xfdf66400 0x0 0x20>;
1571 reg = <0x0 0xfdf66600 0x0 0x20>;
1576 reg = <0x0 0xfdf66800 0x0 0x20>;
1581 reg = <0x0 0xfdf66a00 0x0 0x20>;
1586 reg = <0x0 0xfdf66c00 0x0 0x20>;
1591 reg = <0x0 0xfdf66e00 0x0 0x20>;
1596 reg = <0x0 0xfdf67000 0x0 0x20>;
1601 reg = <0x0 0xfdf67200 0x0 0x20>;
1606 reg = <0x0 0xfdf70000 0x0 0x20>;
1611 reg = <0x0 0xfdf71000 0x0 0x20>;
1616 reg = <0x0 0xfdf72000 0x0 0x20>;
1621 reg = <0x0 0xfdf72200 0x0 0x20>;
1626 reg = <0x0 0xfdf72400 0x0 0x20>;
1631 reg = <0x0 0xfdf80000 0x0 0x20>;
1636 reg = <0x0 0xfdf81000 0x0 0x20>;
1641 reg = <0x0 0xfdf81200 0x0 0x20>;
1646 reg = <0x0 0xfdf82000 0x0 0x20>;
1651 reg = <0x0 0xfdf82200 0x0 0x20>;
1655 reg = <0x00 0xfe060000 0x00 0x10000>;
1657 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
1658 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
1659 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
1660 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1666 bus-range = <0x30 0x3f>;
1674 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
1675 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
1676 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
1677 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
1678 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>;
1681 interrupt-map-mask = <0 0 0 7>;
1682 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
1683 <0 0 0 2 &pcie2x1l1_intc 1>,
1684 <0 0 0 3 &pcie2x1l1_intc 2>,
1685 <0 0 0 4 &pcie2x1l1_intc 3>;
1688 msi-map = <0x3000 &its0 0x3000 0x1000>;
1693 ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
1694 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
1695 <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
1696 reg = <0xa 0x40c00000 0x0 0x00400000>,
1697 <0x0 0xfe180000 0x0 0x00010000>,
1698 <0x0 0xf3000000 0x0 0x00100000>;
1708 #address-cells = <0>;
1711 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>;
1717 bus-range = <0x40 0x4f>;
1725 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
1726 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
1727 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
1728 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
1729 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
1732 interrupt-map-mask = <0 0 0 7>;
1733 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
1734 <0 0 0 2 &pcie2x1l2_intc 1>,
1735 <0 0 0 3 &pcie2x1l2_intc 2>,
1736 <0 0 0 4 &pcie2x1l2_intc 3>;
1739 msi-map = <0x4000 &its0 0x4000 0x1000>;
1744 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
1745 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
1746 <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
1747 reg = <0xa 0x41000000 0x0 0x00400000>,
1748 <0x0 0xfe190000 0x0 0x00010000>,
1749 <0x0 0xf4000000 0x0 0x00100000>;
1759 #address-cells = <0>;
1762 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
1768 reg = <0x0 0xfe1c0000 0x0 0x10000>;
1769 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
1770 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
1792 #address-cells = <0x1>;
1793 #size-cells = <0x0>;
1797 snps,blen = <0 0 0 0 16 8 4>;
1817 reg = <0 0xfe210000 0 0x1000>;
1818 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
1823 ports-implemented = <0x1>;
1825 #size-cells = <0>;
1828 sata-port@0 {
1829 reg = <0>;
1840 reg = <0 0xfe230000 0 0x1000>;
1841 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
1846 ports-implemented = <0x1>;
1848 #size-cells = <0>;
1851 sata-port@0 {
1852 reg = <0>;
1863 reg = <0x0 0xfe2b0000 0x0 0x4000>;
1864 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
1868 #size-cells = <0>;
1874 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1875 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
1879 fifo-depth = <0x100>;
1882 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1889 reg = <0x00 0xfe2d0000 0x00 0x4000>;
1890 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
1894 fifo-depth = <0x100>;
1897 pinctrl-0 = <&sdiom1_pins>;
1904 reg = <0x0 0xfe2e0000 0x0 0x10000>;
1905 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
1913 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1925 reg = <0x0 0xfe470000 0x0 0x1000>;
1926 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
1931 dmas = <&dmac0 0>, <&dmac0 1>;
1938 pinctrl-0 = <&i2s0_lrck
1948 #sound-dai-cells = <0>;
1954 reg = <0x0 0xfe480000 0x0 0x1000>;
1955 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
1964 pinctrl-0 = <&i2s1m0_lrck
1974 #sound-dai-cells = <0>;
1980 reg = <0x0 0xfe490000 0x0 0x1000>;
1981 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
1986 dmas = <&dmac1 0>, <&dmac1 1>;
1990 pinctrl-0 = <&i2s2m1_lrck
1994 #sound-dai-cells = <0>;
2000 reg = <0x0 0xfe4a0000 0x0 0x1000>;
2001 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
2010 pinctrl-0 = <&i2s3_lrck
2014 #sound-dai-cells = <0>;
2020 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
2021 <0x0 0xfe680000 0 0x100000>; /* GICR */
2022 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
2024 mbi-alias = <0x0 0xfe610000>;
2034 reg = <0x0 0xfe640000 0x0 0x20000>;
2041 reg = <0x0 0xfe660000 0x0 0x20000>;
2047 ppi_partition0: interrupt-partition-0 {
2059 reg = <0x0 0xfea10000 0x0 0x4000>;
2060 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>,
2061 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>;
2070 reg = <0x0 0xfea30000 0x0 0x4000>;
2071 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
2072 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>;
2081 reg = <0x0 0xfea90000 0x0 0x1000>;
2084 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>;
2085 pinctrl-0 = <&i2c1m0_xfer>;
2088 #size-cells = <0>;
2094 reg = <0x0 0xfeaa0000 0x0 0x1000>;
2097 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
2098 pinctrl-0 = <&i2c2m0_xfer>;
2101 #size-cells = <0>;
2107 reg = <0x0 0xfeab0000 0x0 0x1000>;
2110 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
2111 pinctrl-0 = <&i2c3m0_xfer>;
2114 #size-cells = <0>;
2120 reg = <0x0 0xfeac0000 0x0 0x1000>;
2123 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
2124 pinctrl-0 = <&i2c4m0_xfer>;
2127 #size-cells = <0>;
2133 reg = <0x0 0xfead0000 0x0 0x1000>;
2136 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>;
2137 pinctrl-0 = <&i2c5m0_xfer>;
2140 #size-cells = <0>;
2146 reg = <0x0 0xfeae0000 0x0 0x20>;
2147 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
2154 reg = <0x0 0xfeaf0000 0x0 0x100>;
2157 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
2162 reg = <0x0 0xfeb00000 0x0 0x1000>;
2163 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;
2169 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
2172 #size-cells = <0>;
2178 reg = <0x0 0xfeb10000 0x0 0x1000>;
2179 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
2185 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
2188 #size-cells = <0>;
2194 reg = <0x0 0xfeb20000 0x0 0x1000>;
2195 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>;
2201 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
2204 #size-cells = <0>;
2210 reg = <0x0 0xfeb30000 0x0 0x1000>;
2211 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>;
2217 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
2220 #size-cells = <0>;
2226 reg = <0x0 0xfeb40000 0x0 0x100>;
2227 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>;
2232 pinctrl-0 = <&uart1m1_xfer>;
2241 reg = <0x0 0xfeb50000 0x0 0x100>;
2242 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>;
2247 pinctrl-0 = <&uart2m1_xfer>;
2256 reg = <0x0 0xfeb60000 0x0 0x100>;
2257 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>;
2262 pinctrl-0 = <&uart3m1_xfer>;
2271 reg = <0x0 0xfeb70000 0x0 0x100>;
2272 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>;
2277 pinctrl-0 = <&uart4m1_xfer>;
2286 reg = <0x0 0xfeb80000 0x0 0x100>;
2287 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>;
2292 pinctrl-0 = <&uart5m1_xfer>;
2301 reg = <0x0 0xfeb90000 0x0 0x100>;
2302 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>;
2307 pinctrl-0 = <&uart6m1_xfer>;
2316 reg = <0x0 0xfeba0000 0x0 0x100>;
2317 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>;
2322 pinctrl-0 = <&uart7m1_xfer>;
2331 reg = <0x0 0xfebb0000 0x0 0x100>;
2332 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>;
2337 pinctrl-0 = <&uart8m1_xfer>;
2346 reg = <0x0 0xfebc0000 0x0 0x100>;
2347 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>;
2352 pinctrl-0 = <&uart9m1_xfer>;
2361 reg = <0x0 0xfebd0000 0x0 0x10>;
2364 pinctrl-0 = <&pwm4m0_pins>;
2372 reg = <0x0 0xfebd0010 0x0 0x10>;
2375 pinctrl-0 = <&pwm5m0_pins>;
2383 reg = <0x0 0xfebd0020 0x0 0x10>;
2386 pinctrl-0 = <&pwm6m0_pins>;
2394 reg = <0x0 0xfebd0030 0x0 0x10>;
2397 pinctrl-0 = <&pwm7m0_pins>;
2405 reg = <0x0 0xfebe0000 0x0 0x10>;
2408 pinctrl-0 = <&pwm8m0_pins>;
2416 reg = <0x0 0xfebe0010 0x0 0x10>;
2419 pinctrl-0 = <&pwm9m0_pins>;
2427 reg = <0x0 0xfebe0020 0x0 0x10>;
2430 pinctrl-0 = <&pwm10m0_pins>;
2438 reg = <0x0 0xfebe0030 0x0 0x10>;
2441 pinctrl-0 = <&pwm11m0_pins>;
2449 reg = <0x0 0xfebf0000 0x0 0x10>;
2452 pinctrl-0 = <&pwm12m0_pins>;
2460 reg = <0x0 0xfebf0010 0x0 0x10>;
2463 pinctrl-0 = <&pwm13m0_pins>;
2471 reg = <0x0 0xfebf0020 0x0 0x10>;
2474 pinctrl-0 = <&pwm14m0_pins>;
2482 reg = <0x0 0xfebf0030 0x0 0x10>;
2485 pinctrl-0 = <&pwm15m0_pins>;
2494 polling-delay-passive = <0>;
2495 polling-delay = <0>;
2496 thermal-sensors = <&tsadc 0>;
2501 hysteresis = <0>;
2507 /* sensor between A76 cores 0 and 1 */
2510 polling-delay = <0>;
2522 hysteresis = <0>;
2540 polling-delay = <0>;
2552 hysteresis = <0>;
2570 polling-delay = <0>;
2582 hysteresis = <0>;
2601 polling-delay-passive = <0>;
2602 polling-delay = <0>;
2608 hysteresis = <0>;
2616 polling-delay = <0>;
2628 hysteresis = <0>;
2643 polling-delay-passive = <0>;
2644 polling-delay = <0>;
2650 hysteresis = <0>;
2659 reg = <0x0 0xfec00000 0x0 0x400>;
2660 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
2668 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2669 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2670 pinctrl-0 = <&tsadc_gpio_func>;
2679 reg = <0x0 0xfec10000 0x0 0x10000>;
2680 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
2691 reg = <0x0 0xfec80000 0x0 0x1000>;
2694 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>;
2695 pinctrl-0 = <&i2c6m0_xfer>;
2698 #size-cells = <0>;
2704 reg = <0x0 0xfec90000 0x0 0x1000>;
2707 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
2708 pinctrl-0 = <&i2c7m0_xfer>;
2711 #size-cells = <0>;
2717 reg = <0x0 0xfeca0000 0x0 0x1000>;
2720 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;
2721 pinctrl-0 = <&i2c8m0_xfer>;
2724 #size-cells = <0>;
2730 reg = <0x0 0xfecb0000 0x0 0x1000>;
2731 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
2737 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
2740 #size-cells = <0>;
2746 reg = <0x0 0xfecc0000 0x0 0x400>;
2757 reg = <0x02 0x2>;
2761 reg = <0x07 0x10>;
2765 reg = <0x17 0x1>;
2769 reg = <0x18 0x1>;
2773 reg = <0x19 0x1>;
2777 reg = <0x1a 0x1>;
2781 reg = <0x1b 0x1>;
2785 reg = <0x1c 0x1>;
2790 reg = <0x28 0x1>;
2794 reg = <0x29 0x1>;
2800 reg = <0x0 0xfed10000 0x0 0x4000>;
2801 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
2802 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
2811 reg = <0x0 0xfed60000 0x0 0x2000>;
2814 #phy-cells = <0>;
2827 reg = <0x0 0xfed80000 0x0 0x10000>;
2849 reg = <0x0 0xfee00000 0x0 0x100>;
2865 reg = <0x0 0xfee20000 0x0 0x100>;
2881 reg = <0x0 0xff001000 0x0 0xef000>;
2882 ranges = <0x0 0x0 0xff001000 0xef000>;
2896 reg = <0x0 0xfd8a0000 0x0 0x100>;
2897 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
2900 gpio-ranges = <&pinctrl 0 0 32>;
2908 reg = <0x0 0xfec20000 0x0 0x100>;
2909 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
2912 gpio-ranges = <&pinctrl 0 32 32>;
2920 reg = <0x0 0xfec30000 0x0 0x100>;
2921 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>;
2924 gpio-ranges = <&pinctrl 0 64 32>;
2932 reg = <0x0 0xfec40000 0x0 0x100>;
2933 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
2936 gpio-ranges = <&pinctrl 0 96 32>;
2944 reg = <0x0 0xfec50000 0x0 0x100>;
2945 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>;
2948 gpio-ranges = <&pinctrl 0 128 32>;