Lines Matching +full:rk3399 +full:- +full:ddr
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3576-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rk3576-power.h>
12 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
14 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
53 xin32k: clock-xin32k {
54 compatible = "fixed-clock";
55 clock-frequency = <32768>;
56 clock-output-names = "xin32k";
57 #clock-cells = <0>;
60 xin24m: clock-xin24m {
61 compatible = "fixed-clock";
62 #clock-cells = <0>;
63 clock-frequency = <24000000>;
64 clock-output-names = "xin24m";
67 spll: clock-spll {
68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <702000000>;
71 clock-output-names = "spll";
75 #address-cells = <1>;
76 #size-cells = <0>;
78 cpu-map {
111 compatible = "arm,cortex-a53";
113 enable-method = "psci";
114 capacity-dmips-mhz = <485>;
116 operating-points-v2 = <&cluster0_opp_table>;
117 dynamic-power-coefficient = <120>;
118 cpu-idle-states = <&CPU_SLEEP>;
119 #cooling-cells = <2>;
124 compatible = "arm,cortex-a53";
126 enable-method = "psci";
127 capacity-dmips-mhz = <485>;
129 operating-points-v2 = <&cluster0_opp_table>;
130 cpu-idle-states = <&CPU_SLEEP>;
131 #cooling-cells = <2>;
136 compatible = "arm,cortex-a53";
138 enable-method = "psci";
139 capacity-dmips-mhz = <485>;
141 operating-points-v2 = <&cluster0_opp_table>;
142 cpu-idle-states = <&CPU_SLEEP>;
143 #cooling-cells = <2>;
148 compatible = "arm,cortex-a53";
150 enable-method = "psci";
151 capacity-dmips-mhz = <485>;
153 operating-points-v2 = <&cluster0_opp_table>;
154 cpu-idle-states = <&CPU_SLEEP>;
155 #cooling-cells = <2>;
160 compatible = "arm,cortex-a72";
162 enable-method = "psci";
163 capacity-dmips-mhz = <1024>;
165 operating-points-v2 = <&cluster1_opp_table>;
166 dynamic-power-coefficient = <320>;
167 cpu-idle-states = <&CPU_SLEEP>;
168 #cooling-cells = <2>;
173 compatible = "arm,cortex-a72";
175 enable-method = "psci";
176 capacity-dmips-mhz = <1024>;
178 operating-points-v2 = <&cluster1_opp_table>;
179 cpu-idle-states = <&CPU_SLEEP>;
180 #cooling-cells = <2>;
185 compatible = "arm,cortex-a72";
187 enable-method = "psci";
188 capacity-dmips-mhz = <1024>;
190 operating-points-v2 = <&cluster1_opp_table>;
191 cpu-idle-states = <&CPU_SLEEP>;
192 #cooling-cells = <2>;
197 compatible = "arm,cortex-a72";
199 enable-method = "psci";
200 capacity-dmips-mhz = <1024>;
202 operating-points-v2 = <&cluster1_opp_table>;
203 cpu-idle-states = <&CPU_SLEEP>;
204 #cooling-cells = <2>;
207 idle-states {
208 entry-method = "psci";
210 CPU_SLEEP: cpu-sleep {
211 compatible = "arm,idle-state";
212 arm,psci-suspend-param = <0x0010000>;
213 entry-latency-us = <120>;
214 exit-latency-us = <250>;
215 min-residency-us = <900>;
216 local-timer-stop;
221 cluster0_opp_table: opp-table-cluster0 {
222 compatible = "operating-points-v2";
223 opp-shared;
225 opp-408000000 {
226 opp-hz = /bits/ 64 <408000000>;
227 opp-microvolt = <700000 700000 950000>;
228 clock-latency-ns = <40000>;
231 opp-600000000 {
232 opp-hz = /bits/ 64 <600000000>;
233 opp-microvolt = <700000 700000 950000>;
234 clock-latency-ns = <40000>;
237 opp-816000000 {
238 opp-hz = /bits/ 64 <816000000>;
239 opp-microvolt = <700000 700000 950000>;
240 clock-latency-ns = <40000>;
243 opp-1008000000 {
244 opp-hz = /bits/ 64 <1008000000>;
245 opp-microvolt = <700000 700000 950000>;
246 clock-latency-ns = <40000>;
249 opp-1200000000 {
250 opp-hz = /bits/ 64 <1200000000>;
251 opp-microvolt = <700000 700000 950000>;
252 clock-latency-ns = <40000>;
255 opp-1416000000 {
256 opp-hz = /bits/ 64 <1416000000>;
257 opp-microvolt = <725000 725000 950000>;
258 clock-latency-ns = <40000>;
261 opp-1608000000 {
262 opp-hz = /bits/ 64 <1608000000>;
263 opp-microvolt = <750000 750000 950000>;
264 clock-latency-ns = <40000>;
267 opp-1800000000 {
268 opp-hz = /bits/ 64 <1800000000>;
269 opp-microvolt = <825000 825000 950000>;
270 clock-latency-ns = <40000>;
271 opp-suspend;
274 opp-2016000000 {
275 opp-hz = /bits/ 64 <2016000000>;
276 opp-microvolt = <900000 900000 950000>;
277 clock-latency-ns = <40000>;
281 cluster1_opp_table: opp-table-cluster1 {
282 compatible = "operating-points-v2";
283 opp-shared;
285 opp-408000000 {
286 opp-hz = /bits/ 64 <408000000>;
287 opp-microvolt = <700000 700000 950000>;
288 clock-latency-ns = <40000>;
289 opp-suspend;
292 opp-600000000 {
293 opp-hz = /bits/ 64 <600000000>;
294 opp-microvolt = <700000 700000 950000>;
295 clock-latency-ns = <40000>;
298 opp-816000000 {
299 opp-hz = /bits/ 64 <816000000>;
300 opp-microvolt = <700000 700000 950000>;
301 clock-latency-ns = <40000>;
304 opp-1008000000 {
305 opp-hz = /bits/ 64 <1008000000>;
306 opp-microvolt = <700000 700000 950000>;
307 clock-latency-ns = <40000>;
310 opp-1200000000 {
311 opp-hz = /bits/ 64 <1200000000>;
312 opp-microvolt = <700000 700000 950000>;
313 clock-latency-ns = <40000>;
316 opp-1416000000 {
317 opp-hz = /bits/ 64 <1416000000>;
318 opp-microvolt = <712500 712500 950000>;
319 clock-latency-ns = <40000>;
322 opp-1608000000 {
323 opp-hz = /bits/ 64 <1608000000>;
324 opp-microvolt = <737500 737500 950000>;
325 clock-latency-ns = <40000>;
328 opp-1800000000 {
329 opp-hz = /bits/ 64 <1800000000>;
330 opp-microvolt = <800000 800000 950000>;
331 clock-latency-ns = <40000>;
334 opp-2016000000 {
335 opp-hz = /bits/ 64 <2016000000>;
336 opp-microvolt = <862500 862500 950000>;
337 clock-latency-ns = <40000>;
340 opp-2208000000 {
341 opp-hz = /bits/ 64 <2208000000>;
342 opp-microvolt = <925000 925000 950000>;
343 clock-latency-ns = <40000>;
347 gpu_opp_table: opp-table-gpu {
348 compatible = "operating-points-v2";
350 opp-300000000 {
351 opp-hz = /bits/ 64 <300000000>;
352 opp-microvolt = <700000 700000 850000>;
355 opp-400000000 {
356 opp-hz = /bits/ 64 <400000000>;
357 opp-microvolt = <700000 700000 850000>;
360 opp-500000000 {
361 opp-hz = /bits/ 64 <500000000>;
362 opp-microvolt = <700000 700000 850000>;
365 opp-600000000 {
366 opp-hz = /bits/ 64 <600000000>;
367 opp-microvolt = <700000 700000 850000>;
370 opp-700000000 {
371 opp-hz = /bits/ 64 <700000000>;
372 opp-microvolt = <725000 725000 850000>;
375 opp-800000000 {
376 opp-hz = /bits/ 64 <800000000>;
377 opp-microvolt = <775000 775000 850000>;
380 opp-900000000 {
381 opp-hz = /bits/ 64 <900000000>;
382 opp-microvolt = <825000 825000 850000>;
385 opp-950000000 {
386 opp-hz = /bits/ 64 <950000000>;
387 opp-microvolt = <850000 850000 850000>;
391 display_subsystem: display-subsystem {
392 compatible = "rockchip,display-subsystem";
398 compatible = "arm,scmi-smc";
399 arm,smc-id = <0x82000010>;
401 #address-cells = <1>;
402 #size-cells = <0>;
406 #clock-cells = <1>;
411 hdmi_sound: hdmi-sound {
412 compatible = "simple-audio-card";
413 simple-audio-card,name = "HDMI";
414 simple-audio-card,format = "i2s";
415 simple-audio-card,mclk-fs = <256>;
418 simple-audio-card,codec {
419 sound-dai = <&hdmi>;
422 simple-audio-card,cpu {
423 sound-dai = <&sai6>;
428 compatible = "rockchip,rk3576-pinctrl";
430 #address-cells = <2>;
431 #size-cells = <2>;
435 compatible = "rockchip,gpio-bank";
438 gpio-controller;
439 gpio-ranges = <&pinctrl 0 0 32>;
441 interrupt-controller;
442 #gpio-cells = <2>;
443 #interrupt-cells = <2>;
447 compatible = "rockchip,gpio-bank";
450 gpio-controller;
451 gpio-ranges = <&pinctrl 0 32 32>;
453 interrupt-controller;
454 #gpio-cells = <2>;
455 #interrupt-cells = <2>;
459 compatible = "rockchip,gpio-bank";
462 gpio-controller;
463 gpio-ranges = <&pinctrl 0 64 32>;
465 interrupt-controller;
466 #gpio-cells = <2>;
467 #interrupt-cells = <2>;
471 compatible = "rockchip,gpio-bank";
474 gpio-controller;
475 gpio-ranges = <&pinctrl 0 96 32>;
477 interrupt-controller;
478 #gpio-cells = <2>;
479 #interrupt-cells = <2>;
483 compatible = "rockchip,gpio-bank";
486 gpio-controller;
487 gpio-ranges = <&pinctrl 0 128 32>;
489 interrupt-controller;
490 #gpio-cells = <2>;
491 #interrupt-cells = <2>;
495 pmu_a53: pmu-a53 {
496 compatible = "arm,cortex-a53-pmu";
501 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>;
504 pmu_a72: pmu-a72 {
505 compatible = "arm,cortex-a72-pmu";
510 interrupt-affinity = <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>;
514 compatible = "arm,psci-1.0";
518 thermal_zones: thermal-zones {
520 package_thermal: package-thermal {
521 polling-delay-passive = <0>;
522 polling-delay = <0>;
523 thermal-sensors = <&tsadc 0>;
526 package_crit: package-crit {
534 /* sensor for cluster1 (big Cortex-A72 cores) */
535 bigcore_thermal: bigcore-thermal {
536 polling-delay-passive = <100>;
537 polling-delay = <0>;
538 thermal-sensors = <&tsadc 1>;
541 bigcore_alert: bigcore-alert {
547 bigcore_crit: bigcore-crit {
554 cooling-maps {
557 cooling-device =
566 /* sensor for cluster0 (little Cortex-A53 cores) */
567 littlecore_thermal: littlecore-thermal {
568 polling-delay-passive = <100>;
569 polling-delay = <0>;
570 thermal-sensors = <&tsadc 2>;
573 littlecore_alert: littlecore-alert {
579 littlecore_crit: littlecore-crit {
586 cooling-maps {
589 cooling-device =
598 gpu_thermal: gpu-thermal {
599 polling-delay-passive = <100>;
600 polling-delay = <0>;
601 thermal-sensors = <&tsadc 3>;
604 gpu_alert: gpu-alert {
610 gpu_crit: gpu-crit {
617 cooling-maps {
620 cooling-device =
626 npu_thermal: npu-thermal {
627 polling-delay-passive = <0>;
628 polling-delay = <0>;
629 thermal-sensors = <&tsadc 4>;
632 npu_crit: npu-crit {
640 ddr_thermal: ddr-thermal {
641 polling-delay-passive = <0>;
642 polling-delay = <0>;
643 thermal-sensors = <&tsadc 5>;
646 ddr_crit: ddr-crit {
656 compatible = "arm,armv8-timer";
664 compatible = "simple-bus";
665 #address-cells = <2>;
666 #size-cells = <2>;
670 compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
674 reg-names = "dbi", "apb", "config";
675 bus-range = <0x0 0xf>;
679 clock-names = "aclk_mst", "aclk_slv",
689 interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
690 #interrupt-cells = <1>;
691 interrupt-map-mask = <0 0 0 7>;
692 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
696 linux,pci-domain = <0>;
697 max-link-speed = <2>;
698 num-ib-windows = <8>;
699 num-viewport = <8>;
700 num-ob-windows = <2>;
701 num-lanes = <1>;
703 phy-names = "pcie-phy";
704 power-domains = <&power RK3576_PD_PHP>;
709 reset-names = "pwr", "pipe";
710 #address-cells = <3>;
711 #size-cells = <2>;
714 pcie0_intc: legacy-interrupt-controller {
715 interrupt-controller;
716 #address-cells = <0>;
717 #interrupt-cells = <1>;
718 interrupt-parent = <&gic>;
724 compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
728 reg-names = "dbi", "apb", "config";
729 bus-range = <0x20 0x2f>;
733 clock-names = "aclk_mst", "aclk_slv",
743 interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
744 #interrupt-cells = <1>;
745 interrupt-map-mask = <0 0 0 7>;
746 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
750 linux,pci-domain = <1>;
751 max-link-speed = <2>;
752 num-ib-windows = <8>;
753 num-viewport = <8>;
754 num-ob-windows = <2>;
755 num-lanes = <1>;
757 phy-names = "pcie-phy";
758 power-domains = <&power RK3576_PD_SUBPHP>;
763 reset-names = "pwr", "pipe";
764 #address-cells = <3>;
765 #size-cells = <2>;
768 pcie1_intc: legacy-interrupt-controller {
769 interrupt-controller;
770 #address-cells = <0>;
771 #interrupt-cells = <1>;
772 interrupt-parent = <&gic>;
778 compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
783 clock-names = "ref_clk", "suspend_clk", "bus_clk";
785 power-domains = <&power RK3576_PD_USB>;
789 phy-names = "usb2-phy", "usb3-phy";
792 snps,dis-u1-entry-quirk;
793 snps,dis-u2-entry-quirk;
794 snps,dis-u2-freeclk-exists-quirk;
795 snps,dis-del-phy-power-chg-quirk;
796 snps,dis-tx-ipgap-linecheck-quirk;
797 snps,parkmode-disable-hs-quirk;
798 snps,parkmode-disable-ss-quirk;
803 compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
808 clock-names = "ref_clk", "suspend_clk", "bus_clk";
810 power-domains = <&power RK3576_PD_PHP>;
814 phy-names = "usb2-phy", "usb3-phy";
817 snps,dis-u1-entry-quirk;
818 snps,dis-u2-entry-quirk;
819 snps,dis-u2-freeclk-exists-quirk;
820 snps,dis-del-phy-power-chg-quirk;
821 snps,dis-tx-ipgap-linecheck-quirk;
823 snps,parkmode-disable-hs-quirk;
824 snps,parkmode-disable-ss-quirk;
825 dma-coherent;
830 compatible = "rockchip,rk3576-sys-grf", "syscon";
835 compatible = "rockchip,rk3576-bigcore-grf", "syscon";
840 compatible = "rockchip,rk3576-litcore-grf", "syscon";
845 compatible = "rockchip,rk3576-cci-grf", "syscon";
850 compatible = "rockchip,rk3576-gpu-grf", "syscon";
855 compatible = "rockchip,rk3576-npu-grf", "syscon";
860 compatible = "rockchip,rk3576-vo0-grf", "syscon";
865 compatible = "rockchip,rk3576-usb-grf", "syscon";
870 compatible = "rockchip,rk3576-php-grf", "syscon";
875 compatible = "rockchip,rk3576-pmu0-grf", "syscon", "simple-mfd";
880 compatible = "rockchip,rk3576-pmu1-grf", "syscon";
885 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon";
890 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon";
895 compatible = "rockchip,rk3576-usbdpphy-grf", "syscon";
900 compatible = "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd";
902 #address-cells = <1>;
903 #size-cells = <1>;
905 u2phy0: usb2-phy@0 {
906 compatible = "rockchip,rk3576-usb2phy";
909 reset-names = "phy", "apb";
913 clock-names = "phyclk", "aclk", "aclk_slv";
914 clock-output-names = "usb480m_phy0";
915 #clock-cells = <0>;
918 u2phy0_otg: otg-port {
919 #phy-cells = <0>;
923 interrupt-names = "otg-bvalid", "otg-id", "linestate";
928 u2phy1: usb2-phy@2000 {
929 compatible = "rockchip,rk3576-usb2phy";
932 reset-names = "phy", "apb";
936 clock-names = "phyclk", "aclk", "aclk_slv";
937 clock-output-names = "usb480m_phy1";
938 #clock-cells = <0>;
941 u2phy1_otg: otg-port {
942 #phy-cells = <0>;
946 interrupt-names = "otg-bvalid", "otg-id", "linestate";
953 compatible = "rockchip,rk3576-hdptxphy-grf", "syscon";
958 compatible = "rockchip,rk3576-dcphy-grf", "syscon";
964 compatible = "rockchip,rk3576-vo1-grf", "syscon";
970 compatible = "rockchip,rk3576-sdgmac-grf", "syscon";
975 compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd";
979 cru: clock-controller@27200000 {
980 compatible = "rockchip,rk3576-cru";
982 #clock-cells = <1>;
983 #reset-cells = <1>;
985 assigned-clocks =
994 assigned-clock-parents = <&cru PLL_AUPLL>;
995 assigned-clock-rates =
1007 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1010 clock-names = "i2c", "pclk";
1012 pinctrl-names = "default";
1013 pinctrl-0 = <&i2c0m0_xfer>;
1014 #address-cells = <1>;
1015 #size-cells = <0>;
1020 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1022 reg-shift = <2>;
1023 reg-io-width = <4>;
1025 clock-names = "baudclk", "apb_pclk";
1028 pinctrl-names = "default";
1029 pinctrl-0 = <&uart1m0_xfer>;
1033 pmu: power-management@27380000 {
1034 compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd";
1037 power: power-controller {
1038 compatible = "rockchip,rk3576-power-controller";
1039 #power-domain-cells = <1>;
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1043 power-domain@RK3576_PD_NPU {
1045 #power-domain-cells = <1>;
1046 #address-cells = <1>;
1047 #size-cells = <0>;
1049 power-domain@RK3576_PD_NPUTOP {
1064 #power-domain-cells = <1>;
1065 #address-cells = <1>;
1066 #size-cells = <0>;
1068 power-domain@RK3576_PD_NPU0 {
1073 #power-domain-cells = <0>;
1075 power-domain@RK3576_PD_NPU1 {
1080 #power-domain-cells = <0>;
1085 power-domain@RK3576_PD_GPU {
1089 #power-domain-cells = <0>;
1092 power-domain@RK3576_PD_NVM {
1097 #power-domain-cells = <1>;
1098 #address-cells = <1>;
1099 #size-cells = <0>;
1101 power-domain@RK3576_PD_SDGMAC {
1118 #power-domain-cells = <0>;
1122 power-domain@RK3576_PD_PHP {
1130 #power-domain-cells = <1>;
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1134 power-domain@RK3576_PD_SUBPHP {
1136 #power-domain-cells = <0>;
1140 power-domain@RK3576_PD_AUDIO {
1142 #power-domain-cells = <0>;
1145 power-domain@RK3576_PD_VEPU1 {
1150 #power-domain-cells = <0>;
1153 power-domain@RK3576_PD_VPU {
1170 #power-domain-cells = <0>;
1173 power-domain@RK3576_PD_VDEC {
1178 #power-domain-cells = <0>;
1181 power-domain@RK3576_PD_VI {
1200 #power-domain-cells = <1>;
1201 #address-cells = <1>;
1202 #size-cells = <0>;
1204 power-domain@RK3576_PD_VEPU0 {
1209 #power-domain-cells = <0>;
1213 power-domain@RK3576_PD_VOP {
1221 #power-domain-cells = <1>;
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1225 power-domain@RK3576_PD_USB {
1234 #power-domain-cells = <0>;
1237 power-domain@RK3576_PD_VO0 {
1245 #power-domain-cells = <0>;
1248 power-domain@RK3576_PD_VO1 {
1256 #power-domain-cells = <0>;
1263 compatible = "rockchip,rk3576-mali", "arm,mali-bifrost";
1265 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
1266 assigned-clock-rates = <198000000>;
1268 clock-names = "core";
1269 dynamic-power-coefficient = <1625>;
1273 interrupt-names = "job", "mmu", "gpu";
1274 operating-points-v2 = <&gpu_opp_table>;
1275 power-domains = <&power RK3576_PD_GPU>;
1276 #cooling-cells = <2>;
1281 compatible = "rockchip,rk3576-vop";
1283 reg-names = "vop", "gamma-lut";
1288 interrupt-names = "sys",
1298 clock-names = "aclk",
1305 power-domains = <&power RK3576_PD_VOP>;
1311 #address-cells = <1>;
1312 #size-cells = <0>;
1315 #address-cells = <1>;
1316 #size-cells = <0>;
1321 #address-cells = <1>;
1322 #size-cells = <0>;
1327 #address-cells = <1>;
1328 #size-cells = <0>;
1335 compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu";
1339 clock-names = "aclk", "iface";
1340 #iommu-cells = <0>;
1341 power-domains = <&power RK3576_PD_VOP>;
1346 compatible = "rockchip,rk3576-sai";
1350 clock-names = "mclk", "hclk";
1352 dma-names = "rx";
1353 power-domains = <&power RK3576_PD_VO0>;
1355 reset-names = "m", "h";
1356 rockchip,sai-rx-route = <0 1 2 3>;
1357 #sound-dai-cells = <0>;
1358 sound-name-prefix = "SAI5";
1363 compatible = "rockchip,rk3576-sai";
1367 clock-names = "mclk", "hclk";
1369 dma-names = "tx", "rx";
1370 power-domains = <&power RK3576_PD_VO0>;
1372 reset-names = "m", "h";
1373 rockchip,sai-rx-route = <0 1 2 3>;
1374 rockchip,sai-tx-route = <0 1 2 3>;
1375 #sound-dai-cells = <0>;
1376 sound-name-prefix = "SAI6";
1381 compatible = "rockchip,rk3576-mipi-dsi2";
1385 clock-names = "pclk", "sys";
1386 power-domains = <&power RK3576_PD_VO0>;
1388 reset-names = "apb";
1390 phy-names = "dcphy";
1395 #address-cells = <1>;
1396 #size-cells = <0>;
1409 compatible = "rockchip,rk3576-dw-hdmi-qp";
1417 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
1423 interrupt-names = "avp", "cec", "earc", "main", "hpd";
1425 pinctrl-names = "default";
1426 pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>;
1427 power-domains = <&power RK3576_PD_VO0>;
1429 reset-names = "ref", "hdp";
1431 rockchip,vo-grf = <&vo0_grf>;
1432 #sound-dai-cells = <0>;
1436 #address-cells = <1>;
1437 #size-cells = <0>;
1450 compatible = "rockchip,rk3576-sai";
1454 clock-names = "mclk", "hclk";
1456 dma-names = "tx";
1457 power-domains = <&power RK3576_PD_VO1>;
1459 reset-names = "m", "h";
1460 rockchip,sai-tx-route = <0 1 2 3>;
1461 #sound-dai-cells = <0>;
1462 sound-name-prefix = "SAI7";
1467 compatible = "rockchip,rk3576-sai";
1471 clock-names = "mclk", "hclk";
1473 dma-names = "tx";
1474 power-domains = <&power RK3576_PD_VO1>;
1476 reset-names = "m", "h";
1477 rockchip,sai-tx-route = <0 1 2 3>;
1478 #sound-dai-cells = <0>;
1479 sound-name-prefix = "SAI8";
1484 compatible = "rockchip,rk3576-sai";
1488 clock-names = "mclk", "hclk";
1490 dma-names = "tx";
1491 power-domains = <&power RK3576_PD_VO1>;
1493 reset-names = "m", "h";
1494 rockchip,sai-tx-route = <0 1 2 3>;
1495 #sound-dai-cells = <0>;
1496 sound-name-prefix = "SAI9";
1501 compatible = "rockchip,rk3576-qos", "syscon";
1506 compatible = "rockchip,rk3576-qos", "syscon";
1511 compatible = "rockchip,rk3576-qos", "syscon";
1516 compatible = "rockchip,rk3576-qos", "syscon";
1521 compatible = "rockchip,rk3576-qos", "syscon";
1526 compatible = "rockchip,rk3576-qos", "syscon";
1531 compatible = "rockchip,rk3576-qos", "syscon";
1536 compatible = "rockchip,rk3576-qos", "syscon";
1541 compatible = "rockchip,rk3576-qos", "syscon";
1546 compatible = "rockchip,rk3576-qos", "syscon";
1551 compatible = "rockchip,rk3576-qos", "syscon";
1556 compatible = "rockchip,rk3576-qos", "syscon";
1561 compatible = "rockchip,rk3576-qos", "syscon";
1566 compatible = "rockchip,rk3576-qos", "syscon";
1571 compatible = "rockchip,rk3576-qos", "syscon";
1576 compatible = "rockchip,rk3576-qos", "syscon";
1581 compatible = "rockchip,rk3576-qos", "syscon";
1586 compatible = "rockchip,rk3576-qos", "syscon";
1591 compatible = "rockchip,rk3576-qos", "syscon";
1596 compatible = "rockchip,rk3576-qos", "syscon";
1601 compatible = "rockchip,rk3576-qos", "syscon";
1606 compatible = "rockchip,rk3576-qos", "syscon";
1611 compatible = "rockchip,rk3576-qos", "syscon";
1616 compatible = "rockchip,rk3576-qos", "syscon";
1621 compatible = "rockchip,rk3576-qos", "syscon";
1626 compatible = "rockchip,rk3576-qos", "syscon";
1631 compatible = "rockchip,rk3576-qos", "syscon";
1636 compatible = "rockchip,rk3576-qos", "syscon";
1641 compatible = "rockchip,rk3576-qos", "syscon";
1646 compatible = "rockchip,rk3576-qos", "syscon";
1651 compatible = "rockchip,rk3576-qos", "syscon";
1656 compatible = "rockchip,rk3576-qos", "syscon";
1661 compatible = "rockchip,rk3576-qos", "syscon";
1666 compatible = "rockchip,rk3576-qos", "syscon";
1671 compatible = "rockchip,rk3576-qos", "syscon";
1676 compatible = "rockchip,rk3576-qos", "syscon";
1681 compatible = "rockchip,rk3576-qos", "syscon";
1686 compatible = "rockchip,rk3576-qos", "syscon";
1691 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
1696 clock-names = "stmmaceth", "clk_mac_ref",
1701 interrupt-names = "macirq", "eth_wake_irq";
1702 power-domains = <&power RK3576_PD_SDGMAC>;
1704 reset-names = "stmmaceth";
1706 rockchip,php-grf = <&ioc_grf>;
1707 snps,axi-config = <&gmac0_stmmac_axi_setup>;
1708 snps,mixed-burst;
1709 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
1710 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
1715 compatible = "snps,dwmac-mdio";
1716 #address-cells = <0x1>;
1717 #size-cells = <0x0>;
1720 gmac0_stmmac_axi_setup: stmmac-axi-config {
1726 gmac0_mtl_rx_setup: rx-queues-config {
1727 snps,rx-queues-to-use = <1>;
1731 gmac0_mtl_tx_setup: tx-queues-config {
1732 snps,tx-queues-to-use = <1>;
1738 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
1743 clock-names = "stmmaceth", "clk_mac_ref",
1748 interrupt-names = "macirq", "eth_wake_irq";
1749 power-domains = <&power RK3576_PD_SDGMAC>;
1751 reset-names = "stmmaceth";
1753 rockchip,php-grf = <&ioc_grf>;
1754 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1755 snps,mixed-burst;
1756 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1757 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1762 compatible = "snps,dwmac-mdio";
1763 #address-cells = <0x1>;
1764 #size-cells = <0x0>;
1767 gmac1_stmmac_axi_setup: stmmac-axi-config {
1773 gmac1_mtl_rx_setup: rx-queues-config {
1774 snps,rx-queues-to-use = <1>;
1778 gmac1_mtl_tx_setup: tx-queues-config {
1779 snps,tx-queues-to-use = <1>;
1785 compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci";
1789 clock-names = "sata", "pmalive", "rxoob";
1791 power-domains = <&power RK3576_PD_SUBPHP>;
1793 phy-names = "sata-phy";
1794 ports-implemented = <0x1>;
1795 dma-coherent;
1800 compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci";
1804 clock-names = "sata", "pmalive", "rxoob";
1806 power-domains = <&power RK3576_PD_SUBPHP>;
1808 phy-names = "sata-phy";
1809 ports-implemented = <0x1>;
1810 dma-coherent;
1815 compatible = "rockchip,rk3576-ufshc";
1821 reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb";
1824 clock-names = "core", "pclk", "pclk_mphy", "ref_out";
1825 assigned-clocks = <&cru CLK_REF_OSC_MPHY>;
1826 assigned-clock-parents = <&cru CLK_REF_MPHY_26M>;
1828 power-domains = <&power RK3576_PD_USB>;
1829 pinctrl-0 = <&ufs_refclk>;
1830 pinctrl-names = "default";
1833 reset-names = "biu", "sys", "ufs", "grf";
1834 reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>;
1843 clock-names = "clk_sfc", "hclk_sfc";
1844 power-domains = <&power RK3576_PD_SDGMAC>;
1845 #address-cells = <1>;
1846 #size-cells = <0>;
1851 compatible = "rockchip,rk3576-dw-mshc";
1854 clock-names = "biu", "ciu";
1855 fifo-depth = <0x100>;
1857 max-frequency = <200000000>;
1858 pinctrl-names = "default";
1859 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4 &sdmmc0_pwren>;
1860 power-domains = <&power RK3576_PD_SDGMAC>;
1862 reset-names = "reset";
1867 compatible = "rockchip,rk3576-dw-mshc";
1870 clock-names = "biu", "ciu";
1871 fifo-depth = <0x100>;
1873 max-frequency = <200000000>;
1874 pinctrl-0 = <&sdmmc1m0_clk &sdmmc1m0_cmd &sdmmc1m0_bus4>;
1875 pinctrl-names = "default";
1876 power-domains = <&power RK3576_PD_SDGMAC>;
1878 reset-names = "reset";
1883 compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc";
1885 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>;
1886 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1890 clock-names = "core", "bus", "axi", "block", "timer";
1892 max-frequency = <200000000>;
1893 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1895 pinctrl-names = "default";
1896 power-domains = <&power RK3576_PD_NVM>;
1900 reset-names = "core", "bus", "axi", "block", "timer";
1901 supports-cqe;
1910 clock-names = "clk_sfc", "hclk_sfc";
1911 power-domains = <&power RK3576_PD_NVM>;
1912 #address-cells = <1>;
1913 #size-cells = <0>;
1918 compatible = "rockchip,rk3576-rng";
1926 compatible = "rockchip,rk3576-otp";
1928 #address-cells = <1>;
1929 #size-cells = <1>;
1932 clock-names = "otp", "apb_pclk", "phy";
1934 reset-names = "otp", "apb";
1937 cpu_code: cpu-code@2 {
1940 otp_cpu_version: cpu-version@5 {
1947 cpub_leakage: cpub-leakage@1e {
1950 cpul_leakage: cpul-leakage@1f {
1953 npu_leakage: npu-leakage@20 {
1956 gpu_leakage: gpu-leakage@21 {
1959 log_leakage: log-leakage@22 {
1962 bigcore_tsadc_trim: bigcore-tsadc-trim@24 {
1966 litcore_tsadc_trim: litcore-tsadc-trim@26 {
1970 ddr_tsadc_trim: ddr-tsadc-trim@28 {
1974 npu_tsadc_trim: npu-tsadc-trim@2a {
1978 gpu_tsadc_trim: gpu-tsadc-trim@2c {
1982 soc_tsadc_trim: soc-tsadc-trim@64 {
1989 compatible = "rockchip,rk3576-sai";
1993 clock-names = "mclk", "hclk";
1995 dma-names = "tx", "rx";
1996 power-domains = <&power RK3576_PD_AUDIO>;
1998 reset-names = "m", "h";
1999 pinctrl-names = "default";
2000 pinctrl-0 = <&sai0m0_lrck
2010 #sound-dai-cells = <0>;
2011 sound-name-prefix = "SAI0";
2016 compatible = "rockchip,rk3576-sai";
2020 clock-names = "mclk", "hclk";
2022 dma-names = "tx", "rx";
2023 power-domains = <&power RK3576_PD_AUDIO>;
2025 reset-names = "m", "h";
2026 pinctrl-names = "default";
2027 pinctrl-0 = <&sai1m0_lrck
2034 #sound-dai-cells = <0>;
2035 sound-name-prefix = "SAI1";
2040 compatible = "rockchip,rk3576-sai";
2044 clock-names = "mclk", "hclk";
2046 dma-names = "tx", "rx";
2047 power-domains = <&power RK3576_PD_AUDIO>;
2049 reset-names = "m", "h";
2050 pinctrl-names = "default";
2051 pinctrl-0 = <&sai2m0_lrck
2055 #sound-dai-cells = <0>;
2056 sound-name-prefix = "SAI2";
2061 compatible = "rockchip,rk3576-sai";
2065 clock-names = "mclk", "hclk";
2067 dma-names = "tx", "rx";
2068 power-domains = <&power RK3576_PD_AUDIO>;
2070 reset-names = "m", "h";
2071 pinctrl-names = "default";
2072 pinctrl-0 = <&sai3m0_lrck
2076 #sound-dai-cells = <0>;
2077 sound-name-prefix = "SAI3";
2082 compatible = "rockchip,rk3576-sai";
2086 clock-names = "mclk", "hclk";
2088 dma-names = "tx", "rx";
2089 power-domains = <&power RK3576_PD_AUDIO>;
2091 reset-names = "m", "h";
2092 pinctrl-names = "default";
2093 pinctrl-0 = <&sai4m0_lrck
2097 #sound-dai-cells = <0>;
2098 sound-name-prefix = "SAI4";
2102 gic: interrupt-controller@2a701000 {
2103 compatible = "arm,gic-400";
2109 interrupt-controller;
2110 #interrupt-cells = <3>;
2111 #address-cells = <2>;
2112 #size-cells = <2>;
2115 dmac0: dma-controller@2ab90000 {
2118 arm,pl330-periph-burst;
2120 clock-names = "apb_pclk";
2123 #dma-cells = <1>;
2126 dmac1: dma-controller@2abb0000 {
2129 arm,pl330-periph-burst;
2131 clock-names = "apb_pclk";
2134 #dma-cells = <1>;
2137 dmac2: dma-controller@2abd0000 {
2140 arm,pl330-periph-burst;
2142 clock-names = "apb_pclk";
2145 #dma-cells = <1>;
2149 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
2152 clock-names = "i2c", "pclk";
2154 pinctrl-names = "default";
2155 pinctrl-0 = <&i2c1m0_xfer>;
2156 #address-cells = <1>;
2157 #size-cells = <0>;
2162 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
2165 clock-names = "i2c", "pclk";
2167 pinctrl-names = "default";
2168 pinctrl-0 = <&i2c2m0_xfer>;
2169 #address-cells = <1>;
2170 #size-cells = <0>;
2175 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
2178 clock-names = "i2c", "pclk";
2180 pinctrl-names = "default";
2181 pinctrl-0 = <&i2c3m0_xfer>;
2182 #address-cells = <1>;
2183 #size-cells = <0>;
2188 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
2191 clock-names = "i2c", "pclk";
2193 pinctrl-names = "default";
2194 pinctrl-0 = <&i2c4m0_xfer>;
2195 #address-cells = <1>;
2196 #size-cells = <0>;
2201 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
2204 clock-names = "i2c", "pclk";
2206 pinctrl-names = "default";
2207 pinctrl-0 = <&i2c5m0_xfer>;
2208 #address-cells = <1>;
2209 #size-cells = <0>;
2214 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
2217 clock-names = "i2c", "pclk";
2219 pinctrl-names = "default";
2220 pinctrl-0 = <&i2c6m0_xfer>;
2221 #address-cells = <1>;
2222 #size-cells = <0>;
2227 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
2230 clock-names = "i2c", "pclk";
2232 pinctrl-names = "default";
2233 pinctrl-0 = <&i2c7m0_xfer>;
2234 #address-cells = <1>;
2235 #size-cells = <0>;
2240 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
2243 clock-names = "i2c", "pclk";
2245 pinctrl-names = "default";
2246 pinctrl-0 = <&i2c8m0_xfer>;
2247 #address-cells = <1>;
2248 #size-cells = <0>;
2253 compatible = "rockchip,rk3576-timer", "rockchip,rk3288-timer";
2256 clock-names = "pclk", "timer";
2261 compatible = "rockchip,rk3576-wdt", "snps,dw-wdt";
2264 clock-names = "tclk", "pclk";
2269 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
2272 clock-names = "spiclk", "apb_pclk";
2274 dma-names = "tx", "rx";
2276 num-cs = <2>;
2277 pinctrl-names = "default";
2278 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>;
2279 #address-cells = <1>;
2280 #size-cells = <0>;
2285 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
2288 clock-names = "spiclk", "apb_pclk";
2290 dma-names = "tx", "rx";
2292 num-cs = <2>;
2293 pinctrl-names = "default";
2294 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>;
2295 #address-cells = <1>;
2296 #size-cells = <0>;
2301 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
2304 clock-names = "spiclk", "apb_pclk";
2306 dma-names = "tx", "rx";
2308 num-cs = <2>;
2309 pinctrl-names = "default";
2310 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>;
2311 #address-cells = <1>;
2312 #size-cells = <0>;
2317 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
2320 clock-names = "spiclk", "apb_pclk";
2322 dma-names = "tx", "rx";
2324 num-cs = <2>;
2325 pinctrl-names = "default";
2326 pinctrl-0 = <&spi3m0_csn0 &spi3m0_csn1 &spi3m0_pins>;
2327 #address-cells = <1>;
2328 #size-cells = <0>;
2333 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
2336 clock-names = "spiclk", "apb_pclk";
2338 dma-names = "tx", "rx";
2340 num-cs = <2>;
2341 pinctrl-names = "default";
2342 pinctrl-0 = <&spi4m0_csn0 &spi4m0_csn1 &spi4m0_pins>;
2343 #address-cells = <1>;
2344 #size-cells = <0>;
2349 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2351 reg-shift = <2>;
2352 reg-io-width = <4>;
2354 clock-names = "baudclk", "apb_pclk";
2356 dma-names = "tx", "rx";
2358 pinctrl-0 = <&uart0m0_xfer>;
2359 pinctrl-names = "default";
2364 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2366 reg-shift = <2>;
2367 reg-io-width = <4>;
2369 clock-names = "baudclk", "apb_pclk";
2371 dma-names = "tx", "rx";
2373 pinctrl-names = "default";
2374 pinctrl-0 = <&uart2m0_xfer>;
2379 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2381 reg-shift = <2>;
2382 reg-io-width = <4>;
2384 clock-names = "baudclk", "apb_pclk";
2386 dma-names = "tx", "rx";
2388 pinctrl-0 = <&uart3m0_xfer>;
2389 pinctrl-names = "default";
2394 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2396 reg-shift = <2>;
2397 reg-io-width = <4>;
2399 clock-names = "baudclk", "apb_pclk";
2401 dma-names = "tx", "rx";
2403 pinctrl-0 = <&uart4m0_xfer>;
2404 pinctrl-names = "default";
2409 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2411 reg-shift = <2>;
2412 reg-io-width = <4>;
2414 clock-names = "baudclk", "apb_pclk";
2416 dma-names = "tx", "rx";
2418 pinctrl-0 = <&uart5m0_xfer>;
2419 pinctrl-names = "default";
2424 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2426 reg-shift = <2>;
2427 reg-io-width = <4>;
2429 clock-names = "baudclk", "apb_pclk";
2431 dma-names = "tx", "rx";
2433 pinctrl-0 = <&uart6m0_xfer>;
2434 pinctrl-names = "default";
2439 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2441 reg-shift = <2>;
2442 reg-io-width = <4>;
2444 clock-names = "baudclk", "apb_pclk";
2446 dma-names = "tx", "rx";
2448 pinctrl-0 = <&uart7m0_xfer>;
2449 pinctrl-names = "default";
2454 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2456 reg-shift = <2>;
2457 reg-io-width = <4>;
2459 clock-names = "baudclk", "apb_pclk";
2461 dma-names = "tx", "rx";
2463 pinctrl-0 = <&uart8m0_xfer>;
2464 pinctrl-names = "default";
2469 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2471 reg-shift = <2>;
2472 reg-io-width = <4>;
2474 clock-names = "baudclk", "apb_pclk";
2476 dma-names = "tx", "rx";
2478 pinctrl-0 = <&uart9m0_xfer>;
2479 pinctrl-names = "default";
2484 compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc";
2487 clock-names = "saradc", "apb_pclk";
2490 reset-names = "saradc-apb";
2491 #io-channel-cells = <1>;
2496 compatible = "rockchip,rk3576-tsadc";
2500 clock-names = "tsadc", "apb_pclk";
2501 assigned-clocks = <&cru CLK_TSADC>;
2502 assigned-clock-rates = <2000000>;
2504 reset-names = "tsadc-apb", "tsadc";
2505 #thermal-sensor-cells = <1>;
2506 rockchip,hw-tshut-temp = <120000>;
2507 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2508 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2509 #address-cells = <1>;
2510 #size-cells = <0>;
2514 nvmem-cells = <&soc_tsadc_trim>;
2515 nvmem-cell-names = "trim";
2519 nvmem-cells = <&bigcore_tsadc_trim>;
2520 nvmem-cell-names = "trim";
2524 nvmem-cells = <&litcore_tsadc_trim>;
2525 nvmem-cell-names = "trim";
2529 nvmem-cells = <&ddr_tsadc_trim>;
2530 nvmem-cell-names = "trim";
2534 nvmem-cells = <&npu_tsadc_trim>;
2535 nvmem-cell-names = "trim";
2539 nvmem-cells = <&gpu_tsadc_trim>;
2540 nvmem-cell-names = "trim";
2545 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
2548 clock-names = "i2c", "pclk";
2550 pinctrl-names = "default";
2551 pinctrl-0 = <&i2c9m0_xfer>;
2552 #address-cells = <1>;
2553 #size-cells = <0>;
2558 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2560 reg-shift = <2>;
2561 reg-io-width = <4>;
2563 clock-names = "baudclk", "apb_pclk";
2566 pinctrl-names = "default";
2567 pinctrl-0 = <&uart10m0_xfer>;
2572 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2574 reg-shift = <2>;
2575 reg-io-width = <4>;
2577 clock-names = "baudclk", "apb_pclk";
2580 pinctrl-names = "default";
2581 pinctrl-0 = <&uart11m0_xfer>;
2586 compatible = "rockchip,rk3576-mipi-dcphy";
2590 clock-names = "pclk", "ref";
2595 reset-names = "m_phy", "apb", "grf", "s_phy";
2597 #phy-cells = <1>;
2602 compatible = "rockchip,rk3576-naneng-combphy";
2604 #phy-cells = <1>;
2608 clock-names = "ref", "apb", "pipe";
2609 assigned-clocks = <&cru CLK_REF_PCIE0_PHY>;
2610 assigned-clock-rates = <100000000>;
2613 reset-names = "phy", "apb";
2614 rockchip,pipe-grf = <&php_grf>;
2615 rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
2620 compatible = "rockchip,rk3576-naneng-combphy";
2622 #phy-cells = <1>;
2626 clock-names = "ref", "apb", "pipe";
2627 assigned-clocks = <&cru CLK_REF_PCIE1_PHY>;
2628 assigned-clock-rates = <100000000>;
2631 reset-names = "phy", "apb";
2632 rockchip,pipe-grf = <&php_grf>;
2633 rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
2638 compatible = "rockchip,rk3576-usbdp-phy";
2640 #phy-cells = <1>;
2645 clock-names = "refclk", "immortal", "pclk", "utmi";
2651 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
2652 rockchip,u2phy-grf = <&usb2phy_grf>;
2653 rockchip,usb-grf = <&usb_grf>;
2654 rockchip,usbdpphy-grf = <&usbdpphy_grf>;
2655 rockchip,vo-grf = <&vo1_grf>;
2660 compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy";
2663 clock-names = "ref", "apb";
2664 #clock-cells = <0>;
2667 reset-names = "apb", "init", "cmn", "lane";
2669 #phy-cells = <0>;
2674 compatible = "mmio-sram";
2677 #address-cells = <1>;
2678 #size-cells = <1>;
2681 rkvdec_sram: rkvdec-sram@0 {
2686 scmi_shmem: scmi-shmem@4010f000 {
2687 compatible = "arm,scmi-shmem";
2693 #include "rk3576-pinctrl.dtsi"