Lines Matching +full:phy +full:- +full:grf
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3576-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rk3576-power.h>
12 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
52 xin32k: clock-xin32k {
53 compatible = "fixed-clock";
54 clock-frequency = <32768>;
55 clock-output-names = "xin32k";
56 #clock-cells = <0>;
59 xin24m: clock-xin24m {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <24000000>;
63 clock-output-names = "xin24m";
66 spll: clock-spll {
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <702000000>;
70 clock-output-names = "spll";
74 #address-cells = <1>;
75 #size-cells = <0>;
77 cpu-map {
110 compatible = "arm,cortex-a53";
112 enable-method = "psci";
113 capacity-dmips-mhz = <485>;
115 operating-points-v2 = <&cluster0_opp_table>;
116 #cooling-cells = <2>;
117 dynamic-power-coefficient = <120>;
118 cpu-idle-states = <&CPU_SLEEP>;
123 compatible = "arm,cortex-a53";
125 enable-method = "psci";
126 capacity-dmips-mhz = <485>;
128 operating-points-v2 = <&cluster0_opp_table>;
129 cpu-idle-states = <&CPU_SLEEP>;
134 compatible = "arm,cortex-a53";
136 enable-method = "psci";
137 capacity-dmips-mhz = <485>;
139 operating-points-v2 = <&cluster0_opp_table>;
140 cpu-idle-states = <&CPU_SLEEP>;
145 compatible = "arm,cortex-a53";
147 enable-method = "psci";
148 capacity-dmips-mhz = <485>;
150 operating-points-v2 = <&cluster0_opp_table>;
151 cpu-idle-states = <&CPU_SLEEP>;
156 compatible = "arm,cortex-a72";
158 enable-method = "psci";
159 capacity-dmips-mhz = <1024>;
161 operating-points-v2 = <&cluster1_opp_table>;
162 #cooling-cells = <2>;
163 dynamic-power-coefficient = <320>;
164 cpu-idle-states = <&CPU_SLEEP>;
169 compatible = "arm,cortex-a72";
171 enable-method = "psci";
172 capacity-dmips-mhz = <1024>;
174 operating-points-v2 = <&cluster1_opp_table>;
175 cpu-idle-states = <&CPU_SLEEP>;
180 compatible = "arm,cortex-a72";
182 enable-method = "psci";
183 capacity-dmips-mhz = <1024>;
185 operating-points-v2 = <&cluster1_opp_table>;
186 cpu-idle-states = <&CPU_SLEEP>;
191 compatible = "arm,cortex-a72";
193 enable-method = "psci";
194 capacity-dmips-mhz = <1024>;
196 operating-points-v2 = <&cluster1_opp_table>;
197 cpu-idle-states = <&CPU_SLEEP>;
200 idle-states {
201 entry-method = "psci";
203 CPU_SLEEP: cpu-sleep {
204 compatible = "arm,idle-state";
205 arm,psci-suspend-param = <0x0010000>;
206 entry-latency-us = <120>;
207 exit-latency-us = <250>;
208 min-residency-us = <900>;
209 local-timer-stop;
214 cluster0_opp_table: opp-table-cluster0 {
215 compatible = "operating-points-v2";
216 opp-shared;
218 opp-408000000 {
219 opp-hz = /bits/ 64 <408000000>;
220 opp-microvolt = <700000 700000 950000>;
221 clock-latency-ns = <40000>;
224 opp-600000000 {
225 opp-hz = /bits/ 64 <600000000>;
226 opp-microvolt = <700000 700000 950000>;
227 clock-latency-ns = <40000>;
230 opp-816000000 {
231 opp-hz = /bits/ 64 <816000000>;
232 opp-microvolt = <700000 700000 950000>;
233 clock-latency-ns = <40000>;
236 opp-1008000000 {
237 opp-hz = /bits/ 64 <1008000000>;
238 opp-microvolt = <700000 700000 950000>;
239 clock-latency-ns = <40000>;
242 opp-1200000000 {
243 opp-hz = /bits/ 64 <1200000000>;
244 opp-microvolt = <700000 700000 950000>;
245 clock-latency-ns = <40000>;
248 opp-1416000000 {
249 opp-hz = /bits/ 64 <1416000000>;
250 opp-microvolt = <725000 725000 950000>;
251 clock-latency-ns = <40000>;
254 opp-1608000000 {
255 opp-hz = /bits/ 64 <1608000000>;
256 opp-microvolt = <750000 750000 950000>;
257 clock-latency-ns = <40000>;
260 opp-1800000000 {
261 opp-hz = /bits/ 64 <1800000000>;
262 opp-microvolt = <825000 825000 950000>;
263 clock-latency-ns = <40000>;
264 opp-suspend;
267 opp-2016000000 {
268 opp-hz = /bits/ 64 <2016000000>;
269 opp-microvolt = <900000 900000 950000>;
270 clock-latency-ns = <40000>;
273 opp-2208000000 {
274 opp-hz = /bits/ 64 <2208000000>;
275 opp-microvolt = <950000 950000 950000>;
276 clock-latency-ns = <40000>;
280 cluster1_opp_table: opp-table-cluster1 {
281 compatible = "operating-points-v2";
282 opp-shared;
284 opp-408000000 {
285 opp-hz = /bits/ 64 <408000000>;
286 opp-microvolt = <700000 700000 950000>;
287 clock-latency-ns = <40000>;
288 opp-suspend;
291 opp-600000000 {
292 opp-hz = /bits/ 64 <600000000>;
293 opp-microvolt = <700000 700000 950000>;
294 clock-latency-ns = <40000>;
297 opp-816000000 {
298 opp-hz = /bits/ 64 <816000000>;
299 opp-microvolt = <700000 700000 950000>;
300 clock-latency-ns = <40000>;
303 opp-1008000000 {
304 opp-hz = /bits/ 64 <1008000000>;
305 opp-microvolt = <700000 700000 950000>;
306 clock-latency-ns = <40000>;
309 opp-1200000000 {
310 opp-hz = /bits/ 64 <1200000000>;
311 opp-microvolt = <700000 700000 950000>;
312 clock-latency-ns = <40000>;
315 opp-1416000000 {
316 opp-hz = /bits/ 64 <1416000000>;
317 opp-microvolt = <712500 712500 950000>;
318 clock-latency-ns = <40000>;
321 opp-1608000000 {
322 opp-hz = /bits/ 64 <1608000000>;
323 opp-microvolt = <737500 737500 950000>;
324 clock-latency-ns = <40000>;
327 opp-1800000000 {
328 opp-hz = /bits/ 64 <1800000000>;
329 opp-microvolt = <800000 800000 950000>;
330 clock-latency-ns = <40000>;
333 opp-2016000000 {
334 opp-hz = /bits/ 64 <2016000000>;
335 opp-microvolt = <862500 862500 950000>;
336 clock-latency-ns = <40000>;
339 opp-2208000000 {
340 opp-hz = /bits/ 64 <2208000000>;
341 opp-microvolt = <925000 925000 950000>;
342 clock-latency-ns = <40000>;
345 opp-2304000000 {
346 opp-hz = /bits/ 64 <2304000000>;
347 opp-microvolt = <950000 950000 950000>;
348 clock-latency-ns = <40000>;
352 gpu_opp_table: opp-table-gpu {
353 compatible = "operating-points-v2";
355 opp-300000000 {
356 opp-hz = /bits/ 64 <300000000>;
357 opp-microvolt = <700000 700000 850000>;
360 opp-400000000 {
361 opp-hz = /bits/ 64 <400000000>;
362 opp-microvolt = <700000 700000 850000>;
365 opp-500000000 {
366 opp-hz = /bits/ 64 <500000000>;
367 opp-microvolt = <700000 700000 850000>;
370 opp-600000000 {
371 opp-hz = /bits/ 64 <600000000>;
372 opp-microvolt = <700000 700000 850000>;
375 opp-700000000 {
376 opp-hz = /bits/ 64 <700000000>;
377 opp-microvolt = <725000 725000 850000>;
380 opp-800000000 {
381 opp-hz = /bits/ 64 <800000000>;
382 opp-microvolt = <775000 775000 850000>;
385 opp-900000000 {
386 opp-hz = /bits/ 64 <900000000>;
387 opp-microvolt = <825000 825000 850000>;
390 opp-950000000 {
391 opp-hz = /bits/ 64 <950000000>;
392 opp-microvolt = <850000 850000 850000>;
396 display_subsystem: display-subsystem {
397 compatible = "rockchip,display-subsystem";
403 compatible = "arm,scmi-smc";
404 arm,smc-id = <0x82000010>;
406 #address-cells = <1>;
407 #size-cells = <0>;
411 #clock-cells = <1>;
416 hdmi_sound: hdmi-sound {
417 compatible = "simple-audio-card";
418 simple-audio-card,name = "HDMI";
419 simple-audio-card,format = "i2s";
420 simple-audio-card,mclk-fs = <256>;
423 simple-audio-card,codec {
424 sound-dai = <&hdmi>;
427 simple-audio-card,cpu {
428 sound-dai = <&sai6>;
433 compatible = "rockchip,rk3576-pinctrl";
434 rockchip,grf = <&ioc_grf>;
435 #address-cells = <2>;
436 #size-cells = <2>;
440 compatible = "rockchip,gpio-bank";
443 gpio-controller;
444 gpio-ranges = <&pinctrl 0 0 32>;
446 interrupt-controller;
447 #gpio-cells = <2>;
448 #interrupt-cells = <2>;
452 compatible = "rockchip,gpio-bank";
455 gpio-controller;
456 gpio-ranges = <&pinctrl 0 32 32>;
458 interrupt-controller;
459 #gpio-cells = <2>;
460 #interrupt-cells = <2>;
464 compatible = "rockchip,gpio-bank";
467 gpio-controller;
468 gpio-ranges = <&pinctrl 0 64 32>;
470 interrupt-controller;
471 #gpio-cells = <2>;
472 #interrupt-cells = <2>;
476 compatible = "rockchip,gpio-bank";
479 gpio-controller;
480 gpio-ranges = <&pinctrl 0 96 32>;
482 interrupt-controller;
483 #gpio-cells = <2>;
484 #interrupt-cells = <2>;
488 compatible = "rockchip,gpio-bank";
491 gpio-controller;
492 gpio-ranges = <&pinctrl 0 128 32>;
494 interrupt-controller;
495 #gpio-cells = <2>;
496 #interrupt-cells = <2>;
500 pmu_a53: pmu-a53 {
501 compatible = "arm,cortex-a53-pmu";
506 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>;
509 pmu_a72: pmu-a72 {
510 compatible = "arm,cortex-a72-pmu";
515 interrupt-affinity = <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>;
519 compatible = "arm,psci-1.0";
524 compatible = "arm,armv8-timer";
532 compatible = "simple-bus";
533 #address-cells = <2>;
534 #size-cells = <2>;
538 compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
542 reg-names = "dbi", "apb", "config";
543 bus-range = <0x0 0xf>;
547 clock-names = "aclk_mst", "aclk_slv",
557 interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
558 #interrupt-cells = <1>;
559 interrupt-map-mask = <0 0 0 7>;
560 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
564 linux,pci-domain = <0>;
565 max-link-speed = <2>;
566 num-ib-windows = <8>;
567 num-viewport = <8>;
568 num-ob-windows = <2>;
569 num-lanes = <1>;
571 phy-names = "pcie-phy";
572 power-domains = <&power RK3576_PD_PHP>;
577 reset-names = "pwr", "pipe";
578 #address-cells = <3>;
579 #size-cells = <2>;
582 pcie0_intc: legacy-interrupt-controller {
583 interrupt-controller;
584 #address-cells = <0>;
585 #interrupt-cells = <1>;
586 interrupt-parent = <&gic>;
592 compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
596 reg-names = "dbi", "apb", "config";
597 bus-range = <0x20 0x2f>;
601 clock-names = "aclk_mst", "aclk_slv",
611 interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
612 #interrupt-cells = <1>;
613 interrupt-map-mask = <0 0 0 7>;
614 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
618 linux,pci-domain = <1>;
619 max-link-speed = <2>;
620 num-ib-windows = <8>;
621 num-viewport = <8>;
622 num-ob-windows = <2>;
623 num-lanes = <1>;
625 phy-names = "pcie-phy";
626 power-domains = <&power RK3576_PD_SUBPHP>;
631 reset-names = "pwr", "pipe";
632 #address-cells = <3>;
633 #size-cells = <2>;
636 pcie1_intc: legacy-interrupt-controller {
637 interrupt-controller;
638 #address-cells = <0>;
639 #interrupt-cells = <1>;
640 interrupt-parent = <&gic>;
646 compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
651 clock-names = "ref_clk", "suspend_clk", "bus_clk";
653 power-domains = <&power RK3576_PD_USB>;
657 phy-names = "usb2-phy", "usb3-phy";
660 snps,dis-u1-entry-quirk;
661 snps,dis-u2-entry-quirk;
662 snps,dis-u2-freeclk-exists-quirk;
663 snps,dis-del-phy-power-chg-quirk;
664 snps,dis-tx-ipgap-linecheck-quirk;
665 snps,parkmode-disable-hs-quirk;
666 snps,parkmode-disable-ss-quirk;
671 compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
676 clock-names = "ref_clk", "suspend_clk", "bus_clk";
678 power-domains = <&power RK3576_PD_PHP>;
682 phy-names = "usb2-phy", "usb3-phy";
685 snps,dis-u1-entry-quirk;
686 snps,dis-u2-entry-quirk;
687 snps,dis-u2-freeclk-exists-quirk;
688 snps,dis-del-phy-power-chg-quirk;
689 snps,dis-tx-ipgap-linecheck-quirk;
691 snps,parkmode-disable-hs-quirk;
692 snps,parkmode-disable-ss-quirk;
693 dma-coherent;
698 compatible = "rockchip,rk3576-sys-grf", "syscon";
703 compatible = "rockchip,rk3576-bigcore-grf", "syscon";
708 compatible = "rockchip,rk3576-litcore-grf", "syscon";
713 compatible = "rockchip,rk3576-cci-grf", "syscon";
718 compatible = "rockchip,rk3576-gpu-grf", "syscon";
723 compatible = "rockchip,rk3576-npu-grf", "syscon";
728 compatible = "rockchip,rk3576-vo0-grf", "syscon";
733 compatible = "rockchip,rk3576-usb-grf", "syscon";
738 compatible = "rockchip,rk3576-php-grf", "syscon";
743 compatible = "rockchip,rk3576-pmu0-grf", "syscon", "simple-mfd";
748 compatible = "rockchip,rk3576-pmu1-grf", "syscon";
753 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon";
758 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon";
763 compatible = "rockchip,rk3576-usbdpphy-grf", "syscon";
768 compatible = "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd";
770 #address-cells = <1>;
771 #size-cells = <1>;
773 u2phy0: usb2-phy@0 {
774 compatible = "rockchip,rk3576-usb2phy";
777 reset-names = "phy", "apb";
781 clock-names = "phyclk", "aclk", "aclk_slv";
782 clock-output-names = "usb480m_phy0";
783 #clock-cells = <0>;
786 u2phy0_otg: otg-port {
787 #phy-cells = <0>;
791 interrupt-names = "otg-bvalid", "otg-id", "linestate";
796 u2phy1: usb2-phy@2000 {
797 compatible = "rockchip,rk3576-usb2phy";
800 reset-names = "phy", "apb";
804 clock-names = "phyclk", "aclk", "aclk_slv";
805 clock-output-names = "usb480m_phy1";
806 #clock-cells = <0>;
809 u2phy1_otg: otg-port {
810 #phy-cells = <0>;
814 interrupt-names = "otg-bvalid", "otg-id", "linestate";
821 compatible = "rockchip,rk3576-hdptxphy-grf", "syscon";
826 compatible = "rockchip,rk3576-vo1-grf", "syscon";
832 compatible = "rockchip,rk3576-sdgmac-grf", "syscon";
837 compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd";
841 cru: clock-controller@27200000 {
842 compatible = "rockchip,rk3576-cru";
844 #clock-cells = <1>;
845 #reset-cells = <1>;
847 assigned-clocks =
856 assigned-clock-parents = <&cru PLL_AUPLL>;
857 assigned-clock-rates =
869 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
872 clock-names = "i2c", "pclk";
874 pinctrl-names = "default";
875 pinctrl-0 = <&i2c0m0_xfer>;
876 #address-cells = <1>;
877 #size-cells = <0>;
882 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
884 reg-shift = <2>;
885 reg-io-width = <4>;
887 clock-names = "baudclk", "apb_pclk";
890 pinctrl-names = "default";
891 pinctrl-0 = <&uart1m0_xfer>;
895 pmu: power-management@27380000 {
896 compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd";
899 power: power-controller {
900 compatible = "rockchip,rk3576-power-controller";
901 #power-domain-cells = <1>;
902 #address-cells = <1>;
903 #size-cells = <0>;
905 power-domain@RK3576_PD_NPU {
907 #power-domain-cells = <1>;
908 #address-cells = <1>;
909 #size-cells = <0>;
911 power-domain@RK3576_PD_NPUTOP {
926 #power-domain-cells = <1>;
927 #address-cells = <1>;
928 #size-cells = <0>;
930 power-domain@RK3576_PD_NPU0 {
935 #power-domain-cells = <0>;
937 power-domain@RK3576_PD_NPU1 {
942 #power-domain-cells = <0>;
947 power-domain@RK3576_PD_GPU {
951 #power-domain-cells = <0>;
954 power-domain@RK3576_PD_NVM {
959 #power-domain-cells = <1>;
960 #address-cells = <1>;
961 #size-cells = <0>;
963 power-domain@RK3576_PD_SDGMAC {
980 #power-domain-cells = <0>;
984 power-domain@RK3576_PD_PHP {
992 #power-domain-cells = <1>;
993 #address-cells = <1>;
994 #size-cells = <0>;
996 power-domain@RK3576_PD_SUBPHP {
998 #power-domain-cells = <0>;
1002 power-domain@RK3576_PD_AUDIO {
1004 #power-domain-cells = <0>;
1007 power-domain@RK3576_PD_VEPU1 {
1012 #power-domain-cells = <0>;
1015 power-domain@RK3576_PD_VPU {
1032 #power-domain-cells = <0>;
1035 power-domain@RK3576_PD_VDEC {
1040 #power-domain-cells = <0>;
1043 power-domain@RK3576_PD_VI {
1062 #power-domain-cells = <1>;
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1066 power-domain@RK3576_PD_VEPU0 {
1071 #power-domain-cells = <0>;
1075 power-domain@RK3576_PD_VOP {
1083 #power-domain-cells = <1>;
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1087 power-domain@RK3576_PD_USB {
1096 #power-domain-cells = <0>;
1099 power-domain@RK3576_PD_VO0 {
1107 #power-domain-cells = <0>;
1110 power-domain@RK3576_PD_VO1 {
1118 #power-domain-cells = <0>;
1125 compatible = "rockchip,rk3576-mali", "arm,mali-bifrost";
1127 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
1128 assigned-clock-rates = <198000000>;
1130 clock-names = "core";
1131 dynamic-power-coefficient = <1625>;
1135 interrupt-names = "job", "mmu", "gpu";
1136 operating-points-v2 = <&gpu_opp_table>;
1137 power-domains = <&power RK3576_PD_GPU>;
1138 #cooling-cells = <2>;
1143 compatible = "rockchip,rk3576-vop";
1145 reg-names = "vop", "gamma-lut";
1150 interrupt-names = "sys",
1160 clock-names = "aclk",
1167 power-domains = <&power RK3576_PD_VOP>;
1168 rockchip,grf = <&sys_grf>;
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1177 #address-cells = <1>;
1178 #size-cells = <0>;
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1189 #address-cells = <1>;
1190 #size-cells = <0>;
1197 compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu";
1201 clock-names = "aclk", "iface";
1202 #iommu-cells = <0>;
1203 power-domains = <&power RK3576_PD_VOP>;
1208 compatible = "rockchip,rk3576-sai";
1212 clock-names = "mclk", "hclk";
1214 dma-names = "rx";
1215 power-domains = <&power RK3576_PD_VO0>;
1217 reset-names = "m", "h";
1218 rockchip,sai-rx-route = <0 1 2 3>;
1219 #sound-dai-cells = <0>;
1220 sound-name-prefix = "SAI5";
1225 compatible = "rockchip,rk3576-sai";
1229 clock-names = "mclk", "hclk";
1231 dma-names = "tx", "rx";
1232 power-domains = <&power RK3576_PD_VO0>;
1234 reset-names = "m", "h";
1235 rockchip,sai-rx-route = <0 1 2 3>;
1236 rockchip,sai-tx-route = <0 1 2 3>;
1237 #sound-dai-cells = <0>;
1238 sound-name-prefix = "SAI6";
1243 compatible = "rockchip,rk3576-dw-hdmi-qp";
1251 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
1257 interrupt-names = "avp", "cec", "earc", "main", "hpd";
1259 pinctrl-names = "default";
1260 pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>;
1261 power-domains = <&power RK3576_PD_VO0>;
1263 reset-names = "ref", "hdp";
1264 rockchip,grf = <&ioc_grf>;
1265 rockchip,vo-grf = <&vo0_grf>;
1266 #sound-dai-cells = <0>;
1270 #address-cells = <1>;
1271 #size-cells = <0>;
1284 compatible = "rockchip,rk3576-sai";
1288 clock-names = "mclk", "hclk";
1290 dma-names = "tx";
1291 power-domains = <&power RK3576_PD_VO1>;
1293 reset-names = "m", "h";
1294 rockchip,sai-tx-route = <0 1 2 3>;
1295 #sound-dai-cells = <0>;
1296 sound-name-prefix = "SAI7";
1301 compatible = "rockchip,rk3576-sai";
1305 clock-names = "mclk", "hclk";
1307 dma-names = "tx";
1308 power-domains = <&power RK3576_PD_VO1>;
1310 reset-names = "m", "h";
1311 rockchip,sai-tx-route = <0 1 2 3>;
1312 #sound-dai-cells = <0>;
1313 sound-name-prefix = "SAI8";
1318 compatible = "rockchip,rk3576-sai";
1322 clock-names = "mclk", "hclk";
1324 dma-names = "tx";
1325 power-domains = <&power RK3576_PD_VO1>;
1327 reset-names = "m", "h";
1328 rockchip,sai-tx-route = <0 1 2 3>;
1329 #sound-dai-cells = <0>;
1330 sound-name-prefix = "SAI9";
1335 compatible = "rockchip,rk3576-qos", "syscon";
1340 compatible = "rockchip,rk3576-qos", "syscon";
1345 compatible = "rockchip,rk3576-qos", "syscon";
1350 compatible = "rockchip,rk3576-qos", "syscon";
1355 compatible = "rockchip,rk3576-qos", "syscon";
1360 compatible = "rockchip,rk3576-qos", "syscon";
1365 compatible = "rockchip,rk3576-qos", "syscon";
1370 compatible = "rockchip,rk3576-qos", "syscon";
1375 compatible = "rockchip,rk3576-qos", "syscon";
1380 compatible = "rockchip,rk3576-qos", "syscon";
1385 compatible = "rockchip,rk3576-qos", "syscon";
1390 compatible = "rockchip,rk3576-qos", "syscon";
1395 compatible = "rockchip,rk3576-qos", "syscon";
1400 compatible = "rockchip,rk3576-qos", "syscon";
1405 compatible = "rockchip,rk3576-qos", "syscon";
1410 compatible = "rockchip,rk3576-qos", "syscon";
1415 compatible = "rockchip,rk3576-qos", "syscon";
1420 compatible = "rockchip,rk3576-qos", "syscon";
1425 compatible = "rockchip,rk3576-qos", "syscon";
1430 compatible = "rockchip,rk3576-qos", "syscon";
1435 compatible = "rockchip,rk3576-qos", "syscon";
1440 compatible = "rockchip,rk3576-qos", "syscon";
1445 compatible = "rockchip,rk3576-qos", "syscon";
1450 compatible = "rockchip,rk3576-qos", "syscon";
1455 compatible = "rockchip,rk3576-qos", "syscon";
1460 compatible = "rockchip,rk3576-qos", "syscon";
1465 compatible = "rockchip,rk3576-qos", "syscon";
1470 compatible = "rockchip,rk3576-qos", "syscon";
1475 compatible = "rockchip,rk3576-qos", "syscon";
1480 compatible = "rockchip,rk3576-qos", "syscon";
1485 compatible = "rockchip,rk3576-qos", "syscon";
1490 compatible = "rockchip,rk3576-qos", "syscon";
1495 compatible = "rockchip,rk3576-qos", "syscon";
1500 compatible = "rockchip,rk3576-qos", "syscon";
1505 compatible = "rockchip,rk3576-qos", "syscon";
1510 compatible = "rockchip,rk3576-qos", "syscon";
1515 compatible = "rockchip,rk3576-qos", "syscon";
1520 compatible = "rockchip,rk3576-qos", "syscon";
1525 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
1530 clock-names = "stmmaceth", "clk_mac_ref",
1535 interrupt-names = "macirq", "eth_wake_irq";
1536 power-domains = <&power RK3576_PD_SDGMAC>;
1538 reset-names = "stmmaceth";
1539 rockchip,grf = <&sdgmac_grf>;
1540 rockchip,php-grf = <&ioc_grf>;
1541 snps,axi-config = <&gmac0_stmmac_axi_setup>;
1542 snps,mixed-burst;
1543 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
1544 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
1549 compatible = "snps,dwmac-mdio";
1550 #address-cells = <0x1>;
1551 #size-cells = <0x0>;
1554 gmac0_stmmac_axi_setup: stmmac-axi-config {
1560 gmac0_mtl_rx_setup: rx-queues-config {
1561 snps,rx-queues-to-use = <1>;
1565 gmac0_mtl_tx_setup: tx-queues-config {
1566 snps,tx-queues-to-use = <1>;
1572 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
1577 clock-names = "stmmaceth", "clk_mac_ref",
1582 interrupt-names = "macirq", "eth_wake_irq";
1583 power-domains = <&power RK3576_PD_SDGMAC>;
1585 reset-names = "stmmaceth";
1586 rockchip,grf = <&sdgmac_grf>;
1587 rockchip,php-grf = <&ioc_grf>;
1588 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1589 snps,mixed-burst;
1590 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1591 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1596 compatible = "snps,dwmac-mdio";
1597 #address-cells = <0x1>;
1598 #size-cells = <0x0>;
1601 gmac1_stmmac_axi_setup: stmmac-axi-config {
1607 gmac1_mtl_rx_setup: rx-queues-config {
1608 snps,rx-queues-to-use = <1>;
1612 gmac1_mtl_tx_setup: tx-queues-config {
1613 snps,tx-queues-to-use = <1>;
1619 compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci";
1623 clock-names = "sata", "pmalive", "rxoob";
1625 power-domains = <&power RK3576_PD_SUBPHP>;
1627 phy-names = "sata-phy";
1628 ports-implemented = <0x1>;
1629 dma-coherent;
1634 compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci";
1638 clock-names = "sata", "pmalive", "rxoob";
1640 power-domains = <&power RK3576_PD_SUBPHP>;
1642 phy-names = "sata-phy";
1643 ports-implemented = <0x1>;
1644 dma-coherent;
1649 compatible = "rockchip,rk3576-ufshc";
1655 reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb";
1658 clock-names = "core", "pclk", "pclk_mphy", "ref_out";
1659 assigned-clocks = <&cru CLK_REF_OSC_MPHY>;
1660 assigned-clock-parents = <&cru CLK_REF_MPHY_26M>;
1662 power-domains = <&power RK3576_PD_USB>;
1663 pinctrl-0 = <&ufs_refclk>;
1664 pinctrl-names = "default";
1667 reset-names = "biu", "sys", "ufs", "grf";
1668 reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>;
1677 clock-names = "clk_sfc", "hclk_sfc";
1678 power-domains = <&power RK3576_PD_SDGMAC>;
1679 #address-cells = <1>;
1680 #size-cells = <0>;
1685 compatible = "rockchip,rk3576-dw-mshc";
1688 clock-names = "biu", "ciu";
1689 fifo-depth = <0x100>;
1691 max-frequency = <200000000>;
1692 pinctrl-names = "default";
1693 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4 &sdmmc0_pwren>;
1694 power-domains = <&power RK3576_PD_SDGMAC>;
1696 reset-names = "reset";
1701 compatible = "rockchip,rk3576-dw-mshc";
1704 clock-names = "biu", "ciu";
1705 fifo-depth = <0x100>;
1707 max-frequency = <200000000>;
1708 pinctrl-0 = <&sdmmc1m0_clk &sdmmc1m0_cmd &sdmmc1m0_bus4>;
1709 pinctrl-names = "default";
1710 power-domains = <&power RK3576_PD_SDGMAC>;
1712 reset-names = "reset";
1717 compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc";
1719 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>;
1720 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1724 clock-names = "core", "bus", "axi", "block", "timer";
1726 max-frequency = <200000000>;
1727 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1729 pinctrl-names = "default";
1730 power-domains = <&power RK3576_PD_NVM>;
1734 reset-names = "core", "bus", "axi", "block", "timer";
1735 supports-cqe;
1744 clock-names = "clk_sfc", "hclk_sfc";
1745 power-domains = <&power RK3576_PD_NVM>;
1746 #address-cells = <1>;
1747 #size-cells = <0>;
1752 compatible = "rockchip,rk3576-rng";
1760 compatible = "rockchip,rk3576-otp";
1762 #address-cells = <1>;
1763 #size-cells = <1>;
1766 clock-names = "otp", "apb_pclk", "phy";
1768 reset-names = "otp", "apb";
1771 cpu_code: cpu-code@2 {
1774 otp_cpu_version: cpu-version@5 {
1781 cpub_leakage: cpub-leakage@1e {
1784 cpul_leakage: cpul-leakage@1f {
1787 npu_leakage: npu-leakage@20 {
1790 gpu_leakage: gpu-leakage@21 {
1793 log_leakage: log-leakage@22 {
1799 compatible = "rockchip,rk3576-sai";
1803 clock-names = "mclk", "hclk";
1805 dma-names = "tx", "rx";
1806 power-domains = <&power RK3576_PD_AUDIO>;
1808 reset-names = "m", "h";
1809 pinctrl-names = "default";
1810 pinctrl-0 = <&sai0m0_lrck
1820 #sound-dai-cells = <0>;
1821 sound-name-prefix = "SAI0";
1826 compatible = "rockchip,rk3576-sai";
1830 clock-names = "mclk", "hclk";
1832 dma-names = "tx", "rx";
1833 power-domains = <&power RK3576_PD_AUDIO>;
1835 reset-names = "m", "h";
1836 pinctrl-names = "default";
1837 pinctrl-0 = <&sai1m0_lrck
1844 #sound-dai-cells = <0>;
1845 sound-name-prefix = "SAI1";
1850 compatible = "rockchip,rk3576-sai";
1854 clock-names = "mclk", "hclk";
1856 dma-names = "tx", "rx";
1857 power-domains = <&power RK3576_PD_AUDIO>;
1859 reset-names = "m", "h";
1860 pinctrl-names = "default";
1861 pinctrl-0 = <&sai2m0_lrck
1865 #sound-dai-cells = <0>;
1866 sound-name-prefix = "SAI2";
1871 compatible = "rockchip,rk3576-sai";
1875 clock-names = "mclk", "hclk";
1877 dma-names = "tx", "rx";
1878 power-domains = <&power RK3576_PD_AUDIO>;
1880 reset-names = "m", "h";
1881 pinctrl-names = "default";
1882 pinctrl-0 = <&sai3m0_lrck
1886 #sound-dai-cells = <0>;
1887 sound-name-prefix = "SAI3";
1892 compatible = "rockchip,rk3576-sai";
1896 clock-names = "mclk", "hclk";
1898 dma-names = "tx", "rx";
1899 power-domains = <&power RK3576_PD_AUDIO>;
1901 reset-names = "m", "h";
1902 pinctrl-names = "default";
1903 pinctrl-0 = <&sai4m0_lrck
1907 #sound-dai-cells = <0>;
1908 sound-name-prefix = "SAI4";
1912 gic: interrupt-controller@2a701000 {
1913 compatible = "arm,gic-400";
1919 interrupt-controller;
1920 #interrupt-cells = <3>;
1921 #address-cells = <2>;
1922 #size-cells = <2>;
1925 dmac0: dma-controller@2ab90000 {
1928 arm,pl330-periph-burst;
1930 clock-names = "apb_pclk";
1933 #dma-cells = <1>;
1936 dmac1: dma-controller@2abb0000 {
1939 arm,pl330-periph-burst;
1941 clock-names = "apb_pclk";
1944 #dma-cells = <1>;
1947 dmac2: dma-controller@2abd0000 {
1950 arm,pl330-periph-burst;
1952 clock-names = "apb_pclk";
1955 #dma-cells = <1>;
1959 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1962 clock-names = "i2c", "pclk";
1964 pinctrl-names = "default";
1965 pinctrl-0 = <&i2c1m0_xfer>;
1966 #address-cells = <1>;
1967 #size-cells = <0>;
1972 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1975 clock-names = "i2c", "pclk";
1977 pinctrl-names = "default";
1978 pinctrl-0 = <&i2c2m0_xfer>;
1979 #address-cells = <1>;
1980 #size-cells = <0>;
1985 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1988 clock-names = "i2c", "pclk";
1990 pinctrl-names = "default";
1991 pinctrl-0 = <&i2c3m0_xfer>;
1992 #address-cells = <1>;
1993 #size-cells = <0>;
1998 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
2001 clock-names = "i2c", "pclk";
2003 pinctrl-names = "default";
2004 pinctrl-0 = <&i2c4m0_xfer>;
2005 #address-cells = <1>;
2006 #size-cells = <0>;
2011 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
2014 clock-names = "i2c", "pclk";
2016 pinctrl-names = "default";
2017 pinctrl-0 = <&i2c5m0_xfer>;
2018 #address-cells = <1>;
2019 #size-cells = <0>;
2024 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
2027 clock-names = "i2c", "pclk";
2029 pinctrl-names = "default";
2030 pinctrl-0 = <&i2c6m0_xfer>;
2031 #address-cells = <1>;
2032 #size-cells = <0>;
2037 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
2040 clock-names = "i2c", "pclk";
2042 pinctrl-names = "default";
2043 pinctrl-0 = <&i2c7m0_xfer>;
2044 #address-cells = <1>;
2045 #size-cells = <0>;
2050 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
2053 clock-names = "i2c", "pclk";
2055 pinctrl-names = "default";
2056 pinctrl-0 = <&i2c8m0_xfer>;
2057 #address-cells = <1>;
2058 #size-cells = <0>;
2063 compatible = "rockchip,rk3576-timer", "rockchip,rk3288-timer";
2066 clock-names = "pclk", "timer";
2071 compatible = "rockchip,rk3576-wdt", "snps,dw-wdt";
2074 clock-names = "tclk", "pclk";
2080 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
2083 clock-names = "spiclk", "apb_pclk";
2085 dma-names = "tx", "rx";
2087 num-cs = <2>;
2088 pinctrl-names = "default";
2089 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>;
2090 #address-cells = <1>;
2091 #size-cells = <0>;
2096 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
2099 clock-names = "spiclk", "apb_pclk";
2101 dma-names = "tx", "rx";
2103 num-cs = <2>;
2104 pinctrl-names = "default";
2105 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>;
2106 #address-cells = <1>;
2107 #size-cells = <0>;
2112 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
2115 clock-names = "spiclk", "apb_pclk";
2117 dma-names = "tx", "rx";
2119 num-cs = <2>;
2120 pinctrl-names = "default";
2121 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>;
2122 #address-cells = <1>;
2123 #size-cells = <0>;
2128 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
2131 clock-names = "spiclk", "apb_pclk";
2133 dma-names = "tx", "rx";
2135 num-cs = <2>;
2136 pinctrl-names = "default";
2137 pinctrl-0 = <&spi3m0_csn0 &spi3m0_csn1 &spi3m0_pins>;
2138 #address-cells = <1>;
2139 #size-cells = <0>;
2144 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
2147 clock-names = "spiclk", "apb_pclk";
2149 dma-names = "tx", "rx";
2151 num-cs = <2>;
2152 pinctrl-names = "default";
2153 pinctrl-0 = <&spi4m0_csn0 &spi4m0_csn1 &spi4m0_pins>;
2154 #address-cells = <1>;
2155 #size-cells = <0>;
2160 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2162 reg-shift = <2>;
2163 reg-io-width = <4>;
2165 clock-names = "baudclk", "apb_pclk";
2167 dma-names = "tx", "rx";
2169 pinctrl-0 = <&uart0m0_xfer>;
2170 pinctrl-names = "default";
2175 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2177 reg-shift = <2>;
2178 reg-io-width = <4>;
2180 clock-names = "baudclk", "apb_pclk";
2182 dma-names = "tx", "rx";
2184 pinctrl-names = "default";
2185 pinctrl-0 = <&uart2m0_xfer>;
2190 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2192 reg-shift = <2>;
2193 reg-io-width = <4>;
2195 clock-names = "baudclk", "apb_pclk";
2197 dma-names = "tx", "rx";
2199 pinctrl-0 = <&uart3m0_xfer>;
2200 pinctrl-names = "default";
2205 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2207 reg-shift = <2>;
2208 reg-io-width = <4>;
2210 clock-names = "baudclk", "apb_pclk";
2212 dma-names = "tx", "rx";
2214 pinctrl-0 = <&uart4m0_xfer>;
2215 pinctrl-names = "default";
2220 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2222 reg-shift = <2>;
2223 reg-io-width = <4>;
2225 clock-names = "baudclk", "apb_pclk";
2227 dma-names = "tx", "rx";
2229 pinctrl-0 = <&uart5m0_xfer>;
2230 pinctrl-names = "default";
2235 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2237 reg-shift = <2>;
2238 reg-io-width = <4>;
2240 clock-names = "baudclk", "apb_pclk";
2242 dma-names = "tx", "rx";
2244 pinctrl-0 = <&uart6m0_xfer>;
2245 pinctrl-names = "default";
2250 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2252 reg-shift = <2>;
2253 reg-io-width = <4>;
2255 clock-names = "baudclk", "apb_pclk";
2257 dma-names = "tx", "rx";
2259 pinctrl-0 = <&uart7m0_xfer>;
2260 pinctrl-names = "default";
2265 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2267 reg-shift = <2>;
2268 reg-io-width = <4>;
2270 clock-names = "baudclk", "apb_pclk";
2272 dma-names = "tx", "rx";
2274 pinctrl-0 = <&uart8m0_xfer>;
2275 pinctrl-names = "default";
2280 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2282 reg-shift = <2>;
2283 reg-io-width = <4>;
2285 clock-names = "baudclk", "apb_pclk";
2287 dma-names = "tx", "rx";
2289 pinctrl-0 = <&uart9m0_xfer>;
2290 pinctrl-names = "default";
2295 compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc";
2298 clock-names = "saradc", "apb_pclk";
2301 reset-names = "saradc-apb";
2302 #io-channel-cells = <1>;
2307 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
2310 clock-names = "i2c", "pclk";
2312 pinctrl-names = "default";
2313 pinctrl-0 = <&i2c9m0_xfer>;
2315 reset-names = "i2c", "apb";
2316 #address-cells = <1>;
2317 #size-cells = <0>;
2322 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2324 reg-shift = <2>;
2325 reg-io-width = <4>;
2327 clock-names = "baudclk", "apb_pclk";
2330 pinctrl-names = "default";
2331 pinctrl-0 = <&uart10m0_xfer>;
2336 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2338 reg-shift = <2>;
2339 reg-io-width = <4>;
2341 clock-names = "baudclk", "apb_pclk";
2344 pinctrl-names = "default";
2345 pinctrl-0 = <&uart11m0_xfer>;
2349 combphy0_ps: phy@2b050000 {
2350 compatible = "rockchip,rk3576-naneng-combphy";
2352 #phy-cells = <1>;
2356 clock-names = "ref", "apb", "pipe";
2357 assigned-clocks = <&cru CLK_REF_PCIE0_PHY>;
2358 assigned-clock-rates = <100000000>;
2361 reset-names = "phy", "apb";
2362 rockchip,pipe-grf = <&php_grf>;
2363 rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
2367 combphy1_psu: phy@2b060000 {
2368 compatible = "rockchip,rk3576-naneng-combphy";
2370 #phy-cells = <1>;
2374 clock-names = "ref", "apb", "pipe";
2375 assigned-clocks = <&cru CLK_REF_PCIE1_PHY>;
2376 assigned-clock-rates = <100000000>;
2379 reset-names = "phy", "apb";
2380 rockchip,pipe-grf = <&php_grf>;
2381 rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
2385 usbdp_phy: phy@2b010000 {
2386 compatible = "rockchip,rk3576-usbdp-phy";
2388 #phy-cells = <1>;
2393 clock-names = "refclk", "immortal", "pclk", "utmi";
2399 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
2400 rockchip,u2phy-grf = <&usb2phy_grf>;
2401 rockchip,usb-grf = <&usb_grf>;
2402 rockchip,usbdpphy-grf = <&usbdpphy_grf>;
2403 rockchip,vo-grf = <&vo1_grf>;
2408 compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy";
2411 clock-names = "ref", "apb";
2412 #clock-cells = <0>;
2415 reset-names = "apb", "init", "cmn", "lane";
2416 rockchip,grf = <&hdptxphy_grf>;
2417 #phy-cells = <0>;
2422 compatible = "mmio-sram";
2425 #address-cells = <1>;
2426 #size-cells = <1>;
2429 rkvdec_sram: rkvdec-sram@0 {
2434 scmi_shmem: scmi-shmem@4010f000 {
2435 compatible = "arm,scmi-shmem";
2441 #include "rk3576-pinctrl.dtsi"