Lines Matching +full:num +full:- +full:tx +full:- +full:queues
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3576-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rk3576-power.h>
12 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
52 xin32k: clock-xin32k {
53 compatible = "fixed-clock";
54 clock-frequency = <32768>;
55 clock-output-names = "xin32k";
56 #clock-cells = <0>;
59 xin24m: clock-xin24m {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <24000000>;
63 clock-output-names = "xin24m";
66 spll: clock-spll {
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <702000000>;
70 clock-output-names = "spll";
74 #address-cells = <1>;
75 #size-cells = <0>;
77 cpu-map {
110 compatible = "arm,cortex-a53";
112 enable-method = "psci";
113 capacity-dmips-mhz = <485>;
115 operating-points-v2 = <&cluster0_opp_table>;
116 #cooling-cells = <2>;
117 dynamic-power-coefficient = <120>;
118 cpu-idle-states = <&CPU_SLEEP>;
123 compatible = "arm,cortex-a53";
125 enable-method = "psci";
126 capacity-dmips-mhz = <485>;
128 operating-points-v2 = <&cluster0_opp_table>;
129 cpu-idle-states = <&CPU_SLEEP>;
134 compatible = "arm,cortex-a53";
136 enable-method = "psci";
137 capacity-dmips-mhz = <485>;
139 operating-points-v2 = <&cluster0_opp_table>;
140 cpu-idle-states = <&CPU_SLEEP>;
145 compatible = "arm,cortex-a53";
147 enable-method = "psci";
148 capacity-dmips-mhz = <485>;
150 operating-points-v2 = <&cluster0_opp_table>;
151 cpu-idle-states = <&CPU_SLEEP>;
156 compatible = "arm,cortex-a72";
158 enable-method = "psci";
159 capacity-dmips-mhz = <1024>;
161 operating-points-v2 = <&cluster1_opp_table>;
162 #cooling-cells = <2>;
163 dynamic-power-coefficient = <320>;
164 cpu-idle-states = <&CPU_SLEEP>;
169 compatible = "arm,cortex-a72";
171 enable-method = "psci";
172 capacity-dmips-mhz = <1024>;
174 operating-points-v2 = <&cluster1_opp_table>;
175 cpu-idle-states = <&CPU_SLEEP>;
180 compatible = "arm,cortex-a72";
182 enable-method = "psci";
183 capacity-dmips-mhz = <1024>;
185 operating-points-v2 = <&cluster1_opp_table>;
186 cpu-idle-states = <&CPU_SLEEP>;
191 compatible = "arm,cortex-a72";
193 enable-method = "psci";
194 capacity-dmips-mhz = <1024>;
196 operating-points-v2 = <&cluster1_opp_table>;
197 cpu-idle-states = <&CPU_SLEEP>;
200 idle-states {
201 entry-method = "psci";
203 CPU_SLEEP: cpu-sleep {
204 compatible = "arm,idle-state";
205 arm,psci-suspend-param = <0x0010000>;
206 entry-latency-us = <120>;
207 exit-latency-us = <250>;
208 min-residency-us = <900>;
209 local-timer-stop;
214 cluster0_opp_table: opp-table-cluster0 {
215 compatible = "operating-points-v2";
216 opp-shared;
218 opp-408000000 {
219 opp-hz = /bits/ 64 <408000000>;
220 opp-microvolt = <700000 700000 950000>;
221 clock-latency-ns = <40000>;
224 opp-600000000 {
225 opp-hz = /bits/ 64 <600000000>;
226 opp-microvolt = <700000 700000 950000>;
227 clock-latency-ns = <40000>;
230 opp-816000000 {
231 opp-hz = /bits/ 64 <816000000>;
232 opp-microvolt = <700000 700000 950000>;
233 clock-latency-ns = <40000>;
236 opp-1008000000 {
237 opp-hz = /bits/ 64 <1008000000>;
238 opp-microvolt = <700000 700000 950000>;
239 clock-latency-ns = <40000>;
242 opp-1200000000 {
243 opp-hz = /bits/ 64 <1200000000>;
244 opp-microvolt = <700000 700000 950000>;
245 clock-latency-ns = <40000>;
248 opp-1416000000 {
249 opp-hz = /bits/ 64 <1416000000>;
250 opp-microvolt = <725000 725000 950000>;
251 clock-latency-ns = <40000>;
254 opp-1608000000 {
255 opp-hz = /bits/ 64 <1608000000>;
256 opp-microvolt = <750000 750000 950000>;
257 clock-latency-ns = <40000>;
260 opp-1800000000 {
261 opp-hz = /bits/ 64 <1800000000>;
262 opp-microvolt = <825000 825000 950000>;
263 clock-latency-ns = <40000>;
264 opp-suspend;
267 opp-2016000000 {
268 opp-hz = /bits/ 64 <2016000000>;
269 opp-microvolt = <900000 900000 950000>;
270 clock-latency-ns = <40000>;
273 opp-2208000000 {
274 opp-hz = /bits/ 64 <2208000000>;
275 opp-microvolt = <950000 950000 950000>;
276 clock-latency-ns = <40000>;
280 cluster1_opp_table: opp-table-cluster1 {
281 compatible = "operating-points-v2";
282 opp-shared;
284 opp-408000000 {
285 opp-hz = /bits/ 64 <408000000>;
286 opp-microvolt = <700000 700000 950000>;
287 clock-latency-ns = <40000>;
288 opp-suspend;
291 opp-600000000 {
292 opp-hz = /bits/ 64 <600000000>;
293 opp-microvolt = <700000 700000 950000>;
294 clock-latency-ns = <40000>;
297 opp-816000000 {
298 opp-hz = /bits/ 64 <816000000>;
299 opp-microvolt = <700000 700000 950000>;
300 clock-latency-ns = <40000>;
303 opp-1008000000 {
304 opp-hz = /bits/ 64 <1008000000>;
305 opp-microvolt = <700000 700000 950000>;
306 clock-latency-ns = <40000>;
309 opp-1200000000 {
310 opp-hz = /bits/ 64 <1200000000>;
311 opp-microvolt = <700000 700000 950000>;
312 clock-latency-ns = <40000>;
315 opp-1416000000 {
316 opp-hz = /bits/ 64 <1416000000>;
317 opp-microvolt = <712500 712500 950000>;
318 clock-latency-ns = <40000>;
321 opp-1608000000 {
322 opp-hz = /bits/ 64 <1608000000>;
323 opp-microvolt = <737500 737500 950000>;
324 clock-latency-ns = <40000>;
327 opp-1800000000 {
328 opp-hz = /bits/ 64 <1800000000>;
329 opp-microvolt = <800000 800000 950000>;
330 clock-latency-ns = <40000>;
333 opp-2016000000 {
334 opp-hz = /bits/ 64 <2016000000>;
335 opp-microvolt = <862500 862500 950000>;
336 clock-latency-ns = <40000>;
339 opp-2208000000 {
340 opp-hz = /bits/ 64 <2208000000>;
341 opp-microvolt = <925000 925000 950000>;
342 clock-latency-ns = <40000>;
345 opp-2304000000 {
346 opp-hz = /bits/ 64 <2304000000>;
347 opp-microvolt = <950000 950000 950000>;
348 clock-latency-ns = <40000>;
352 gpu_opp_table: opp-table-gpu {
353 compatible = "operating-points-v2";
355 opp-300000000 {
356 opp-hz = /bits/ 64 <300000000>;
357 opp-microvolt = <700000 700000 850000>;
360 opp-400000000 {
361 opp-hz = /bits/ 64 <400000000>;
362 opp-microvolt = <700000 700000 850000>;
365 opp-500000000 {
366 opp-hz = /bits/ 64 <500000000>;
367 opp-microvolt = <700000 700000 850000>;
370 opp-600000000 {
371 opp-hz = /bits/ 64 <600000000>;
372 opp-microvolt = <700000 700000 850000>;
375 opp-700000000 {
376 opp-hz = /bits/ 64 <700000000>;
377 opp-microvolt = <725000 725000 850000>;
380 opp-800000000 {
381 opp-hz = /bits/ 64 <800000000>;
382 opp-microvolt = <775000 775000 850000>;
385 opp-900000000 {
386 opp-hz = /bits/ 64 <900000000>;
387 opp-microvolt = <825000 825000 850000>;
390 opp-950000000 {
391 opp-hz = /bits/ 64 <950000000>;
392 opp-microvolt = <850000 850000 850000>;
396 display_subsystem: display-subsystem {
397 compatible = "rockchip,display-subsystem";
403 compatible = "arm,scmi-smc";
404 arm,smc-id = <0x82000010>;
406 #address-cells = <1>;
407 #size-cells = <0>;
411 #clock-cells = <1>;
416 hdmi_sound: hdmi-sound {
417 compatible = "simple-audio-card";
418 simple-audio-card,name = "HDMI";
419 simple-audio-card,format = "i2s";
420 simple-audio-card,mclk-fs = <256>;
423 simple-audio-card,codec {
424 sound-dai = <&hdmi>;
427 simple-audio-card,cpu {
428 sound-dai = <&sai6>;
433 compatible = "rockchip,rk3576-pinctrl";
435 #address-cells = <2>;
436 #size-cells = <2>;
440 compatible = "rockchip,gpio-bank";
443 gpio-controller;
444 gpio-ranges = <&pinctrl 0 0 32>;
446 interrupt-controller;
447 #gpio-cells = <2>;
448 #interrupt-cells = <2>;
452 compatible = "rockchip,gpio-bank";
455 gpio-controller;
456 gpio-ranges = <&pinctrl 0 32 32>;
458 interrupt-controller;
459 #gpio-cells = <2>;
460 #interrupt-cells = <2>;
464 compatible = "rockchip,gpio-bank";
467 gpio-controller;
468 gpio-ranges = <&pinctrl 0 64 32>;
470 interrupt-controller;
471 #gpio-cells = <2>;
472 #interrupt-cells = <2>;
476 compatible = "rockchip,gpio-bank";
479 gpio-controller;
480 gpio-ranges = <&pinctrl 0 96 32>;
482 interrupt-controller;
483 #gpio-cells = <2>;
484 #interrupt-cells = <2>;
488 compatible = "rockchip,gpio-bank";
491 gpio-controller;
492 gpio-ranges = <&pinctrl 0 128 32>;
494 interrupt-controller;
495 #gpio-cells = <2>;
496 #interrupt-cells = <2>;
500 pmu_a53: pmu-a53 {
501 compatible = "arm,cortex-a53-pmu";
506 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>;
509 pmu_a72: pmu-a72 {
510 compatible = "arm,cortex-a72-pmu";
515 interrupt-affinity = <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>;
519 compatible = "arm,psci-1.0";
524 compatible = "arm,armv8-timer";
532 compatible = "simple-bus";
533 #address-cells = <2>;
534 #size-cells = <2>;
538 compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
542 reg-names = "dbi", "apb", "config";
543 bus-range = <0x0 0xf>;
547 clock-names = "aclk_mst", "aclk_slv",
557 interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
558 #interrupt-cells = <1>;
559 interrupt-map-mask = <0 0 0 7>;
560 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
564 linux,pci-domain = <0>;
565 max-link-speed = <2>;
566 num-ib-windows = <8>;
567 num-viewport = <8>;
568 num-ob-windows = <2>;
569 num-lanes = <1>;
571 phy-names = "pcie-phy";
572 power-domains = <&power RK3576_PD_PHP>;
577 reset-names = "pwr", "pipe";
578 #address-cells = <3>;
579 #size-cells = <2>;
582 pcie0_intc: legacy-interrupt-controller {
583 interrupt-controller;
584 #address-cells = <0>;
585 #interrupt-cells = <1>;
586 interrupt-parent = <&gic>;
592 compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
596 reg-names = "dbi", "apb", "config";
597 bus-range = <0x20 0x2f>;
601 clock-names = "aclk_mst", "aclk_slv",
611 interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
612 #interrupt-cells = <1>;
613 interrupt-map-mask = <0 0 0 7>;
614 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
618 linux,pci-domain = <1>;
619 max-link-speed = <2>;
620 num-ib-windows = <8>;
621 num-viewport = <8>;
622 num-ob-windows = <2>;
623 num-lanes = <1>;
625 phy-names = "pcie-phy";
626 power-domains = <&power RK3576_PD_SUBPHP>;
631 reset-names = "pwr", "pipe";
632 #address-cells = <3>;
633 #size-cells = <2>;
636 pcie1_intc: legacy-interrupt-controller {
637 interrupt-controller;
638 #address-cells = <0>;
639 #interrupt-cells = <1>;
640 interrupt-parent = <&gic>;
646 compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
651 clock-names = "ref_clk", "suspend_clk", "bus_clk";
653 power-domains = <&power RK3576_PD_USB>;
657 phy-names = "usb2-phy", "usb3-phy";
660 snps,dis-u1-entry-quirk;
661 snps,dis-u2-entry-quirk;
662 snps,dis-u2-freeclk-exists-quirk;
663 snps,dis-del-phy-power-chg-quirk;
664 snps,dis-tx-ipgap-linecheck-quirk;
665 snps,parkmode-disable-hs-quirk;
666 snps,parkmode-disable-ss-quirk;
671 compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
676 clock-names = "ref_clk", "suspend_clk", "bus_clk";
678 power-domains = <&power RK3576_PD_PHP>;
682 phy-names = "usb2-phy", "usb3-phy";
685 snps,dis-u1-entry-quirk;
686 snps,dis-u2-entry-quirk;
687 snps,dis-u2-freeclk-exists-quirk;
688 snps,dis-del-phy-power-chg-quirk;
689 snps,dis-tx-ipgap-linecheck-quirk;
691 snps,parkmode-disable-hs-quirk;
692 snps,parkmode-disable-ss-quirk;
693 dma-coherent;
698 compatible = "rockchip,rk3576-sys-grf", "syscon";
703 compatible = "rockchip,rk3576-bigcore-grf", "syscon";
708 compatible = "rockchip,rk3576-litcore-grf", "syscon";
713 compatible = "rockchip,rk3576-cci-grf", "syscon";
718 compatible = "rockchip,rk3576-gpu-grf", "syscon";
723 compatible = "rockchip,rk3576-npu-grf", "syscon";
728 compatible = "rockchip,rk3576-vo0-grf", "syscon";
733 compatible = "rockchip,rk3576-usb-grf", "syscon";
738 compatible = "rockchip,rk3576-php-grf", "syscon";
743 compatible = "rockchip,rk3576-pmu0-grf", "syscon", "simple-mfd";
748 compatible = "rockchip,rk3576-pmu1-grf", "syscon";
753 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon";
758 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon";
763 compatible = "rockchip,rk3576-usbdpphy-grf", "syscon";
768 compatible = "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd";
770 #address-cells = <1>;
771 #size-cells = <1>;
773 u2phy0: usb2-phy@0 {
774 compatible = "rockchip,rk3576-usb2phy";
777 reset-names = "phy", "apb";
781 clock-names = "phyclk", "aclk", "aclk_slv";
782 clock-output-names = "usb480m_phy0";
783 #clock-cells = <0>;
786 u2phy0_otg: otg-port {
787 #phy-cells = <0>;
791 interrupt-names = "otg-bvalid", "otg-id", "linestate";
796 u2phy1: usb2-phy@2000 {
797 compatible = "rockchip,rk3576-usb2phy";
800 reset-names = "phy", "apb";
804 clock-names = "phyclk", "aclk", "aclk_slv";
805 clock-output-names = "usb480m_phy1";
806 #clock-cells = <0>;
809 u2phy1_otg: otg-port {
810 #phy-cells = <0>;
814 interrupt-names = "otg-bvalid", "otg-id", "linestate";
821 compatible = "rockchip,rk3576-hdptxphy-grf", "syscon";
826 compatible = "rockchip,rk3576-vo1-grf", "syscon";
832 compatible = "rockchip,rk3576-sdgmac-grf", "syscon";
837 compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd";
841 cru: clock-controller@27200000 {
842 compatible = "rockchip,rk3576-cru";
844 #clock-cells = <1>;
845 #reset-cells = <1>;
847 assigned-clocks =
856 assigned-clock-parents = <&cru PLL_AUPLL>;
857 assigned-clock-rates =
869 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
872 clock-names = "i2c", "pclk";
874 pinctrl-names = "default";
875 pinctrl-0 = <&i2c0m0_xfer>;
876 #address-cells = <1>;
877 #size-cells = <0>;
882 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
884 reg-shift = <2>;
885 reg-io-width = <4>;
887 clock-names = "baudclk", "apb_pclk";
890 pinctrl-names = "default";
891 pinctrl-0 = <&uart1m0_xfer>;
895 pmu: power-management@27380000 {
896 compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd";
899 power: power-controller {
900 compatible = "rockchip,rk3576-power-controller";
901 #power-domain-cells = <1>;
902 #address-cells = <1>;
903 #size-cells = <0>;
905 power-domain@RK3576_PD_NPU {
907 #power-domain-cells = <1>;
908 #address-cells = <1>;
909 #size-cells = <0>;
911 power-domain@RK3576_PD_NPUTOP {
926 #power-domain-cells = <1>;
927 #address-cells = <1>;
928 #size-cells = <0>;
930 power-domain@RK3576_PD_NPU0 {
935 #power-domain-cells = <0>;
937 power-domain@RK3576_PD_NPU1 {
942 #power-domain-cells = <0>;
947 power-domain@RK3576_PD_GPU {
951 #power-domain-cells = <0>;
954 power-domain@RK3576_PD_NVM {
959 #power-domain-cells = <1>;
960 #address-cells = <1>;
961 #size-cells = <0>;
963 power-domain@RK3576_PD_SDGMAC {
980 #power-domain-cells = <0>;
984 power-domain@RK3576_PD_PHP {
992 #power-domain-cells = <1>;
993 #address-cells = <1>;
994 #size-cells = <0>;
996 power-domain@RK3576_PD_SUBPHP {
998 #power-domain-cells = <0>;
1002 power-domain@RK3576_PD_AUDIO {
1004 #power-domain-cells = <0>;
1007 power-domain@RK3576_PD_VEPU1 {
1012 #power-domain-cells = <0>;
1015 power-domain@RK3576_PD_VPU {
1032 #power-domain-cells = <0>;
1035 power-domain@RK3576_PD_VDEC {
1040 #power-domain-cells = <0>;
1043 power-domain@RK3576_PD_VI {
1062 #power-domain-cells = <1>;
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1066 power-domain@RK3576_PD_VEPU0 {
1071 #power-domain-cells = <0>;
1075 power-domain@RK3576_PD_VOP {
1083 #power-domain-cells = <1>;
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1087 power-domain@RK3576_PD_USB {
1096 #power-domain-cells = <0>;
1099 power-domain@RK3576_PD_VO0 {
1107 #power-domain-cells = <0>;
1110 power-domain@RK3576_PD_VO1 {
1118 #power-domain-cells = <0>;
1125 compatible = "rockchip,rk3576-mali", "arm,mali-bifrost";
1127 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
1128 assigned-clock-rates = <198000000>;
1130 clock-names = "core";
1131 dynamic-power-coefficient = <1625>;
1135 interrupt-names = "job", "mmu", "gpu";
1136 operating-points-v2 = <&gpu_opp_table>;
1137 power-domains = <&power RK3576_PD_GPU>;
1138 #cooling-cells = <2>;
1143 compatible = "rockchip,rk3576-vop";
1145 reg-names = "vop", "gamma-lut";
1150 interrupt-names = "sys",
1159 clock-names = "aclk",
1165 power-domains = <&power RK3576_PD_VOP>;
1171 #address-cells = <1>;
1172 #size-cells = <0>;
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1181 #address-cells = <1>;
1182 #size-cells = <0>;
1187 #address-cells = <1>;
1188 #size-cells = <0>;
1195 compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu";
1199 clock-names = "aclk", "iface";
1200 #iommu-cells = <0>;
1201 power-domains = <&power RK3576_PD_VOP>;
1206 compatible = "rockchip,rk3576-sai";
1210 clock-names = "mclk", "hclk";
1212 dma-names = "rx";
1213 power-domains = <&power RK3576_PD_VO0>;
1215 reset-names = "m", "h";
1216 rockchip,sai-rx-route = <0 1 2 3>;
1217 #sound-dai-cells = <0>;
1218 sound-name-prefix = "SAI5";
1223 compatible = "rockchip,rk3576-sai";
1227 clock-names = "mclk", "hclk";
1229 dma-names = "tx", "rx";
1230 power-domains = <&power RK3576_PD_VO0>;
1232 reset-names = "m", "h";
1233 rockchip,sai-rx-route = <0 1 2 3>;
1234 rockchip,sai-tx-route = <0 1 2 3>;
1235 #sound-dai-cells = <0>;
1236 sound-name-prefix = "SAI6";
1241 compatible = "rockchip,rk3576-dw-hdmi-qp";
1249 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
1255 interrupt-names = "avp", "cec", "earc", "main", "hpd";
1257 pinctrl-names = "default";
1258 pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>;
1259 power-domains = <&power RK3576_PD_VO0>;
1261 reset-names = "ref", "hdp";
1263 rockchip,vo-grf = <&vo0_grf>;
1264 #sound-dai-cells = <0>;
1268 #address-cells = <1>;
1269 #size-cells = <0>;
1282 compatible = "rockchip,rk3576-sai";
1286 clock-names = "mclk", "hclk";
1288 dma-names = "tx";
1289 power-domains = <&power RK3576_PD_VO1>;
1291 reset-names = "m", "h";
1292 rockchip,sai-tx-route = <0 1 2 3>;
1293 #sound-dai-cells = <0>;
1294 sound-name-prefix = "SAI7";
1299 compatible = "rockchip,rk3576-sai";
1303 clock-names = "mclk", "hclk";
1305 dma-names = "tx";
1306 power-domains = <&power RK3576_PD_VO1>;
1308 reset-names = "m", "h";
1309 rockchip,sai-tx-route = <0 1 2 3>;
1310 #sound-dai-cells = <0>;
1311 sound-name-prefix = "SAI8";
1316 compatible = "rockchip,rk3576-sai";
1320 clock-names = "mclk", "hclk";
1322 dma-names = "tx";
1323 power-domains = <&power RK3576_PD_VO1>;
1325 reset-names = "m", "h";
1326 rockchip,sai-tx-route = <0 1 2 3>;
1327 #sound-dai-cells = <0>;
1328 sound-name-prefix = "SAI9";
1333 compatible = "rockchip,rk3576-qos", "syscon";
1338 compatible = "rockchip,rk3576-qos", "syscon";
1343 compatible = "rockchip,rk3576-qos", "syscon";
1348 compatible = "rockchip,rk3576-qos", "syscon";
1353 compatible = "rockchip,rk3576-qos", "syscon";
1358 compatible = "rockchip,rk3576-qos", "syscon";
1363 compatible = "rockchip,rk3576-qos", "syscon";
1368 compatible = "rockchip,rk3576-qos", "syscon";
1373 compatible = "rockchip,rk3576-qos", "syscon";
1378 compatible = "rockchip,rk3576-qos", "syscon";
1383 compatible = "rockchip,rk3576-qos", "syscon";
1388 compatible = "rockchip,rk3576-qos", "syscon";
1393 compatible = "rockchip,rk3576-qos", "syscon";
1398 compatible = "rockchip,rk3576-qos", "syscon";
1403 compatible = "rockchip,rk3576-qos", "syscon";
1408 compatible = "rockchip,rk3576-qos", "syscon";
1413 compatible = "rockchip,rk3576-qos", "syscon";
1418 compatible = "rockchip,rk3576-qos", "syscon";
1423 compatible = "rockchip,rk3576-qos", "syscon";
1428 compatible = "rockchip,rk3576-qos", "syscon";
1433 compatible = "rockchip,rk3576-qos", "syscon";
1438 compatible = "rockchip,rk3576-qos", "syscon";
1443 compatible = "rockchip,rk3576-qos", "syscon";
1448 compatible = "rockchip,rk3576-qos", "syscon";
1453 compatible = "rockchip,rk3576-qos", "syscon";
1458 compatible = "rockchip,rk3576-qos", "syscon";
1463 compatible = "rockchip,rk3576-qos", "syscon";
1468 compatible = "rockchip,rk3576-qos", "syscon";
1473 compatible = "rockchip,rk3576-qos", "syscon";
1478 compatible = "rockchip,rk3576-qos", "syscon";
1483 compatible = "rockchip,rk3576-qos", "syscon";
1488 compatible = "rockchip,rk3576-qos", "syscon";
1493 compatible = "rockchip,rk3576-qos", "syscon";
1498 compatible = "rockchip,rk3576-qos", "syscon";
1503 compatible = "rockchip,rk3576-qos", "syscon";
1508 compatible = "rockchip,rk3576-qos", "syscon";
1513 compatible = "rockchip,rk3576-qos", "syscon";
1518 compatible = "rockchip,rk3576-qos", "syscon";
1523 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
1528 clock-names = "stmmaceth", "clk_mac_ref",
1533 interrupt-names = "macirq", "eth_wake_irq";
1534 power-domains = <&power RK3576_PD_SDGMAC>;
1536 reset-names = "stmmaceth";
1538 rockchip,php-grf = <&ioc_grf>;
1539 snps,axi-config = <&gmac0_stmmac_axi_setup>;
1540 snps,mixed-burst;
1541 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
1542 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
1547 compatible = "snps,dwmac-mdio";
1548 #address-cells = <0x1>;
1549 #size-cells = <0x0>;
1552 gmac0_stmmac_axi_setup: stmmac-axi-config {
1558 gmac0_mtl_rx_setup: rx-queues-config {
1559 snps,rx-queues-to-use = <1>;
1563 gmac0_mtl_tx_setup: tx-queues-config {
1564 snps,tx-queues-to-use = <1>;
1570 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
1575 clock-names = "stmmaceth", "clk_mac_ref",
1580 interrupt-names = "macirq", "eth_wake_irq";
1581 power-domains = <&power RK3576_PD_SDGMAC>;
1583 reset-names = "stmmaceth";
1585 rockchip,php-grf = <&ioc_grf>;
1586 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1587 snps,mixed-burst;
1588 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1589 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1594 compatible = "snps,dwmac-mdio";
1595 #address-cells = <0x1>;
1596 #size-cells = <0x0>;
1599 gmac1_stmmac_axi_setup: stmmac-axi-config {
1605 gmac1_mtl_rx_setup: rx-queues-config {
1606 snps,rx-queues-to-use = <1>;
1610 gmac1_mtl_tx_setup: tx-queues-config {
1611 snps,tx-queues-to-use = <1>;
1617 compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci";
1621 clock-names = "sata", "pmalive", "rxoob";
1623 power-domains = <&power RK3576_PD_SUBPHP>;
1625 phy-names = "sata-phy";
1626 ports-implemented = <0x1>;
1627 dma-coherent;
1632 compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci";
1636 clock-names = "sata", "pmalive", "rxoob";
1638 power-domains = <&power RK3576_PD_SUBPHP>;
1640 phy-names = "sata-phy";
1641 ports-implemented = <0x1>;
1642 dma-coherent;
1647 compatible = "rockchip,rk3576-ufshc";
1653 reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb";
1656 clock-names = "core", "pclk", "pclk_mphy", "ref_out";
1657 assigned-clocks = <&cru CLK_REF_OSC_MPHY>;
1658 assigned-clock-parents = <&cru CLK_REF_MPHY_26M>;
1660 power-domains = <&power RK3576_PD_USB>;
1661 pinctrl-0 = <&ufs_refclk>;
1662 pinctrl-names = "default";
1665 reset-names = "biu", "sys", "ufs", "grf";
1666 reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>;
1675 clock-names = "clk_sfc", "hclk_sfc";
1676 power-domains = <&power RK3576_PD_SDGMAC>;
1677 #address-cells = <1>;
1678 #size-cells = <0>;
1683 compatible = "rockchip,rk3576-dw-mshc";
1686 clock-names = "biu", "ciu";
1687 fifo-depth = <0x100>;
1689 max-frequency = <200000000>;
1690 pinctrl-names = "default";
1691 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4 &sdmmc0_pwren>;
1692 power-domains = <&power RK3576_PD_SDGMAC>;
1694 reset-names = "reset";
1699 compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc";
1701 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>;
1702 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1706 clock-names = "core", "bus", "axi", "block", "timer";
1708 max-frequency = <200000000>;
1709 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1711 pinctrl-names = "default";
1712 power-domains = <&power RK3576_PD_NVM>;
1716 reset-names = "core", "bus", "axi", "block", "timer";
1717 supports-cqe;
1726 clock-names = "clk_sfc", "hclk_sfc";
1727 power-domains = <&power RK3576_PD_NVM>;
1728 #address-cells = <1>;
1729 #size-cells = <0>;
1734 compatible = "rockchip,rk3576-rng";
1742 compatible = "rockchip,rk3576-otp";
1744 #address-cells = <1>;
1745 #size-cells = <1>;
1748 clock-names = "otp", "apb_pclk", "phy";
1750 reset-names = "otp", "apb";
1753 cpu_code: cpu-code@2 {
1756 otp_cpu_version: cpu-version@5 {
1763 cpub_leakage: cpub-leakage@1e {
1766 cpul_leakage: cpul-leakage@1f {
1769 npu_leakage: npu-leakage@20 {
1772 gpu_leakage: gpu-leakage@21 {
1775 log_leakage: log-leakage@22 {
1781 compatible = "rockchip,rk3576-sai";
1785 clock-names = "mclk", "hclk";
1787 dma-names = "tx", "rx";
1788 power-domains = <&power RK3576_PD_AUDIO>;
1790 reset-names = "m", "h";
1791 pinctrl-names = "default";
1792 pinctrl-0 = <&sai0m0_lrck
1802 #sound-dai-cells = <0>;
1803 sound-name-prefix = "SAI0";
1808 compatible = "rockchip,rk3576-sai";
1812 clock-names = "mclk", "hclk";
1814 dma-names = "tx", "rx";
1815 power-domains = <&power RK3576_PD_AUDIO>;
1817 reset-names = "m", "h";
1818 pinctrl-names = "default";
1819 pinctrl-0 = <&sai1m0_lrck
1826 #sound-dai-cells = <0>;
1827 sound-name-prefix = "SAI1";
1832 compatible = "rockchip,rk3576-sai";
1836 clock-names = "mclk", "hclk";
1838 dma-names = "tx", "rx";
1839 power-domains = <&power RK3576_PD_AUDIO>;
1841 reset-names = "m", "h";
1842 pinctrl-names = "default";
1843 pinctrl-0 = <&sai2m0_lrck
1847 #sound-dai-cells = <0>;
1848 sound-name-prefix = "SAI2";
1853 compatible = "rockchip,rk3576-sai";
1857 clock-names = "mclk", "hclk";
1859 dma-names = "tx", "rx";
1860 power-domains = <&power RK3576_PD_AUDIO>;
1862 reset-names = "m", "h";
1863 pinctrl-names = "default";
1864 pinctrl-0 = <&sai3m0_lrck
1868 #sound-dai-cells = <0>;
1869 sound-name-prefix = "SAI3";
1874 compatible = "rockchip,rk3576-sai";
1878 clock-names = "mclk", "hclk";
1880 dma-names = "tx", "rx";
1881 power-domains = <&power RK3576_PD_AUDIO>;
1883 reset-names = "m", "h";
1884 pinctrl-names = "default";
1885 pinctrl-0 = <&sai4m0_lrck
1889 #sound-dai-cells = <0>;
1890 sound-name-prefix = "SAI4";
1894 gic: interrupt-controller@2a701000 {
1895 compatible = "arm,gic-400";
1901 interrupt-controller;
1902 #interrupt-cells = <3>;
1903 #address-cells = <2>;
1904 #size-cells = <2>;
1907 dmac0: dma-controller@2ab90000 {
1910 arm,pl330-periph-burst;
1912 clock-names = "apb_pclk";
1915 #dma-cells = <1>;
1918 dmac1: dma-controller@2abb0000 {
1921 arm,pl330-periph-burst;
1923 clock-names = "apb_pclk";
1926 #dma-cells = <1>;
1929 dmac2: dma-controller@2abd0000 {
1932 arm,pl330-periph-burst;
1934 clock-names = "apb_pclk";
1937 #dma-cells = <1>;
1941 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1944 clock-names = "i2c", "pclk";
1946 pinctrl-names = "default";
1947 pinctrl-0 = <&i2c1m0_xfer>;
1948 #address-cells = <1>;
1949 #size-cells = <0>;
1954 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1957 clock-names = "i2c", "pclk";
1959 pinctrl-names = "default";
1960 pinctrl-0 = <&i2c2m0_xfer>;
1961 #address-cells = <1>;
1962 #size-cells = <0>;
1967 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1970 clock-names = "i2c", "pclk";
1972 pinctrl-names = "default";
1973 pinctrl-0 = <&i2c3m0_xfer>;
1974 #address-cells = <1>;
1975 #size-cells = <0>;
1980 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1983 clock-names = "i2c", "pclk";
1985 pinctrl-names = "default";
1986 pinctrl-0 = <&i2c4m0_xfer>;
1987 #address-cells = <1>;
1988 #size-cells = <0>;
1993 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1996 clock-names = "i2c", "pclk";
1998 pinctrl-names = "default";
1999 pinctrl-0 = <&i2c5m0_xfer>;
2000 #address-cells = <1>;
2001 #size-cells = <0>;
2006 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
2009 clock-names = "i2c", "pclk";
2011 pinctrl-names = "default";
2012 pinctrl-0 = <&i2c6m0_xfer>;
2013 #address-cells = <1>;
2014 #size-cells = <0>;
2019 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
2022 clock-names = "i2c", "pclk";
2024 pinctrl-names = "default";
2025 pinctrl-0 = <&i2c7m0_xfer>;
2026 #address-cells = <1>;
2027 #size-cells = <0>;
2032 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
2035 clock-names = "i2c", "pclk";
2037 pinctrl-names = "default";
2038 pinctrl-0 = <&i2c8m0_xfer>;
2039 #address-cells = <1>;
2040 #size-cells = <0>;
2045 compatible = "rockchip,rk3576-timer", "rockchip,rk3288-timer";
2048 clock-names = "pclk", "timer";
2053 compatible = "rockchip,rk3576-wdt", "snps,dw-wdt";
2056 clock-names = "tclk", "pclk";
2062 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
2065 clock-names = "spiclk", "apb_pclk";
2067 dma-names = "tx", "rx";
2069 num-cs = <2>;
2070 pinctrl-names = "default";
2071 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>;
2072 #address-cells = <1>;
2073 #size-cells = <0>;
2078 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
2081 clock-names = "spiclk", "apb_pclk";
2083 dma-names = "tx", "rx";
2085 num-cs = <2>;
2086 pinctrl-names = "default";
2087 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>;
2088 #address-cells = <1>;
2089 #size-cells = <0>;
2094 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
2097 clock-names = "spiclk", "apb_pclk";
2099 dma-names = "tx", "rx";
2101 num-cs = <2>;
2102 pinctrl-names = "default";
2103 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>;
2104 #address-cells = <1>;
2105 #size-cells = <0>;
2110 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
2113 clock-names = "spiclk", "apb_pclk";
2115 dma-names = "tx", "rx";
2117 num-cs = <2>;
2118 pinctrl-names = "default";
2119 pinctrl-0 = <&spi3m0_csn0 &spi3m0_csn1 &spi3m0_pins>;
2120 #address-cells = <1>;
2121 #size-cells = <0>;
2126 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
2129 clock-names = "spiclk", "apb_pclk";
2131 dma-names = "tx", "rx";
2133 num-cs = <2>;
2134 pinctrl-names = "default";
2135 pinctrl-0 = <&spi4m0_csn0 &spi4m0_csn1 &spi4m0_pins>;
2136 #address-cells = <1>;
2137 #size-cells = <0>;
2142 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2144 reg-shift = <2>;
2145 reg-io-width = <4>;
2147 clock-names = "baudclk", "apb_pclk";
2149 dma-names = "tx", "rx";
2151 pinctrl-0 = <&uart0m0_xfer>;
2152 pinctrl-names = "default";
2157 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2159 reg-shift = <2>;
2160 reg-io-width = <4>;
2162 clock-names = "baudclk", "apb_pclk";
2164 dma-names = "tx", "rx";
2166 pinctrl-names = "default";
2167 pinctrl-0 = <&uart2m0_xfer>;
2172 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2174 reg-shift = <2>;
2175 reg-io-width = <4>;
2177 clock-names = "baudclk", "apb_pclk";
2179 dma-names = "tx", "rx";
2181 pinctrl-0 = <&uart3m0_xfer>;
2182 pinctrl-names = "default";
2187 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2189 reg-shift = <2>;
2190 reg-io-width = <4>;
2192 clock-names = "baudclk", "apb_pclk";
2194 dma-names = "tx", "rx";
2196 pinctrl-0 = <&uart4m0_xfer>;
2197 pinctrl-names = "default";
2202 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2204 reg-shift = <2>;
2205 reg-io-width = <4>;
2207 clock-names = "baudclk", "apb_pclk";
2209 dma-names = "tx", "rx";
2211 pinctrl-0 = <&uart5m0_xfer>;
2212 pinctrl-names = "default";
2217 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2219 reg-shift = <2>;
2220 reg-io-width = <4>;
2222 clock-names = "baudclk", "apb_pclk";
2224 dma-names = "tx", "rx";
2226 pinctrl-0 = <&uart6m0_xfer>;
2227 pinctrl-names = "default";
2232 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2234 reg-shift = <2>;
2235 reg-io-width = <4>;
2237 clock-names = "baudclk", "apb_pclk";
2239 dma-names = "tx", "rx";
2241 pinctrl-0 = <&uart7m0_xfer>;
2242 pinctrl-names = "default";
2247 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2249 reg-shift = <2>;
2250 reg-io-width = <4>;
2252 clock-names = "baudclk", "apb_pclk";
2254 dma-names = "tx", "rx";
2256 pinctrl-0 = <&uart8m0_xfer>;
2257 pinctrl-names = "default";
2262 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2264 reg-shift = <2>;
2265 reg-io-width = <4>;
2267 clock-names = "baudclk", "apb_pclk";
2269 dma-names = "tx", "rx";
2271 pinctrl-0 = <&uart9m0_xfer>;
2272 pinctrl-names = "default";
2277 compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc";
2280 clock-names = "saradc", "apb_pclk";
2283 reset-names = "saradc-apb";
2284 #io-channel-cells = <1>;
2289 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
2292 clock-names = "i2c", "pclk";
2294 pinctrl-names = "default";
2295 pinctrl-0 = <&i2c9m0_xfer>;
2297 reset-names = "i2c", "apb";
2298 #address-cells = <1>;
2299 #size-cells = <0>;
2304 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2306 reg-shift = <2>;
2307 reg-io-width = <4>;
2309 clock-names = "baudclk", "apb_pclk";
2312 pinctrl-names = "default";
2313 pinctrl-0 = <&uart10m0_xfer>;
2318 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
2320 reg-shift = <2>;
2321 reg-io-width = <4>;
2323 clock-names = "baudclk", "apb_pclk";
2326 pinctrl-names = "default";
2327 pinctrl-0 = <&uart11m0_xfer>;
2332 compatible = "rockchip,rk3576-naneng-combphy";
2334 #phy-cells = <1>;
2338 clock-names = "ref", "apb", "pipe";
2339 assigned-clocks = <&cru CLK_REF_PCIE0_PHY>;
2340 assigned-clock-rates = <100000000>;
2343 reset-names = "phy", "apb";
2344 rockchip,pipe-grf = <&php_grf>;
2345 rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
2350 compatible = "rockchip,rk3576-naneng-combphy";
2352 #phy-cells = <1>;
2356 clock-names = "ref", "apb", "pipe";
2357 assigned-clocks = <&cru CLK_REF_PCIE1_PHY>;
2358 assigned-clock-rates = <100000000>;
2361 reset-names = "phy", "apb";
2362 rockchip,pipe-grf = <&php_grf>;
2363 rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
2368 compatible = "rockchip,rk3576-usbdp-phy";
2370 #phy-cells = <1>;
2375 clock-names = "refclk", "immortal", "pclk", "utmi";
2381 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
2382 rockchip,u2phy-grf = <&usb2phy_grf>;
2383 rockchip,usb-grf = <&usb_grf>;
2384 rockchip,usbdpphy-grf = <&usbdpphy_grf>;
2385 rockchip,vo-grf = <&vo1_grf>;
2390 compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy";
2393 clock-names = "ref", "apb";
2396 reset-names = "apb", "init", "cmn", "lane";
2398 #phy-cells = <0>;
2403 compatible = "mmio-sram";
2406 #address-cells = <1>;
2407 #size-cells = <1>;
2410 rkvdec_sram: rkvdec-sram@0 {
2415 scmi_shmem: scmi-shmem@4010f000 {
2416 compatible = "arm,scmi-shmem";
2422 #include "rk3576-pinctrl.dtsi"