Lines Matching +full:rk3328 +full:- +full:grf +full:- +full:gpio
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
49 #address-cells = <2>;
50 #size-cells = <0>;
54 compatible = "arm,cortex-a55";
57 #cooling-cells = <2>;
58 enable-method = "psci";
59 operating-points-v2 = <&cpu0_opp_table>;
60 i-cache-size = <0x8000>;
61 i-cache-line-size = <64>;
62 i-cache-sets = <128>;
63 d-cache-size = <0x8000>;
64 d-cache-line-size = <64>;
65 d-cache-sets = <128>;
66 next-level-cache = <&l3_cache>;
71 compatible = "arm,cortex-a55";
73 #cooling-cells = <2>;
74 enable-method = "psci";
75 operating-points-v2 = <&cpu0_opp_table>;
76 i-cache-size = <0x8000>;
77 i-cache-line-size = <64>;
78 i-cache-sets = <128>;
79 d-cache-size = <0x8000>;
80 d-cache-line-size = <64>;
81 d-cache-sets = <128>;
82 next-level-cache = <&l3_cache>;
87 compatible = "arm,cortex-a55";
89 #cooling-cells = <2>;
90 enable-method = "psci";
91 operating-points-v2 = <&cpu0_opp_table>;
92 i-cache-size = <0x8000>;
93 i-cache-line-size = <64>;
94 i-cache-sets = <128>;
95 d-cache-size = <0x8000>;
96 d-cache-line-size = <64>;
97 d-cache-sets = <128>;
98 next-level-cache = <&l3_cache>;
103 compatible = "arm,cortex-a55";
105 #cooling-cells = <2>;
106 enable-method = "psci";
107 operating-points-v2 = <&cpu0_opp_table>;
108 i-cache-size = <0x8000>;
109 i-cache-line-size = <64>;
110 i-cache-sets = <128>;
111 d-cache-size = <0x8000>;
112 d-cache-line-size = <64>;
113 d-cache-sets = <128>;
114 next-level-cache = <&l3_cache>;
119 * There are no private per-core L2 caches, but only the
122 l3_cache: l3-cache {
124 cache-level = <2>;
125 cache-unified;
126 cache-size = <0x80000>;
127 cache-line-size = <64>;
128 cache-sets = <512>;
131 cpu0_opp_table: opp-table-0 {
132 compatible = "operating-points-v2";
133 opp-shared;
135 opp-408000000 {
136 opp-hz = /bits/ 64 <408000000>;
137 opp-microvolt = <900000 900000 1150000>;
138 clock-latency-ns = <40000>;
141 opp-600000000 {
142 opp-hz = /bits/ 64 <600000000>;
143 opp-microvolt = <900000 900000 1150000>;
146 opp-816000000 {
147 opp-hz = /bits/ 64 <816000000>;
148 opp-microvolt = <900000 900000 1150000>;
149 opp-suspend;
152 opp-1104000000 {
153 opp-hz = /bits/ 64 <1104000000>;
154 opp-microvolt = <900000 900000 1150000>;
157 opp-1416000000 {
158 opp-hz = /bits/ 64 <1416000000>;
159 opp-microvolt = <900000 900000 1150000>;
162 opp-1608000000 {
163 opp-hz = /bits/ 64 <1608000000>;
164 opp-microvolt = <975000 975000 1150000>;
167 opp-1800000000 {
168 opp-hz = /bits/ 64 <1800000000>;
169 opp-microvolt = <1050000 1050000 1150000>;
173 display_subsystem: display-subsystem {
174 compatible = "rockchip,display-subsystem";
180 compatible = "arm,scmi-smc";
181 arm,smc-id = <0x82000010>;
183 #address-cells = <1>;
184 #size-cells = <0>;
188 #clock-cells = <1>;
193 gpu_opp_table: opp-table-1 {
194 compatible = "operating-points-v2";
196 opp-200000000 {
197 opp-hz = /bits/ 64 <200000000>;
198 opp-microvolt = <850000 850000 1000000>;
201 opp-300000000 {
202 opp-hz = /bits/ 64 <300000000>;
203 opp-microvolt = <850000 850000 1000000>;
206 opp-400000000 {
207 opp-hz = /bits/ 64 <400000000>;
208 opp-microvolt = <850000 850000 1000000>;
211 opp-600000000 {
212 opp-hz = /bits/ 64 <600000000>;
213 opp-microvolt = <900000 900000 1000000>;
216 opp-700000000 {
217 opp-hz = /bits/ 64 <700000000>;
218 opp-microvolt = <950000 950000 1000000>;
221 opp-800000000 {
222 opp-hz = /bits/ 64 <800000000>;
223 opp-microvolt = <1000000 1000000 1000000>;
227 hdmi_sound: hdmi-sound {
228 compatible = "simple-audio-card";
229 simple-audio-card,name = "HDMI";
230 simple-audio-card,format = "i2s";
231 simple-audio-card,mclk-fs = <256>;
234 simple-audio-card,codec {
235 sound-dai = <&hdmi>;
238 simple-audio-card,cpu {
239 sound-dai = <&i2s0_8ch>;
244 compatible = "arm,cortex-a55-pmu";
249 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
253 compatible = "arm,psci-1.0";
258 compatible = "arm,armv8-timer";
263 arm,no-tick-in-suspend;
267 compatible = "fixed-clock";
268 clock-frequency = <24000000>;
269 clock-output-names = "xin24m";
270 #clock-cells = <0>;
274 compatible = "fixed-clock";
275 clock-frequency = <32768>;
276 clock-output-names = "xin32k";
277 pinctrl-0 = <&clk32k_out0>;
278 pinctrl-names = "default";
279 #clock-cells = <0>;
283 compatible = "mmio-sram";
285 #address-cells = <1>;
286 #size-cells = <1>;
290 compatible = "arm,scmi-shmem";
296 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
300 clock-names = "sata", "pmalive", "rxoob";
303 phy-names = "sata-phy";
304 ports-implemented = <0x1>;
305 power-domains = <&power RK3568_PD_PIPE>;
310 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
314 clock-names = "sata", "pmalive", "rxoob";
317 phy-names = "sata-phy";
318 ports-implemented = <0x1>;
319 power-domains = <&power RK3568_PD_PIPE>;
324 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
329 clock-names = "ref_clk", "suspend_clk",
333 power-domains = <&power RK3568_PD_PIPE>;
340 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
345 clock-names = "ref_clk", "suspend_clk",
349 phy-names = "usb2-phy", "usb3-phy";
351 power-domains = <&power RK3568_PD_PIPE>;
357 gic: interrupt-controller@fd400000 {
358 compatible = "arm,gic-v3";
362 interrupt-controller;
363 #interrupt-cells = <3>;
364 mbi-alias = <0x0 0xfd410000>;
365 mbi-ranges = <296 24>;
366 msi-controller;
370 compatible = "generic-ehci";
376 phy-names = "usb";
381 compatible = "generic-ohci";
387 phy-names = "usb";
392 compatible = "generic-ehci";
398 phy-names = "usb";
403 compatible = "generic-ohci";
409 phy-names = "usb";
414 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
417 pmu_io_domains: io-domains {
418 compatible = "rockchip,rk3568-pmu-io-voltage-domain";
427 grf: syscon@fdc60000 { label
428 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
433 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
438 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
443 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
448 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
452 pmucru: clock-controller@fdd00000 {
453 compatible = "rockchip,rk3568-pmucru";
455 #clock-cells = <1>;
456 #reset-cells = <1>;
459 cru: clock-controller@fdd20000 {
460 compatible = "rockchip,rk3568-cru";
463 clock-names = "xin24m";
464 #clock-cells = <1>;
465 #reset-cells = <1>;
466 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
467 assigned-clock-rates = <32768>, <1200000000>, <200000000>;
468 assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
469 rockchip,grf = <&grf>;
473 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
477 clock-names = "i2c", "pclk";
478 pinctrl-0 = <&i2c0_xfer>;
479 pinctrl-names = "default";
480 #address-cells = <1>;
481 #size-cells = <0>;
486 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
490 clock-names = "baudclk", "apb_pclk";
492 pinctrl-0 = <&uart0_xfer>;
493 pinctrl-names = "default";
494 reg-io-width = <4>;
495 reg-shift = <2>;
500 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
503 clock-names = "pwm", "pclk";
504 pinctrl-0 = <&pwm0m0_pins>;
505 pinctrl-names = "default";
506 #pwm-cells = <3>;
511 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
514 clock-names = "pwm", "pclk";
515 pinctrl-0 = <&pwm1m0_pins>;
516 pinctrl-names = "default";
517 #pwm-cells = <3>;
522 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
525 clock-names = "pwm", "pclk";
526 pinctrl-0 = <&pwm2m0_pins>;
527 pinctrl-names = "default";
528 #pwm-cells = <3>;
533 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
536 clock-names = "pwm", "pclk";
537 pinctrl-0 = <&pwm3_pins>;
538 pinctrl-names = "default";
539 #pwm-cells = <3>;
543 pmu: power-management@fdd90000 {
544 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
547 power: power-controller {
548 compatible = "rockchip,rk3568-power-controller";
549 #power-domain-cells = <1>;
550 #address-cells = <1>;
551 #size-cells = <0>;
554 power-domain@RK3568_PD_GPU {
559 #power-domain-cells = <0>;
563 power-domain@RK3568_PD_VI {
570 #power-domain-cells = <0>;
573 power-domain@RK3568_PD_VO {
581 #power-domain-cells = <0>;
584 power-domain@RK3568_PD_RGA {
594 #power-domain-cells = <0>;
597 power-domain@RK3568_PD_VPU {
601 #power-domain-cells = <0>;
604 power-domain@RK3568_PD_RKVDEC {
608 #power-domain-cells = <0>;
611 power-domain@RK3568_PD_RKVENC {
617 #power-domain-cells = <0>;
623 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
628 interrupt-names = "job", "mmu", "gpu";
630 clock-names = "gpu", "bus";
631 #cooling-cells = <2>;
632 operating-points-v2 = <&gpu_opp_table>;
633 power-domains = <&power RK3568_PD_GPU>;
637 vpu: video-codec@fdea0400 {
638 compatible = "rockchip,rk3568-vpu";
641 interrupt-names = "vdpu";
643 clock-names = "aclk", "hclk";
645 power-domains = <&power RK3568_PD_VPU>;
649 compatible = "rockchip,rk3568-iommu";
652 clock-names = "aclk", "iface";
654 power-domains = <&power RK3568_PD_VPU>;
655 #iommu-cells = <0>;
659 compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga";
663 clock-names = "aclk", "hclk", "sclk";
665 reset-names = "core", "axi", "ahb";
666 power-domains = <&power RK3568_PD_RGA>;
669 vepu: video-codec@fdee0000 {
670 compatible = "rockchip,rk3568-vepu";
674 clock-names = "aclk", "hclk";
676 power-domains = <&power RK3568_PD_RGA>;
680 compatible = "rockchip,rk3568-iommu";
684 clock-names = "aclk", "iface";
685 power-domains = <&power RK3568_PD_RGA>;
686 #iommu-cells = <0>;
690 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
695 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
696 fifo-depth = <0x100>;
697 max-frequency = <150000000>;
699 reset-names = "reset";
704 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
708 interrupt-names = "macirq", "eth_wake_irq";
713 clock-names = "stmmaceth", "mac_clk_rx",
718 reset-names = "stmmaceth";
719 rockchip,grf = <&grf>;
720 snps,axi-config = <&gmac1_stmmac_axi_setup>;
721 snps,mixed-burst;
722 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
723 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
728 compatible = "snps,dwmac-mdio";
729 #address-cells = <0x1>;
730 #size-cells = <0x0>;
733 gmac1_stmmac_axi_setup: stmmac-axi-config {
739 gmac1_mtl_rx_setup: rx-queues-config {
740 snps,rx-queues-to-use = <1>;
744 gmac1_mtl_tx_setup: tx-queues-config {
745 snps,tx-queues-to-use = <1>;
752 reg-names = "vop", "gamma-lut";
756 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
758 power-domains = <&power RK3568_PD_VO>;
759 rockchip,grf = <&grf>;
763 #address-cells = <1>;
764 #size-cells = <0>;
768 #address-cells = <1>;
769 #size-cells = <0>;
774 #address-cells = <1>;
775 #size-cells = <0>;
780 #address-cells = <1>;
781 #size-cells = <0>;
787 compatible = "rockchip,rk3568-iommu";
791 clock-names = "aclk", "iface";
792 #iommu-cells = <0>;
793 power-domains = <&power RK3568_PD_VO>;
798 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
801 clock-names = "pclk";
803 phy-names = "dphy";
805 power-domains = <&power RK3568_PD_VO>;
806 reset-names = "apb";
808 rockchip,grf = <&grf>;
812 #address-cells = <1>;
813 #size-cells = <0>;
826 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
829 clock-names = "pclk";
831 phy-names = "dphy";
833 power-domains = <&power RK3568_PD_VO>;
834 reset-names = "apb";
836 rockchip,grf = <&grf>;
840 #address-cells = <1>;
841 #size-cells = <0>;
854 compatible = "rockchip,rk3568-dw-hdmi";
862 clock-names = "iahb", "isfr", "cec", "ref";
863 pinctrl-names = "default";
864 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
865 power-domains = <&power RK3568_PD_VO>;
866 reg-io-width = <4>;
867 rockchip,grf = <&grf>;
868 #sound-dai-cells = <0>;
872 #address-cells = <1>;
873 #size-cells = <0>;
886 compatible = "rockchip,rk3568-qos", "syscon";
891 compatible = "rockchip,rk3568-qos", "syscon";
896 compatible = "rockchip,rk3568-qos", "syscon";
901 compatible = "rockchip,rk3568-qos", "syscon";
906 compatible = "rockchip,rk3568-qos", "syscon";
911 compatible = "rockchip,rk3568-qos", "syscon";
916 compatible = "rockchip,rk3568-qos", "syscon";
921 compatible = "rockchip,rk3568-qos", "syscon";
926 compatible = "rockchip,rk3568-qos", "syscon";
931 compatible = "rockchip,rk3568-qos", "syscon";
936 compatible = "rockchip,rk3568-qos", "syscon";
941 compatible = "rockchip,rk3568-qos", "syscon";
946 compatible = "rockchip,rk3568-qos", "syscon";
951 compatible = "rockchip,rk3568-qos", "syscon";
956 compatible = "rockchip,rk3568-qos", "syscon";
961 compatible = "rockchip,rk3568-qos", "syscon";
966 compatible = "rockchip,rk3568-qos", "syscon";
971 compatible = "rockchip,rk3568-qos", "syscon";
976 compatible = "rockchip,rk3568-qos", "syscon";
981 compatible = "rockchip,rk3568-qos", "syscon";
986 compatible = "rockchip,rk3568-qos", "syscon";
991 compatible = "rockchip,rk3568-qos", "syscon";
996 compatible = "rockchip,rk3568-qos", "syscon";
1001 compatible = "rockchip,rk3568-qos", "syscon";
1006 compatible = "rockchip,rk3568-dfi";
1013 compatible = "rockchip,rk3568-pcie";
1017 reg-names = "dbi", "apb", "config";
1023 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1024 bus-range = <0x0 0xf>;
1028 clock-names = "aclk_mst", "aclk_slv",
1031 #interrupt-cells = <1>;
1032 interrupt-map-mask = <0 0 0 7>;
1033 interrupt-map = <0 0 0 1 &pcie_intc 0>,
1037 linux,pci-domain = <0>;
1038 num-ib-windows = <6>;
1039 num-ob-windows = <2>;
1040 max-link-speed = <2>;
1041 msi-map = <0x0 &gic 0x0 0x1000>;
1042 num-lanes = <1>;
1044 phy-names = "pcie-phy";
1045 power-domains = <&power RK3568_PD_PIPE>;
1050 reset-names = "pipe";
1051 #address-cells = <3>;
1052 #size-cells = <2>;
1055 pcie_intc: legacy-interrupt-controller {
1056 #address-cells = <0>;
1057 #interrupt-cells = <1>;
1058 interrupt-controller;
1059 interrupt-parent = <&gic>;
1065 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1070 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1071 fifo-depth = <0x100>;
1072 max-frequency = <150000000>;
1074 reset-names = "reset";
1079 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1084 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1085 fifo-depth = <0x100>;
1086 max-frequency = <150000000>;
1088 reset-names = "reset";
1097 clock-names = "clk_sfc", "hclk_sfc";
1098 pinctrl-0 = <&fspi_pins>;
1099 pinctrl-names = "default";
1104 compatible = "rockchip,rk3568-dwcmshc";
1107 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
1108 assigned-clock-rates = <200000000>, <24000000>;
1112 clock-names = "core", "bus", "axi", "block", "timer";
1117 compatible = "rockchip,rk3568-rng";
1120 clock-names = "core", "ahb";
1126 compatible = "rockchip,rk3568-i2s-tdm";
1129 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1130 assigned-clock-rates = <1188000000>, <1188000000>;
1132 clock-names = "mclk_tx", "mclk_rx", "hclk";
1134 dma-names = "tx";
1136 reset-names = "tx-m", "rx-m";
1137 rockchip,grf = <&grf>;
1138 #sound-dai-cells = <0>;
1143 compatible = "rockchip,rk3568-i2s-tdm";
1146 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
1147 assigned-clock-rates = <1188000000>, <1188000000>;
1150 clock-names = "mclk_tx", "mclk_rx", "hclk";
1152 dma-names = "rx", "tx";
1154 reset-names = "tx-m", "rx-m";
1155 rockchip,grf = <&grf>;
1156 pinctrl-names = "default";
1157 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
1163 #sound-dai-cells = <0>;
1168 compatible = "rockchip,rk3568-i2s-tdm";
1171 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1172 assigned-clock-rates = <1188000000>;
1174 clock-names = "mclk_tx", "mclk_rx", "hclk";
1176 dma-names = "tx", "rx";
1178 reset-names = "tx-m";
1179 rockchip,grf = <&grf>;
1180 pinctrl-names = "default";
1181 pinctrl-0 = <&i2s2m0_sclktx
1185 #sound-dai-cells = <0>;
1190 compatible = "rockchip,rk3568-i2s-tdm";
1195 clock-names = "mclk_tx", "mclk_rx", "hclk";
1197 dma-names = "tx", "rx";
1199 reset-names = "tx-m", "rx-m";
1200 rockchip,grf = <&grf>;
1201 #sound-dai-cells = <0>;
1206 compatible = "rockchip,rk3568-pdm";
1210 clock-names = "pdm_clk", "pdm_hclk";
1212 dma-names = "rx";
1213 pinctrl-0 = <&pdmm0_clk
1219 pinctrl-names = "default";
1221 reset-names = "pdm-m";
1222 #sound-dai-cells = <0>;
1227 compatible = "rockchip,rk3568-spdif";
1230 clock-names = "mclk", "hclk";
1233 dma-names = "tx";
1234 pinctrl-names = "default";
1235 pinctrl-0 = <&spdifm0_tx>;
1236 #sound-dai-cells = <0>;
1240 dmac0: dma-controller@fe530000 {
1245 arm,pl330-periph-burst;
1247 clock-names = "apb_pclk";
1248 #dma-cells = <1>;
1251 dmac1: dma-controller@fe550000 {
1256 arm,pl330-periph-burst;
1258 clock-names = "apb_pclk";
1259 #dma-cells = <1>;
1263 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1267 clock-names = "i2c", "pclk";
1268 pinctrl-0 = <&i2c1_xfer>;
1269 pinctrl-names = "default";
1270 #address-cells = <1>;
1271 #size-cells = <0>;
1276 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1280 clock-names = "i2c", "pclk";
1281 pinctrl-0 = <&i2c2m0_xfer>;
1282 pinctrl-names = "default";
1283 #address-cells = <1>;
1284 #size-cells = <0>;
1289 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1293 clock-names = "i2c", "pclk";
1294 pinctrl-0 = <&i2c3m0_xfer>;
1295 pinctrl-names = "default";
1296 #address-cells = <1>;
1297 #size-cells = <0>;
1302 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1306 clock-names = "i2c", "pclk";
1307 pinctrl-0 = <&i2c4m0_xfer>;
1308 pinctrl-names = "default";
1309 #address-cells = <1>;
1310 #size-cells = <0>;
1315 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1319 clock-names = "i2c", "pclk";
1320 pinctrl-0 = <&i2c5m0_xfer>;
1321 pinctrl-names = "default";
1322 #address-cells = <1>;
1323 #size-cells = <0>;
1328 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
1332 clock-names = "tclk", "pclk";
1336 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1340 clock-names = "spiclk", "apb_pclk";
1342 dma-names = "tx", "rx";
1343 pinctrl-names = "default";
1344 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1345 #address-cells = <1>;
1346 #size-cells = <0>;
1351 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1355 clock-names = "spiclk", "apb_pclk";
1357 dma-names = "tx", "rx";
1358 pinctrl-names = "default";
1359 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1360 #address-cells = <1>;
1361 #size-cells = <0>;
1366 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1370 clock-names = "spiclk", "apb_pclk";
1372 dma-names = "tx", "rx";
1373 pinctrl-names = "default";
1374 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1375 #address-cells = <1>;
1376 #size-cells = <0>;
1381 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1385 clock-names = "spiclk", "apb_pclk";
1387 dma-names = "tx", "rx";
1388 pinctrl-names = "default";
1389 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
1390 #address-cells = <1>;
1391 #size-cells = <0>;
1396 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1400 clock-names = "baudclk", "apb_pclk";
1402 pinctrl-0 = <&uart1m0_xfer>;
1403 pinctrl-names = "default";
1404 reg-io-width = <4>;
1405 reg-shift = <2>;
1410 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1414 clock-names = "baudclk", "apb_pclk";
1416 pinctrl-0 = <&uart2m0_xfer>;
1417 pinctrl-names = "default";
1418 reg-io-width = <4>;
1419 reg-shift = <2>;
1424 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1428 clock-names = "baudclk", "apb_pclk";
1430 pinctrl-0 = <&uart3m0_xfer>;
1431 pinctrl-names = "default";
1432 reg-io-width = <4>;
1433 reg-shift = <2>;
1438 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1442 clock-names = "baudclk", "apb_pclk";
1444 pinctrl-0 = <&uart4m0_xfer>;
1445 pinctrl-names = "default";
1446 reg-io-width = <4>;
1447 reg-shift = <2>;
1452 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1456 clock-names = "baudclk", "apb_pclk";
1458 pinctrl-0 = <&uart5m0_xfer>;
1459 pinctrl-names = "default";
1460 reg-io-width = <4>;
1461 reg-shift = <2>;
1466 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1470 clock-names = "baudclk", "apb_pclk";
1472 pinctrl-0 = <&uart6m0_xfer>;
1473 pinctrl-names = "default";
1474 reg-io-width = <4>;
1475 reg-shift = <2>;
1480 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1484 clock-names = "baudclk", "apb_pclk";
1486 pinctrl-0 = <&uart7m0_xfer>;
1487 pinctrl-names = "default";
1488 reg-io-width = <4>;
1489 reg-shift = <2>;
1494 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1498 clock-names = "baudclk", "apb_pclk";
1500 pinctrl-0 = <&uart8m0_xfer>;
1501 pinctrl-names = "default";
1502 reg-io-width = <4>;
1503 reg-shift = <2>;
1508 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1512 clock-names = "baudclk", "apb_pclk";
1514 pinctrl-0 = <&uart9m0_xfer>;
1515 pinctrl-names = "default";
1516 reg-io-width = <4>;
1517 reg-shift = <2>;
1521 thermal_zones: thermal-zones {
1522 cpu_thermal: cpu-thermal {
1523 polling-delay-passive = <100>;
1524 polling-delay = <1000>;
1526 thermal-sensors = <&tsadc 0>;
1546 cooling-maps {
1549 cooling-device =
1558 gpu_thermal: gpu-thermal {
1559 polling-delay-passive = <20>; /* milliseconds */
1560 polling-delay = <1000>; /* milliseconds */
1562 thermal-sensors = <&tsadc 1>;
1565 gpu_threshold: gpu-threshold {
1570 gpu_target: gpu-target {
1575 gpu_crit: gpu-crit {
1582 cooling-maps {
1585 cooling-device =
1593 compatible = "rockchip,rk3568-tsadc";
1596 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
1597 assigned-clock-rates = <17000000>, <700000>;
1599 clock-names = "tsadc", "apb_pclk";
1602 rockchip,grf = <&grf>;
1603 rockchip,hw-tshut-temp = <95000>;
1604 pinctrl-names = "default", "sleep";
1605 pinctrl-0 = <&tsadc_shutorg>;
1606 pinctrl-1 = <&tsadc_pin>;
1607 #thermal-sensor-cells = <1>;
1612 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
1616 clock-names = "saradc", "apb_pclk";
1618 reset-names = "saradc-apb";
1619 #io-channel-cells = <1>;
1624 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1627 clock-names = "pwm", "pclk";
1628 pinctrl-0 = <&pwm4_pins>;
1629 pinctrl-names = "default";
1630 #pwm-cells = <3>;
1635 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1638 clock-names = "pwm", "pclk";
1639 pinctrl-0 = <&pwm5_pins>;
1640 pinctrl-names = "default";
1641 #pwm-cells = <3>;
1646 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1649 clock-names = "pwm", "pclk";
1650 pinctrl-0 = <&pwm6_pins>;
1651 pinctrl-names = "default";
1652 #pwm-cells = <3>;
1657 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1660 clock-names = "pwm", "pclk";
1661 pinctrl-0 = <&pwm7_pins>;
1662 pinctrl-names = "default";
1663 #pwm-cells = <3>;
1668 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1671 clock-names = "pwm", "pclk";
1672 pinctrl-0 = <&pwm8m0_pins>;
1673 pinctrl-names = "default";
1674 #pwm-cells = <3>;
1679 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1682 clock-names = "pwm", "pclk";
1683 pinctrl-0 = <&pwm9m0_pins>;
1684 pinctrl-names = "default";
1685 #pwm-cells = <3>;
1690 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1693 clock-names = "pwm", "pclk";
1694 pinctrl-0 = <&pwm10m0_pins>;
1695 pinctrl-names = "default";
1696 #pwm-cells = <3>;
1701 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1704 clock-names = "pwm", "pclk";
1705 pinctrl-0 = <&pwm11m0_pins>;
1706 pinctrl-names = "default";
1707 #pwm-cells = <3>;
1712 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1715 clock-names = "pwm", "pclk";
1716 pinctrl-0 = <&pwm12m0_pins>;
1717 pinctrl-names = "default";
1718 #pwm-cells = <3>;
1723 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1726 clock-names = "pwm", "pclk";
1727 pinctrl-0 = <&pwm13m0_pins>;
1728 pinctrl-names = "default";
1729 #pwm-cells = <3>;
1734 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1737 clock-names = "pwm", "pclk";
1738 pinctrl-0 = <&pwm14m0_pins>;
1739 pinctrl-names = "default";
1740 #pwm-cells = <3>;
1745 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1748 clock-names = "pwm", "pclk";
1749 pinctrl-0 = <&pwm15m0_pins>;
1750 pinctrl-names = "default";
1751 #pwm-cells = <3>;
1756 compatible = "rockchip,rk3568-naneng-combphy";
1761 clock-names = "ref", "apb", "pipe";
1762 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
1763 assigned-clock-rates = <100000000>;
1765 rockchip,pipe-grf = <&pipegrf>;
1766 rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
1767 #phy-cells = <1>;
1772 compatible = "rockchip,rk3568-naneng-combphy";
1777 clock-names = "ref", "apb", "pipe";
1778 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
1779 assigned-clock-rates = <100000000>;
1781 rockchip,pipe-grf = <&pipegrf>;
1782 rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
1783 #phy-cells = <1>;
1788 compatible = "rockchip,rk3568-csi-dphy";
1791 clock-names = "pclk";
1792 #phy-cells = <0>;
1794 reset-names = "apb";
1795 rockchip,grf = <&grf>;
1799 dsi_dphy0: mipi-dphy@fe850000 {
1800 compatible = "rockchip,rk3568-dsi-dphy";
1802 clock-names = "ref", "pclk";
1804 #phy-cells = <0>;
1805 power-domains = <&power RK3568_PD_VO>;
1806 reset-names = "apb";
1811 dsi_dphy1: mipi-dphy@fe860000 {
1812 compatible = "rockchip,rk3568-dsi-dphy";
1814 clock-names = "ref", "pclk";
1816 #phy-cells = <0>;
1817 power-domains = <&power RK3568_PD_VO>;
1818 reset-names = "apb";
1824 compatible = "rockchip,rk3568-usb2phy";
1827 clock-names = "phyclk";
1828 clock-output-names = "clk_usbphy0_480m";
1831 #clock-cells = <0>;
1834 usb2phy0_host: host-port {
1835 #phy-cells = <0>;
1839 usb2phy0_otg: otg-port {
1840 #phy-cells = <0>;
1846 compatible = "rockchip,rk3568-usb2phy";
1849 clock-names = "phyclk";
1850 clock-output-names = "clk_usbphy1_480m";
1853 #clock-cells = <0>;
1856 usb2phy1_host: host-port {
1857 #phy-cells = <0>;
1861 usb2phy1_otg: otg-port {
1862 #phy-cells = <0>;
1868 compatible = "rockchip,rk3568-pinctrl";
1869 rockchip,grf = <&grf>;
1871 #address-cells = <2>;
1872 #size-cells = <2>;
1875 gpio0: gpio@fdd60000 {
1876 compatible = "rockchip,gpio-bank";
1880 gpio-controller;
1881 gpio-ranges = <&pinctrl 0 0 32>;
1882 #gpio-cells = <2>;
1883 interrupt-controller;
1884 #interrupt-cells = <2>;
1887 gpio1: gpio@fe740000 {
1888 compatible = "rockchip,gpio-bank";
1892 gpio-controller;
1893 gpio-ranges = <&pinctrl 0 32 32>;
1894 #gpio-cells = <2>;
1895 interrupt-controller;
1896 #interrupt-cells = <2>;
1899 gpio2: gpio@fe750000 {
1900 compatible = "rockchip,gpio-bank";
1904 gpio-controller;
1905 gpio-ranges = <&pinctrl 0 64 32>;
1906 #gpio-cells = <2>;
1907 interrupt-controller;
1908 #interrupt-cells = <2>;
1911 gpio3: gpio@fe760000 {
1912 compatible = "rockchip,gpio-bank";
1916 gpio-controller;
1917 gpio-ranges = <&pinctrl 0 96 32>;
1918 #gpio-cells = <2>;
1919 interrupt-controller;
1920 #interrupt-cells = <2>;
1923 gpio4: gpio@fe770000 {
1924 compatible = "rockchip,gpio-bank";
1928 gpio-controller;
1929 gpio-ranges = <&pinctrl 0 128 32>;
1930 #gpio-cells = <2>;
1931 interrupt-controller;
1932 #interrupt-cells = <2>;
1937 #include "rk3568-pinctrl.dtsi"