Lines Matching full:cru
6 #include <dt-bindings/clock/rk3568-cru.h>
298 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
299 <&cru CLK_SATA1_RXOOB>;
312 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
313 <&cru CLK_SATA2_RXOOB>;
327 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
328 <&cru ACLK_USB3OTG0>;
334 resets = <&cru SRST_USB3OTG0>;
343 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
344 <&cru ACLK_USB3OTG1>;
352 resets = <&cru SRST_USB3OTG1>;
373 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
374 <&cru PCLK_USB>;
384 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
385 <&cru PCLK_USB>;
395 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
396 <&cru PCLK_USB>;
406 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
407 <&cru PCLK_USB>;
459 cru: clock-controller@fdd20000 { label
460 compatible = "rockchip,rk3568-cru";
466 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
556 clocks = <&cru ACLK_GPU_PRE>,
557 <&cru PCLK_GPU_PRE>;
565 clocks = <&cru HCLK_VI>,
566 <&cru PCLK_VI>;
575 clocks = <&cru HCLK_VO>,
576 <&cru PCLK_VO>,
577 <&cru ACLK_VOP_PRE>;
586 clocks = <&cru HCLK_RGA_PRE>,
587 <&cru PCLK_RGA_PRE>;
599 clocks = <&cru HCLK_VPU_PRE>;
605 clocks = <&cru HCLK_RKVDEC_PRE>;
613 clocks = <&cru HCLK_RKVENC_PRE>;
629 clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
642 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
653 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
662 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>;
664 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
673 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
683 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
693 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
694 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
698 resets = <&cru SRST_SDMMC2>;
709 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
710 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
711 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
712 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
717 resets = <&cru SRST_A_GMAC1>;
754 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>,
755 <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
790 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
802 clocks = <&cru PCLK_DSITX_0>;
807 resets = <&cru SRST_P_DSITX_0>;
830 clocks = <&cru PCLK_DSITX_1>;
835 resets = <&cru SRST_P_DSITX_1>;
857 clocks = <&cru PCLK_HDMI_HOST>,
858 <&cru CLK_HDMI_SFR>,
859 <&cru CLK_HDMI_CEC>,
861 <&cru HCLK_VO>;
1025 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
1026 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
1027 <&cru CLK_PCIE20_AUX_NDFT>;
1049 resets = <&cru SRST_PCIE20_POWERUP>;
1068 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
1069 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
1073 resets = <&cru SRST_SDMMC0>;
1082 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
1083 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
1087 resets = <&cru SRST_SDMMC1>;
1096 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1107 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
1109 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1110 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1111 <&cru TCLK_EMMC>;
1119 clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
1121 resets = <&cru SRST_TRNG_NS>;
1129 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1131 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1135 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1146 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
1148 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>,
1149 <&cru HCLK_I2S1_8CH>;
1153 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1171 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1173 clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
1177 resets = <&cru SRST_M_I2S2_2CH>;
1193 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>,
1194 <&cru HCLK_I2S3_2CH>;
1198 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>;
1209 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
1220 resets = <&cru SRST_M_PDM>;
1231 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
1246 clocks = <&cru ACLK_BUS>;
1257 clocks = <&cru ACLK_BUS>;
1266 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1279 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1292 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1305 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1318 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1331 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
1339 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1354 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1369 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1384 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
1399 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1413 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1427 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1441 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1455 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1469 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1483 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1497 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1511 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1596 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
1598 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
1600 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>,
1601 <&cru SRST_TSADCPHY>;
1615 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
1617 resets = <&cru SRST_P_SARADC>;
1626 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1637 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1648 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1659 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1670 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1681 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1692 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1703 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1714 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1725 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1736 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1747 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1759 <&cru PCLK_PIPEPHY1>,
1760 <&cru PCLK_PIPE>;
1764 resets = <&cru SRST_PIPEPHY1>;
1775 <&cru PCLK_PIPEPHY2>,
1776 <&cru PCLK_PIPE>;
1780 resets = <&cru SRST_PIPEPHY2>;
1790 clocks = <&cru PCLK_MIPICSIPHY>;
1793 resets = <&cru SRST_P_MIPICSIPHY>;
1803 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>;
1807 resets = <&cru SRST_P_MIPIDSIPHY0>;
1815 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
1819 resets = <&cru SRST_P_MIPIDSIPHY1>;
1891 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
1903 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
1915 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
1927 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;