Lines Matching +full:0 +full:xfe388000
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&scmi_clk 0>;
60 i-cache-size = <0x8000>;
63 d-cache-size = <0x8000>;
72 reg = <0x0 0x100>;
76 i-cache-size = <0x8000>;
79 d-cache-size = <0x8000>;
88 reg = <0x0 0x200>;
92 i-cache-size = <0x8000>;
95 d-cache-size = <0x8000>;
104 reg = <0x0 0x300>;
108 i-cache-size = <0x8000>;
111 d-cache-size = <0x8000>;
126 cache-size = <0x80000>;
131 cpu0_opp_table: opp-table-0 {
181 arm,smc-id = <0x82000010>;
184 #size-cells = <0>;
187 reg = <0x14>;
270 #clock-cells = <0>;
277 pinctrl-0 = <&clk32k_out0>;
279 #clock-cells = <0>;
284 reg = <0x0 0x0010f000 0x0 0x100>;
287 ranges = <0 0x0 0x0010f000 0x100>;
289 scmi_shmem: sram@0 {
291 reg = <0x0 0x100>;
297 reg = <0 0xfc400000 0 0x1000>;
304 ports-implemented = <0x1>;
311 reg = <0 0xfc800000 0 0x1000>;
318 ports-implemented = <0x1>;
325 reg = <0x0 0xfcc00000 0x0 0x400000>;
341 reg = <0x0 0xfd000000 0x0 0x400000>;
359 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
360 <0x0 0xfd460000 0 0x80000>; /* GICR */
364 mbi-alias = <0x0 0xfd410000>;
371 reg = <0x0 0xfd800000 0x0 0x40000>;
382 reg = <0x0 0xfd840000 0x0 0x40000>;
393 reg = <0x0 0xfd880000 0x0 0x40000>;
404 reg = <0x0 0xfd8c0000 0x0 0x40000>;
415 reg = <0x0 0xfdc20000 0x0 0x10000>;
424 reg = <0x0 0xfdc50000 0x0 0x1000>;
429 reg = <0x0 0xfdc60000 0x0 0x10000>;
434 reg = <0x0 0xfdc80000 0x0 0x1000>;
439 reg = <0x0 0xfdc90000 0x0 0x1000>;
444 reg = <0x0 0xfdca0000 0x0 0x8000>;
449 reg = <0x0 0xfdca8000 0x0 0x8000>;
454 reg = <0x0 0xfdd00000 0x0 0x1000>;
461 reg = <0x0 0xfdd20000 0x0 0x1000>;
474 reg = <0x0 0xfdd40000 0x0 0x1000>;
478 pinctrl-0 = <&i2c0_xfer>;
481 #size-cells = <0>;
487 reg = <0x0 0xfdd50000 0x0 0x100>;
491 dmas = <&dmac0 0>, <&dmac0 1>;
492 pinctrl-0 = <&uart0_xfer>;
501 reg = <0x0 0xfdd70000 0x0 0x10>;
504 pinctrl-0 = <&pwm0m0_pins>;
512 reg = <0x0 0xfdd70010 0x0 0x10>;
515 pinctrl-0 = <&pwm1m0_pins>;
523 reg = <0x0 0xfdd70020 0x0 0x10>;
526 pinctrl-0 = <&pwm2m0_pins>;
534 reg = <0x0 0xfdd70030 0x0 0x10>;
537 pinctrl-0 = <&pwm3_pins>;
545 reg = <0x0 0xfdd90000 0x0 0x1000>;
551 #size-cells = <0>;
559 #power-domain-cells = <0>;
570 #power-domain-cells = <0>;
581 #power-domain-cells = <0>;
594 #power-domain-cells = <0>;
601 #power-domain-cells = <0>;
608 #power-domain-cells = <0>;
617 #power-domain-cells = <0>;
624 reg = <0x0 0xfde60000 0x0 0x4000>;
639 reg = <0x0 0xfdea0000 0x0 0x800>;
650 reg = <0x0 0xfdea0800 0x0 0x40>;
655 #iommu-cells = <0>;
660 reg = <0x0 0xfdeb0000 0x0 0x180>;
671 reg = <0x0 0xfdee0000 0x0 0x800>;
681 reg = <0x0 0xfdee0800 0x0 0x40>;
686 #iommu-cells = <0>;
691 reg = <0x0 0xfe000000 0x0 0x4000>;
696 fifo-depth = <0x100>;
705 reg = <0x0 0xfe010000 0x0 0x10000>;
729 #address-cells = <0x1>;
730 #size-cells = <0x0>;
734 snps,blen = <0 0 0 0 16 8 4>;
751 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
764 #size-cells = <0>;
766 vp0: port@0 {
767 reg = <0>;
769 #size-cells = <0>;
775 #size-cells = <0>;
781 #size-cells = <0>;
788 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
792 #iommu-cells = <0>;
799 reg = <0x00 0xfe060000 0x00 0x10000>;
813 #size-cells = <0>;
815 dsi0_in: port@0 {
816 reg = <0>;
827 reg = <0x0 0xfe070000 0x0 0x10000>;
841 #size-cells = <0>;
843 dsi1_in: port@0 {
844 reg = <0>;
855 reg = <0x0 0xfe0a0000 0x0 0x20000>;
864 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
868 #sound-dai-cells = <0>;
873 #size-cells = <0>;
875 hdmi_in: port@0 {
876 reg = <0>;
887 reg = <0x0 0xfe128000 0x0 0x20>;
892 reg = <0x0 0xfe138080 0x0 0x20>;
897 reg = <0x0 0xfe138100 0x0 0x20>;
902 reg = <0x0 0xfe138180 0x0 0x20>;
907 reg = <0x0 0xfe148000 0x0 0x20>;
912 reg = <0x0 0xfe148080 0x0 0x20>;
917 reg = <0x0 0xfe148100 0x0 0x20>;
922 reg = <0x0 0xfe150000 0x0 0x20>;
927 reg = <0x0 0xfe158000 0x0 0x20>;
932 reg = <0x0 0xfe158100 0x0 0x20>;
937 reg = <0x0 0xfe158180 0x0 0x20>;
942 reg = <0x0 0xfe158200 0x0 0x20>;
947 reg = <0x0 0xfe158280 0x0 0x20>;
952 reg = <0x0 0xfe158300 0x0 0x20>;
957 reg = <0x0 0xfe180000 0x0 0x20>;
962 reg = <0x0 0xfe190000 0x0 0x20>;
967 reg = <0x0 0xfe190280 0x0 0x20>;
972 reg = <0x0 0xfe190300 0x0 0x20>;
977 reg = <0x0 0xfe190380 0x0 0x20>;
982 reg = <0x0 0xfe190400 0x0 0x20>;
987 reg = <0x0 0xfe198000 0x0 0x20>;
992 reg = <0x0 0xfe1a8000 0x0 0x20>;
997 reg = <0x0 0xfe1a8080 0x0 0x20>;
1002 reg = <0x0 0xfe1a8100 0x0 0x20>;
1007 reg = <0x00 0xfe230000 0x00 0x400>;
1014 reg = <0x3 0xc0000000 0x0 0x00400000>,
1015 <0x0 0xfe260000 0x0 0x00010000>,
1016 <0x0 0xf4000000 0x0 0x00100000>;
1024 bus-range = <0x0 0xf>;
1032 interrupt-map-mask = <0 0 0 7>;
1033 interrupt-map = <0 0 0 1 &pcie_intc 0>,
1034 <0 0 0 2 &pcie_intc 1>,
1035 <0 0 0 3 &pcie_intc 2>,
1036 <0 0 0 4 &pcie_intc 3>;
1037 linux,pci-domain = <0>;
1041 msi-map = <0x0 &gic 0x0 0x1000>;
1046 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
1047 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
1048 <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
1056 #address-cells = <0>;
1066 reg = <0x0 0xfe2b0000 0x0 0x4000>;
1071 fifo-depth = <0x100>;
1080 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1085 fifo-depth = <0x100>;
1094 reg = <0x0 0xfe300000 0x0 0x4000>;
1098 pinctrl-0 = <&fspi_pins>;
1105 reg = <0x0 0xfe310000 0x0 0x10000>;
1118 reg = <0x0 0xfe388000 0x0 0x4000>;
1127 reg = <0x0 0xfe400000 0x0 0x1000>;
1133 dmas = <&dmac1 0>;
1138 #sound-dai-cells = <0>;
1144 reg = <0x0 0xfe410000 0x0 0x1000>;
1157 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
1163 #sound-dai-cells = <0>;
1169 reg = <0x0 0xfe420000 0x0 0x1000>;
1181 pinctrl-0 = <&i2s2m0_sclktx
1185 #sound-dai-cells = <0>;
1191 reg = <0x0 0xfe430000 0x0 0x1000>;
1201 #sound-dai-cells = <0>;
1207 reg = <0x0 0xfe440000 0x0 0x1000>;
1213 pinctrl-0 = <&pdmm0_clk
1222 #sound-dai-cells = <0>;
1228 reg = <0x0 0xfe460000 0x0 0x1000>;
1235 pinctrl-0 = <&spdifm0_tx>;
1236 #sound-dai-cells = <0>;
1242 reg = <0x0 0xfe530000 0x0 0x4000>;
1253 reg = <0x0 0xfe550000 0x0 0x4000>;
1264 reg = <0x0 0xfe5a0000 0x0 0x1000>;
1268 pinctrl-0 = <&i2c1_xfer>;
1271 #size-cells = <0>;
1277 reg = <0x0 0xfe5b0000 0x0 0x1000>;
1281 pinctrl-0 = <&i2c2m0_xfer>;
1284 #size-cells = <0>;
1290 reg = <0x0 0xfe5c0000 0x0 0x1000>;
1294 pinctrl-0 = <&i2c3m0_xfer>;
1297 #size-cells = <0>;
1303 reg = <0x0 0xfe5d0000 0x0 0x1000>;
1307 pinctrl-0 = <&i2c4m0_xfer>;
1310 #size-cells = <0>;
1316 reg = <0x0 0xfe5e0000 0x0 0x1000>;
1320 pinctrl-0 = <&i2c5m0_xfer>;
1323 #size-cells = <0>;
1329 reg = <0x0 0xfe600000 0x0 0x100>;
1337 reg = <0x0 0xfe610000 0x0 0x1000>;
1344 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1346 #size-cells = <0>;
1352 reg = <0x0 0xfe620000 0x0 0x1000>;
1359 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1361 #size-cells = <0>;
1367 reg = <0x0 0xfe630000 0x0 0x1000>;
1374 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1376 #size-cells = <0>;
1382 reg = <0x0 0xfe640000 0x0 0x1000>;
1389 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
1391 #size-cells = <0>;
1397 reg = <0x0 0xfe650000 0x0 0x100>;
1402 pinctrl-0 = <&uart1m0_xfer>;
1411 reg = <0x0 0xfe660000 0x0 0x100>;
1416 pinctrl-0 = <&uart2m0_xfer>;
1425 reg = <0x0 0xfe670000 0x0 0x100>;
1430 pinctrl-0 = <&uart3m0_xfer>;
1439 reg = <0x0 0xfe680000 0x0 0x100>;
1444 pinctrl-0 = <&uart4m0_xfer>;
1453 reg = <0x0 0xfe690000 0x0 0x100>;
1458 pinctrl-0 = <&uart5m0_xfer>;
1467 reg = <0x0 0xfe6a0000 0x0 0x100>;
1472 pinctrl-0 = <&uart6m0_xfer>;
1481 reg = <0x0 0xfe6b0000 0x0 0x100>;
1486 pinctrl-0 = <&uart7m0_xfer>;
1495 reg = <0x0 0xfe6c0000 0x0 0x100>;
1500 pinctrl-0 = <&uart8m0_xfer>;
1509 reg = <0x0 0xfe6d0000 0x0 0x100>;
1514 pinctrl-0 = <&uart9m0_xfer>;
1526 thermal-sensors = <&tsadc 0>;
1594 reg = <0x0 0xfe710000 0x0 0x100>;
1605 pinctrl-0 = <&tsadc_shutorg>;
1613 reg = <0x0 0xfe720000 0x0 0x100>;
1625 reg = <0x0 0xfe6e0000 0x0 0x10>;
1628 pinctrl-0 = <&pwm4_pins>;
1636 reg = <0x0 0xfe6e0010 0x0 0x10>;
1639 pinctrl-0 = <&pwm5_pins>;
1647 reg = <0x0 0xfe6e0020 0x0 0x10>;
1650 pinctrl-0 = <&pwm6_pins>;
1658 reg = <0x0 0xfe6e0030 0x0 0x10>;
1661 pinctrl-0 = <&pwm7_pins>;
1669 reg = <0x0 0xfe6f0000 0x0 0x10>;
1672 pinctrl-0 = <&pwm8m0_pins>;
1680 reg = <0x0 0xfe6f0010 0x0 0x10>;
1683 pinctrl-0 = <&pwm9m0_pins>;
1691 reg = <0x0 0xfe6f0020 0x0 0x10>;
1694 pinctrl-0 = <&pwm10m0_pins>;
1702 reg = <0x0 0xfe6f0030 0x0 0x10>;
1705 pinctrl-0 = <&pwm11m0_pins>;
1713 reg = <0x0 0xfe700000 0x0 0x10>;
1716 pinctrl-0 = <&pwm12m0_pins>;
1724 reg = <0x0 0xfe700010 0x0 0x10>;
1727 pinctrl-0 = <&pwm13m0_pins>;
1735 reg = <0x0 0xfe700020 0x0 0x10>;
1738 pinctrl-0 = <&pwm14m0_pins>;
1746 reg = <0x0 0xfe700030 0x0 0x10>;
1749 pinctrl-0 = <&pwm15m0_pins>;
1757 reg = <0x0 0xfe830000 0x0 0x100>;
1773 reg = <0x0 0xfe840000 0x0 0x100>;
1789 reg = <0x0 0xfe870000 0x0 0x10000>;
1792 #phy-cells = <0>;
1801 reg = <0x0 0xfe850000 0x0 0x10000>;
1804 #phy-cells = <0>;
1813 reg = <0x0 0xfe860000 0x0 0x10000>;
1816 #phy-cells = <0>;
1825 reg = <0x0 0xfe8a0000 0x0 0x10000>;
1831 #clock-cells = <0>;
1835 #phy-cells = <0>;
1840 #phy-cells = <0>;
1847 reg = <0x0 0xfe8b0000 0x0 0x10000>;
1853 #clock-cells = <0>;
1857 #phy-cells = <0>;
1862 #phy-cells = <0>;
1877 reg = <0x0 0xfdd60000 0x0 0x100>;
1881 gpio-ranges = <&pinctrl 0 0 32>;
1889 reg = <0x0 0xfe740000 0x0 0x100>;
1893 gpio-ranges = <&pinctrl 0 32 32>;
1901 reg = <0x0 0xfe750000 0x0 0x100>;
1905 gpio-ranges = <&pinctrl 0 64 32>;
1913 reg = <0x0 0xfe760000 0x0 0x100>;
1917 gpio-ranges = <&pinctrl 0 96 32>;
1925 reg = <0x0 0xfe770000 0x0 0x100>;
1929 gpio-ranges = <&pinctrl 0 128 32>;