Lines Matching +full:tsadc +full:- +full:apb
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
49 #address-cells = <2>;
50 #size-cells = <0>;
54 compatible = "arm,cortex-a55";
57 #cooling-cells = <2>;
58 enable-method = "psci";
59 i-cache-size = <0x8000>;
60 i-cache-line-size = <64>;
61 i-cache-sets = <128>;
62 d-cache-size = <0x8000>;
63 d-cache-line-size = <64>;
64 d-cache-sets = <128>;
65 next-level-cache = <&l3_cache>;
70 compatible = "arm,cortex-a55";
72 #cooling-cells = <2>;
73 enable-method = "psci";
74 i-cache-size = <0x8000>;
75 i-cache-line-size = <64>;
76 i-cache-sets = <128>;
77 d-cache-size = <0x8000>;
78 d-cache-line-size = <64>;
79 d-cache-sets = <128>;
80 next-level-cache = <&l3_cache>;
85 compatible = "arm,cortex-a55";
87 #cooling-cells = <2>;
88 enable-method = "psci";
89 i-cache-size = <0x8000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <128>;
92 d-cache-size = <0x8000>;
93 d-cache-line-size = <64>;
94 d-cache-sets = <128>;
95 next-level-cache = <&l3_cache>;
100 compatible = "arm,cortex-a55";
102 #cooling-cells = <2>;
103 enable-method = "psci";
104 i-cache-size = <0x8000>;
105 i-cache-line-size = <64>;
106 i-cache-sets = <128>;
107 d-cache-size = <0x8000>;
108 d-cache-line-size = <64>;
109 d-cache-sets = <128>;
110 next-level-cache = <&l3_cache>;
115 * There are no private per-core L2 caches, but only the
118 l3_cache: l3-cache {
120 cache-level = <2>;
121 cache-unified;
122 cache-size = <0x80000>;
123 cache-line-size = <64>;
124 cache-sets = <512>;
127 display_subsystem: display-subsystem {
128 compatible = "rockchip,display-subsystem";
134 compatible = "arm,scmi-smc";
135 arm,smc-id = <0x82000010>;
137 #address-cells = <1>;
138 #size-cells = <0>;
142 #clock-cells = <1>;
147 hdmi_sound: hdmi-sound {
148 compatible = "simple-audio-card";
149 simple-audio-card,name = "HDMI";
150 simple-audio-card,format = "i2s";
151 simple-audio-card,mclk-fs = <256>;
154 simple-audio-card,codec {
155 sound-dai = <&hdmi>;
158 simple-audio-card,cpu {
159 sound-dai = <&i2s0_8ch>;
164 compatible = "arm,cortex-a55-pmu";
169 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
173 compatible = "arm,psci-1.0";
178 compatible = "arm,armv8-timer";
183 arm,no-tick-in-suspend;
187 compatible = "fixed-clock";
188 clock-frequency = <24000000>;
189 clock-output-names = "xin24m";
190 #clock-cells = <0>;
194 compatible = "fixed-clock";
195 clock-frequency = <32768>;
196 clock-output-names = "xin32k";
197 pinctrl-0 = <&clk32k_out0>;
198 pinctrl-names = "default";
199 #clock-cells = <0>;
203 compatible = "mmio-sram";
205 #address-cells = <1>;
206 #size-cells = <1>;
210 compatible = "arm,scmi-shmem";
216 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
220 clock-names = "sata", "pmalive", "rxoob";
223 phy-names = "sata-phy";
224 ports-implemented = <0x1>;
225 power-domains = <&power RK3568_PD_PIPE>;
230 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
234 clock-names = "sata", "pmalive", "rxoob";
237 phy-names = "sata-phy";
238 ports-implemented = <0x1>;
239 power-domains = <&power RK3568_PD_PIPE>;
244 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
249 clock-names = "ref_clk", "suspend_clk",
253 power-domains = <&power RK3568_PD_PIPE>;
260 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
265 clock-names = "ref_clk", "suspend_clk",
269 phy-names = "usb2-phy", "usb3-phy";
271 power-domains = <&power RK3568_PD_PIPE>;
277 gic: interrupt-controller@fd400000 {
278 compatible = "arm,gic-v3";
282 interrupt-controller;
283 #interrupt-cells = <3>;
284 mbi-alias = <0x0 0xfd410000>;
285 mbi-ranges = <296 24>;
286 msi-controller;
290 compatible = "generic-ehci";
296 phy-names = "usb";
301 compatible = "generic-ohci";
307 phy-names = "usb";
312 compatible = "generic-ehci";
318 phy-names = "usb";
323 compatible = "generic-ohci";
329 phy-names = "usb";
334 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
337 pmu_io_domains: io-domains {
338 compatible = "rockchip,rk3568-pmu-io-voltage-domain";
348 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
353 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
358 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
363 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
368 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
372 pmucru: clock-controller@fdd00000 {
373 compatible = "rockchip,rk3568-pmucru";
375 #clock-cells = <1>;
376 #reset-cells = <1>;
379 cru: clock-controller@fdd20000 {
380 compatible = "rockchip,rk3568-cru";
383 clock-names = "xin24m";
384 #clock-cells = <1>;
385 #reset-cells = <1>;
386 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
387 assigned-clock-rates = <32768>, <1200000000>, <200000000>;
388 assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
393 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
397 clock-names = "i2c", "pclk";
398 pinctrl-0 = <&i2c0_xfer>;
399 pinctrl-names = "default";
400 #address-cells = <1>;
401 #size-cells = <0>;
406 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
410 clock-names = "baudclk", "apb_pclk";
412 pinctrl-0 = <&uart0_xfer>;
413 pinctrl-names = "default";
414 reg-io-width = <4>;
415 reg-shift = <2>;
420 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
423 clock-names = "pwm", "pclk";
424 pinctrl-0 = <&pwm0m0_pins>;
425 pinctrl-names = "default";
426 #pwm-cells = <3>;
431 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
434 clock-names = "pwm", "pclk";
435 pinctrl-0 = <&pwm1m0_pins>;
436 pinctrl-names = "default";
437 #pwm-cells = <3>;
442 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
445 clock-names = "pwm", "pclk";
446 pinctrl-0 = <&pwm2m0_pins>;
447 pinctrl-names = "default";
448 #pwm-cells = <3>;
453 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
456 clock-names = "pwm", "pclk";
457 pinctrl-0 = <&pwm3_pins>;
458 pinctrl-names = "default";
459 #pwm-cells = <3>;
463 pmu: power-management@fdd90000 {
464 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
467 power: power-controller {
468 compatible = "rockchip,rk3568-power-controller";
469 #power-domain-cells = <1>;
470 #address-cells = <1>;
471 #size-cells = <0>;
474 power-domain@RK3568_PD_GPU {
479 #power-domain-cells = <0>;
483 power-domain@RK3568_PD_VI {
490 #power-domain-cells = <0>;
493 power-domain@RK3568_PD_VO {
501 #power-domain-cells = <0>;
504 power-domain@RK3568_PD_RGA {
514 #power-domain-cells = <0>;
517 power-domain@RK3568_PD_VPU {
521 #power-domain-cells = <0>;
524 power-domain@RK3568_PD_RKVDEC {
528 #power-domain-cells = <0>;
531 power-domain@RK3568_PD_RKVENC {
537 #power-domain-cells = <0>;
543 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
548 interrupt-names = "job", "mmu", "gpu";
550 clock-names = "gpu", "bus";
551 #cooling-cells = <2>;
552 power-domains = <&power RK3568_PD_GPU>;
556 vpu: video-codec@fdea0400 {
557 compatible = "rockchip,rk3568-vpu";
560 interrupt-names = "vdpu";
562 clock-names = "aclk", "hclk";
564 power-domains = <&power RK3568_PD_VPU>;
568 compatible = "rockchip,rk3568-iommu";
571 clock-names = "aclk", "iface";
573 power-domains = <&power RK3568_PD_VPU>;
574 #iommu-cells = <0>;
578 compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga";
582 clock-names = "aclk", "hclk", "sclk";
584 reset-names = "core", "axi", "ahb";
585 power-domains = <&power RK3568_PD_RGA>;
588 vepu: video-codec@fdee0000 {
589 compatible = "rockchip,rk3568-vepu";
593 clock-names = "aclk", "hclk";
595 power-domains = <&power RK3568_PD_RGA>;
599 compatible = "rockchip,rk3568-iommu";
603 clock-names = "aclk", "iface";
604 power-domains = <&power RK3568_PD_RGA>;
605 #iommu-cells = <0>;
609 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
614 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
615 fifo-depth = <0x100>;
616 max-frequency = <150000000>;
618 reset-names = "reset";
623 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
627 interrupt-names = "macirq", "eth_wake_irq";
632 clock-names = "stmmaceth", "mac_clk_rx",
637 reset-names = "stmmaceth";
639 snps,axi-config = <&gmac1_stmmac_axi_setup>;
640 snps,mixed-burst;
641 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
642 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
647 compatible = "snps,dwmac-mdio";
648 #address-cells = <0x1>;
649 #size-cells = <0x0>;
652 gmac1_stmmac_axi_setup: stmmac-axi-config {
658 gmac1_mtl_rx_setup: rx-queues-config {
659 snps,rx-queues-to-use = <1>;
663 gmac1_mtl_tx_setup: tx-queues-config {
664 snps,tx-queues-to-use = <1>;
671 reg-names = "vop", "gamma-lut";
675 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
677 power-domains = <&power RK3568_PD_VO>;
682 #address-cells = <1>;
683 #size-cells = <0>;
687 #address-cells = <1>;
688 #size-cells = <0>;
693 #address-cells = <1>;
694 #size-cells = <0>;
699 #address-cells = <1>;
700 #size-cells = <0>;
706 compatible = "rockchip,rk3568-iommu";
710 clock-names = "aclk", "iface";
711 #iommu-cells = <0>;
712 power-domains = <&power RK3568_PD_VO>;
717 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
720 clock-names = "pclk";
722 phy-names = "dphy";
724 power-domains = <&power RK3568_PD_VO>;
725 reset-names = "apb";
731 #address-cells = <1>;
732 #size-cells = <0>;
745 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
748 clock-names = "pclk";
750 phy-names = "dphy";
752 power-domains = <&power RK3568_PD_VO>;
753 reset-names = "apb";
759 #address-cells = <1>;
760 #size-cells = <0>;
773 compatible = "rockchip,rk3568-dw-hdmi";
781 clock-names = "iahb", "isfr", "cec", "ref";
782 pinctrl-names = "default";
783 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
784 power-domains = <&power RK3568_PD_VO>;
785 reg-io-width = <4>;
787 #sound-dai-cells = <0>;
791 #address-cells = <1>;
792 #size-cells = <0>;
805 compatible = "rockchip,rk3568-qos", "syscon";
810 compatible = "rockchip,rk3568-qos", "syscon";
815 compatible = "rockchip,rk3568-qos", "syscon";
820 compatible = "rockchip,rk3568-qos", "syscon";
825 compatible = "rockchip,rk3568-qos", "syscon";
830 compatible = "rockchip,rk3568-qos", "syscon";
835 compatible = "rockchip,rk3568-qos", "syscon";
840 compatible = "rockchip,rk3568-qos", "syscon";
845 compatible = "rockchip,rk3568-qos", "syscon";
850 compatible = "rockchip,rk3568-qos", "syscon";
855 compatible = "rockchip,rk3568-qos", "syscon";
860 compatible = "rockchip,rk3568-qos", "syscon";
865 compatible = "rockchip,rk3568-qos", "syscon";
870 compatible = "rockchip,rk3568-qos", "syscon";
875 compatible = "rockchip,rk3568-qos", "syscon";
880 compatible = "rockchip,rk3568-qos", "syscon";
885 compatible = "rockchip,rk3568-qos", "syscon";
890 compatible = "rockchip,rk3568-qos", "syscon";
895 compatible = "rockchip,rk3568-qos", "syscon";
900 compatible = "rockchip,rk3568-qos", "syscon";
905 compatible = "rockchip,rk3568-qos", "syscon";
910 compatible = "rockchip,rk3568-qos", "syscon";
915 compatible = "rockchip,rk3568-qos", "syscon";
920 compatible = "rockchip,rk3568-qos", "syscon";
925 compatible = "rockchip,rk3568-dfi";
932 compatible = "rockchip,rk3568-pcie";
936 reg-names = "dbi", "apb", "config";
942 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
943 bus-range = <0x0 0xf>;
947 clock-names = "aclk_mst", "aclk_slv",
950 #interrupt-cells = <1>;
951 interrupt-map-mask = <0 0 0 7>;
952 interrupt-map = <0 0 0 1 &pcie_intc 0>,
956 linux,pci-domain = <0>;
957 num-ib-windows = <6>;
958 num-ob-windows = <2>;
959 max-link-speed = <2>;
960 msi-map = <0x0 &gic 0x0 0x1000>;
961 num-lanes = <1>;
963 phy-names = "pcie-phy";
964 power-domains = <&power RK3568_PD_PIPE>;
969 reset-names = "pipe";
970 #address-cells = <3>;
971 #size-cells = <2>;
974 pcie_intc: legacy-interrupt-controller {
975 #address-cells = <0>;
976 #interrupt-cells = <1>;
977 interrupt-controller;
978 interrupt-parent = <&gic>;
984 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
989 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
990 fifo-depth = <0x100>;
991 max-frequency = <150000000>;
993 reset-names = "reset";
998 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1003 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1004 fifo-depth = <0x100>;
1005 max-frequency = <150000000>;
1007 reset-names = "reset";
1016 clock-names = "clk_sfc", "hclk_sfc";
1017 pinctrl-0 = <&fspi_pins>;
1018 pinctrl-names = "default";
1023 compatible = "rockchip,rk3568-dwcmshc";
1026 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
1027 assigned-clock-rates = <200000000>, <24000000>;
1031 clock-names = "core", "bus", "axi", "block", "timer";
1036 compatible = "rockchip,rk3568-rng";
1039 clock-names = "core", "ahb";
1045 compatible = "rockchip,rk3568-i2s-tdm";
1048 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1049 assigned-clock-rates = <1188000000>, <1188000000>;
1051 clock-names = "mclk_tx", "mclk_rx", "hclk";
1053 dma-names = "tx";
1055 reset-names = "tx-m", "rx-m";
1057 #sound-dai-cells = <0>;
1062 compatible = "rockchip,rk3568-i2s-tdm";
1065 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
1066 assigned-clock-rates = <1188000000>, <1188000000>;
1069 clock-names = "mclk_tx", "mclk_rx", "hclk";
1071 dma-names = "rx", "tx";
1073 reset-names = "tx-m", "rx-m";
1075 pinctrl-names = "default";
1076 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
1082 #sound-dai-cells = <0>;
1087 compatible = "rockchip,rk3568-i2s-tdm";
1090 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1091 assigned-clock-rates = <1188000000>;
1093 clock-names = "mclk_tx", "mclk_rx", "hclk";
1095 dma-names = "tx", "rx";
1097 reset-names = "tx-m";
1099 pinctrl-names = "default";
1100 pinctrl-0 = <&i2s2m0_sclktx
1104 #sound-dai-cells = <0>;
1109 compatible = "rockchip,rk3568-i2s-tdm";
1114 clock-names = "mclk_tx", "mclk_rx", "hclk";
1116 dma-names = "tx", "rx";
1118 reset-names = "tx-m", "rx-m";
1120 #sound-dai-cells = <0>;
1125 compatible = "rockchip,rk3568-pdm";
1129 clock-names = "pdm_clk", "pdm_hclk";
1131 dma-names = "rx";
1132 pinctrl-0 = <&pdmm0_clk
1138 pinctrl-names = "default";
1140 reset-names = "pdm-m";
1141 #sound-dai-cells = <0>;
1146 compatible = "rockchip,rk3568-spdif";
1149 clock-names = "mclk", "hclk";
1152 dma-names = "tx";
1153 pinctrl-names = "default";
1154 pinctrl-0 = <&spdifm0_tx>;
1155 #sound-dai-cells = <0>;
1159 dmac0: dma-controller@fe530000 {
1164 arm,pl330-periph-burst;
1166 clock-names = "apb_pclk";
1167 #dma-cells = <1>;
1170 dmac1: dma-controller@fe550000 {
1175 arm,pl330-periph-burst;
1177 clock-names = "apb_pclk";
1178 #dma-cells = <1>;
1182 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1186 clock-names = "i2c", "pclk";
1187 pinctrl-0 = <&i2c1_xfer>;
1188 pinctrl-names = "default";
1189 #address-cells = <1>;
1190 #size-cells = <0>;
1195 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1199 clock-names = "i2c", "pclk";
1200 pinctrl-0 = <&i2c2m0_xfer>;
1201 pinctrl-names = "default";
1202 #address-cells = <1>;
1203 #size-cells = <0>;
1208 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1212 clock-names = "i2c", "pclk";
1213 pinctrl-0 = <&i2c3m0_xfer>;
1214 pinctrl-names = "default";
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1221 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1225 clock-names = "i2c", "pclk";
1226 pinctrl-0 = <&i2c4m0_xfer>;
1227 pinctrl-names = "default";
1228 #address-cells = <1>;
1229 #size-cells = <0>;
1234 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1238 clock-names = "i2c", "pclk";
1239 pinctrl-0 = <&i2c5m0_xfer>;
1240 pinctrl-names = "default";
1241 #address-cells = <1>;
1242 #size-cells = <0>;
1247 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
1251 clock-names = "tclk", "pclk";
1255 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1259 clock-names = "spiclk", "apb_pclk";
1261 dma-names = "tx", "rx";
1262 pinctrl-names = "default";
1263 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1264 #address-cells = <1>;
1265 #size-cells = <0>;
1270 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1274 clock-names = "spiclk", "apb_pclk";
1276 dma-names = "tx", "rx";
1277 pinctrl-names = "default";
1278 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1279 #address-cells = <1>;
1280 #size-cells = <0>;
1285 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1289 clock-names = "spiclk", "apb_pclk";
1291 dma-names = "tx", "rx";
1292 pinctrl-names = "default";
1293 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1294 #address-cells = <1>;
1295 #size-cells = <0>;
1300 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1304 clock-names = "spiclk", "apb_pclk";
1306 dma-names = "tx", "rx";
1307 pinctrl-names = "default";
1308 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
1309 #address-cells = <1>;
1310 #size-cells = <0>;
1315 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1319 clock-names = "baudclk", "apb_pclk";
1321 pinctrl-0 = <&uart1m0_xfer>;
1322 pinctrl-names = "default";
1323 reg-io-width = <4>;
1324 reg-shift = <2>;
1329 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1333 clock-names = "baudclk", "apb_pclk";
1335 pinctrl-0 = <&uart2m0_xfer>;
1336 pinctrl-names = "default";
1337 reg-io-width = <4>;
1338 reg-shift = <2>;
1343 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1347 clock-names = "baudclk", "apb_pclk";
1349 pinctrl-0 = <&uart3m0_xfer>;
1350 pinctrl-names = "default";
1351 reg-io-width = <4>;
1352 reg-shift = <2>;
1357 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1361 clock-names = "baudclk", "apb_pclk";
1363 pinctrl-0 = <&uart4m0_xfer>;
1364 pinctrl-names = "default";
1365 reg-io-width = <4>;
1366 reg-shift = <2>;
1371 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1375 clock-names = "baudclk", "apb_pclk";
1377 pinctrl-0 = <&uart5m0_xfer>;
1378 pinctrl-names = "default";
1379 reg-io-width = <4>;
1380 reg-shift = <2>;
1385 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1389 clock-names = "baudclk", "apb_pclk";
1391 pinctrl-0 = <&uart6m0_xfer>;
1392 pinctrl-names = "default";
1393 reg-io-width = <4>;
1394 reg-shift = <2>;
1399 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1403 clock-names = "baudclk", "apb_pclk";
1405 pinctrl-0 = <&uart7m0_xfer>;
1406 pinctrl-names = "default";
1407 reg-io-width = <4>;
1408 reg-shift = <2>;
1413 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1417 clock-names = "baudclk", "apb_pclk";
1419 pinctrl-0 = <&uart8m0_xfer>;
1420 pinctrl-names = "default";
1421 reg-io-width = <4>;
1422 reg-shift = <2>;
1427 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1431 clock-names = "baudclk", "apb_pclk";
1433 pinctrl-0 = <&uart9m0_xfer>;
1434 pinctrl-names = "default";
1435 reg-io-width = <4>;
1436 reg-shift = <2>;
1440 thermal_zones: thermal-zones {
1441 cpu_thermal: cpu-thermal {
1442 polling-delay-passive = <100>;
1443 polling-delay = <1000>;
1445 thermal-sensors = <&tsadc 0>;
1465 cooling-maps {
1468 cooling-device =
1477 gpu_thermal: gpu-thermal {
1478 polling-delay-passive = <20>; /* milliseconds */
1479 polling-delay = <1000>; /* milliseconds */
1481 thermal-sensors = <&tsadc 1>;
1484 gpu_threshold: gpu-threshold {
1489 gpu_target: gpu-target {
1494 gpu_crit: gpu-crit {
1501 cooling-maps {
1504 cooling-device =
1511 tsadc: tsadc@fe710000 { label
1512 compatible = "rockchip,rk3568-tsadc";
1515 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
1516 assigned-clock-rates = <17000000>, <700000>;
1518 clock-names = "tsadc", "apb_pclk";
1522 rockchip,hw-tshut-temp = <95000>;
1523 pinctrl-names = "default", "sleep";
1524 pinctrl-0 = <&tsadc_shutorg>;
1525 pinctrl-1 = <&tsadc_pin>;
1526 #thermal-sensor-cells = <1>;
1531 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
1535 clock-names = "saradc", "apb_pclk";
1537 reset-names = "saradc-apb";
1538 #io-channel-cells = <1>;
1543 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1546 clock-names = "pwm", "pclk";
1547 pinctrl-0 = <&pwm4_pins>;
1548 pinctrl-names = "default";
1549 #pwm-cells = <3>;
1554 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1557 clock-names = "pwm", "pclk";
1558 pinctrl-0 = <&pwm5_pins>;
1559 pinctrl-names = "default";
1560 #pwm-cells = <3>;
1565 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1568 clock-names = "pwm", "pclk";
1569 pinctrl-0 = <&pwm6_pins>;
1570 pinctrl-names = "default";
1571 #pwm-cells = <3>;
1576 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1579 clock-names = "pwm", "pclk";
1580 pinctrl-0 = <&pwm7_pins>;
1581 pinctrl-names = "default";
1582 #pwm-cells = <3>;
1587 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1590 clock-names = "pwm", "pclk";
1591 pinctrl-0 = <&pwm8m0_pins>;
1592 pinctrl-names = "default";
1593 #pwm-cells = <3>;
1598 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1601 clock-names = "pwm", "pclk";
1602 pinctrl-0 = <&pwm9m0_pins>;
1603 pinctrl-names = "default";
1604 #pwm-cells = <3>;
1609 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1612 clock-names = "pwm", "pclk";
1613 pinctrl-0 = <&pwm10m0_pins>;
1614 pinctrl-names = "default";
1615 #pwm-cells = <3>;
1620 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1623 clock-names = "pwm", "pclk";
1624 pinctrl-0 = <&pwm11m0_pins>;
1625 pinctrl-names = "default";
1626 #pwm-cells = <3>;
1631 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1634 clock-names = "pwm", "pclk";
1635 pinctrl-0 = <&pwm12m0_pins>;
1636 pinctrl-names = "default";
1637 #pwm-cells = <3>;
1642 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1645 clock-names = "pwm", "pclk";
1646 pinctrl-0 = <&pwm13m0_pins>;
1647 pinctrl-names = "default";
1648 #pwm-cells = <3>;
1653 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1656 clock-names = "pwm", "pclk";
1657 pinctrl-0 = <&pwm14m0_pins>;
1658 pinctrl-names = "default";
1659 #pwm-cells = <3>;
1664 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1667 clock-names = "pwm", "pclk";
1668 pinctrl-0 = <&pwm15m0_pins>;
1669 pinctrl-names = "default";
1670 #pwm-cells = <3>;
1675 compatible = "rockchip,rk3568-naneng-combphy";
1680 clock-names = "ref", "apb", "pipe";
1681 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
1682 assigned-clock-rates = <100000000>;
1684 reset-names = "phy";
1685 rockchip,pipe-grf = <&pipegrf>;
1686 rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
1687 #phy-cells = <1>;
1692 compatible = "rockchip,rk3568-naneng-combphy";
1697 clock-names = "ref", "apb", "pipe";
1698 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
1699 assigned-clock-rates = <100000000>;
1701 reset-names = "phy";
1702 rockchip,pipe-grf = <&pipegrf>;
1703 rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
1704 #phy-cells = <1>;
1709 compatible = "rockchip,rk3568-csi-dphy";
1712 clock-names = "pclk";
1713 #phy-cells = <0>;
1715 reset-names = "apb";
1720 dsi_dphy0: mipi-dphy@fe850000 {
1721 compatible = "rockchip,rk3568-dsi-dphy";
1723 clock-names = "ref", "pclk";
1725 #phy-cells = <0>;
1726 power-domains = <&power RK3568_PD_VO>;
1727 reset-names = "apb";
1732 dsi_dphy1: mipi-dphy@fe860000 {
1733 compatible = "rockchip,rk3568-dsi-dphy";
1735 clock-names = "ref", "pclk";
1737 #phy-cells = <0>;
1738 power-domains = <&power RK3568_PD_VO>;
1739 reset-names = "apb";
1745 compatible = "rockchip,rk3568-usb2phy";
1748 clock-names = "phyclk";
1749 clock-output-names = "clk_usbphy0_480m";
1752 #clock-cells = <0>;
1755 usb2phy0_host: host-port {
1756 #phy-cells = <0>;
1760 usb2phy0_otg: otg-port {
1761 #phy-cells = <0>;
1767 compatible = "rockchip,rk3568-usb2phy";
1770 clock-names = "phyclk";
1771 clock-output-names = "clk_usbphy1_480m";
1774 #clock-cells = <0>;
1777 usb2phy1_host: host-port {
1778 #phy-cells = <0>;
1782 usb2phy1_otg: otg-port {
1783 #phy-cells = <0>;
1789 compatible = "rockchip,rk3568-pinctrl";
1792 #address-cells = <2>;
1793 #size-cells = <2>;
1797 compatible = "rockchip,gpio-bank";
1801 gpio-controller;
1802 gpio-ranges = <&pinctrl 0 0 32>;
1803 #gpio-cells = <2>;
1804 interrupt-controller;
1805 #interrupt-cells = <2>;
1809 compatible = "rockchip,gpio-bank";
1813 gpio-controller;
1814 gpio-ranges = <&pinctrl 0 32 32>;
1815 #gpio-cells = <2>;
1816 interrupt-controller;
1817 #interrupt-cells = <2>;
1821 compatible = "rockchip,gpio-bank";
1825 gpio-controller;
1826 gpio-ranges = <&pinctrl 0 64 32>;
1827 #gpio-cells = <2>;
1828 interrupt-controller;
1829 #interrupt-cells = <2>;
1833 compatible = "rockchip,gpio-bank";
1837 gpio-controller;
1838 gpio-ranges = <&pinctrl 0 96 32>;
1839 #gpio-cells = <2>;
1840 interrupt-controller;
1841 #interrupt-cells = <2>;
1845 compatible = "rockchip,gpio-bank";
1849 gpio-controller;
1850 gpio-ranges = <&pinctrl 0 128 32>;
1851 #gpio-cells = <2>;
1852 interrupt-controller;
1853 #interrupt-cells = <2>;
1858 #include "rk3568-pinctrl.dtsi"