Lines Matching +full:hw +full:- +full:tshut +full:- +full:temp
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
49 #address-cells = <2>;
50 #size-cells = <0>;
54 compatible = "arm,cortex-a55";
57 #cooling-cells = <2>;
58 enable-method = "psci";
59 i-cache-size = <0x8000>;
60 i-cache-line-size = <64>;
61 i-cache-sets = <128>;
62 d-cache-size = <0x8000>;
63 d-cache-line-size = <64>;
64 d-cache-sets = <128>;
65 next-level-cache = <&l3_cache>;
70 compatible = "arm,cortex-a55";
72 #cooling-cells = <2>;
73 enable-method = "psci";
74 i-cache-size = <0x8000>;
75 i-cache-line-size = <64>;
76 i-cache-sets = <128>;
77 d-cache-size = <0x8000>;
78 d-cache-line-size = <64>;
79 d-cache-sets = <128>;
80 next-level-cache = <&l3_cache>;
85 compatible = "arm,cortex-a55";
87 #cooling-cells = <2>;
88 enable-method = "psci";
89 i-cache-size = <0x8000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <128>;
92 d-cache-size = <0x8000>;
93 d-cache-line-size = <64>;
94 d-cache-sets = <128>;
95 next-level-cache = <&l3_cache>;
100 compatible = "arm,cortex-a55";
102 #cooling-cells = <2>;
103 enable-method = "psci";
104 i-cache-size = <0x8000>;
105 i-cache-line-size = <64>;
106 i-cache-sets = <128>;
107 d-cache-size = <0x8000>;
108 d-cache-line-size = <64>;
109 d-cache-sets = <128>;
110 next-level-cache = <&l3_cache>;
115 * There are no private per-core L2 caches, but only the
118 l3_cache: l3-cache {
120 cache-level = <2>;
121 cache-unified;
122 cache-size = <0x80000>;
123 cache-line-size = <64>;
124 cache-sets = <512>;
127 display_subsystem: display-subsystem {
128 compatible = "rockchip,display-subsystem";
134 compatible = "arm,scmi-smc";
135 arm,smc-id = <0x82000010>;
137 #address-cells = <1>;
138 #size-cells = <0>;
142 #clock-cells = <1>;
147 hdmi_sound: hdmi-sound {
148 compatible = "simple-audio-card";
149 simple-audio-card,name = "HDMI";
150 simple-audio-card,format = "i2s";
151 simple-audio-card,mclk-fs = <256>;
154 simple-audio-card,codec {
155 sound-dai = <&hdmi>;
158 simple-audio-card,cpu {
159 sound-dai = <&i2s0_8ch>;
164 compatible = "arm,cortex-a55-pmu";
169 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
173 compatible = "arm,psci-1.0";
177 reserved-memory {
178 #address-cells = <2>;
179 #size-cells = <2>;
183 compatible = "arm,scmi-shmem";
185 no-map;
190 compatible = "arm,armv8-timer";
195 arm,no-tick-in-suspend;
199 compatible = "fixed-clock";
200 clock-frequency = <24000000>;
201 clock-output-names = "xin24m";
202 #clock-cells = <0>;
206 compatible = "fixed-clock";
207 clock-frequency = <32768>;
208 clock-output-names = "xin32k";
209 pinctrl-0 = <&clk32k_out0>;
210 pinctrl-names = "default";
211 #clock-cells = <0>;
215 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
219 clock-names = "sata", "pmalive", "rxoob";
222 phy-names = "sata-phy";
223 ports-implemented = <0x1>;
224 power-domains = <&power RK3568_PD_PIPE>;
229 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
233 clock-names = "sata", "pmalive", "rxoob";
236 phy-names = "sata-phy";
237 ports-implemented = <0x1>;
238 power-domains = <&power RK3568_PD_PIPE>;
243 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
248 clock-names = "ref_clk", "suspend_clk",
252 power-domains = <&power RK3568_PD_PIPE>;
259 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
264 clock-names = "ref_clk", "suspend_clk",
268 phy-names = "usb2-phy", "usb3-phy";
270 power-domains = <&power RK3568_PD_PIPE>;
276 gic: interrupt-controller@fd400000 {
277 compatible = "arm,gic-v3";
281 interrupt-controller;
282 #interrupt-cells = <3>;
283 mbi-alias = <0x0 0xfd410000>;
284 mbi-ranges = <296 24>;
285 msi-controller;
287 #address-cells = <2>;
288 #size-cells = <2>;
289 dma-noncoherent;
291 its: msi-controller@fd440000 {
292 compatible = "arm,gic-v3-its";
294 dma-noncoherent;
295 msi-controller;
296 #msi-cells = <1>;
301 compatible = "generic-ehci";
307 phy-names = "usb";
312 compatible = "generic-ohci";
318 phy-names = "usb";
323 compatible = "generic-ehci";
329 phy-names = "usb";
334 compatible = "generic-ohci";
340 phy-names = "usb";
345 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
348 pmu_io_domains: io-domains {
349 compatible = "rockchip,rk3568-pmu-io-voltage-domain";
359 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
364 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
369 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
374 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
379 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
383 pmucru: clock-controller@fdd00000 {
384 compatible = "rockchip,rk3568-pmucru";
386 #clock-cells = <1>;
387 #reset-cells = <1>;
390 cru: clock-controller@fdd20000 {
391 compatible = "rockchip,rk3568-cru";
394 clock-names = "xin24m";
395 #clock-cells = <1>;
396 #reset-cells = <1>;
397 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
398 assigned-clock-rates = <32768>, <1200000000>, <200000000>;
399 assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
404 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
408 clock-names = "i2c", "pclk";
409 pinctrl-0 = <&i2c0_xfer>;
410 pinctrl-names = "default";
411 #address-cells = <1>;
412 #size-cells = <0>;
417 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
421 clock-names = "baudclk", "apb_pclk";
423 pinctrl-0 = <&uart0_xfer>;
424 pinctrl-names = "default";
425 reg-io-width = <4>;
426 reg-shift = <2>;
431 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
434 clock-names = "pwm", "pclk";
435 pinctrl-0 = <&pwm0m0_pins>;
436 pinctrl-names = "default";
437 #pwm-cells = <3>;
442 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
445 clock-names = "pwm", "pclk";
446 pinctrl-0 = <&pwm1m0_pins>;
447 pinctrl-names = "default";
448 #pwm-cells = <3>;
453 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
456 clock-names = "pwm", "pclk";
457 pinctrl-0 = <&pwm2m0_pins>;
458 pinctrl-names = "default";
459 #pwm-cells = <3>;
464 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
467 clock-names = "pwm", "pclk";
468 pinctrl-0 = <&pwm3_pins>;
469 pinctrl-names = "default";
470 #pwm-cells = <3>;
474 pmu: power-management@fdd90000 {
475 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
478 power: power-controller {
479 compatible = "rockchip,rk3568-power-controller";
480 #power-domain-cells = <1>;
481 #address-cells = <1>;
482 #size-cells = <0>;
485 power-domain@RK3568_PD_GPU {
490 #power-domain-cells = <0>;
494 power-domain@RK3568_PD_VI {
501 #power-domain-cells = <0>;
504 power-domain@RK3568_PD_VO {
512 #power-domain-cells = <0>;
515 power-domain@RK3568_PD_RGA {
525 #power-domain-cells = <0>;
528 power-domain@RK3568_PD_VPU {
532 #power-domain-cells = <0>;
535 power-domain@RK3568_PD_RKVDEC {
539 #power-domain-cells = <0>;
542 power-domain@RK3568_PD_RKVENC {
548 #power-domain-cells = <0>;
554 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
559 interrupt-names = "job", "mmu", "gpu";
561 clock-names = "gpu", "bus";
562 #cooling-cells = <2>;
563 power-domains = <&power RK3568_PD_GPU>;
567 vpu: video-codec@fdea0400 {
568 compatible = "rockchip,rk3568-vpu";
571 interrupt-names = "vdpu";
573 clock-names = "aclk", "hclk";
575 power-domains = <&power RK3568_PD_VPU>;
579 compatible = "rockchip,rk3568-iommu";
582 clock-names = "aclk", "iface";
584 power-domains = <&power RK3568_PD_VPU>;
585 #iommu-cells = <0>;
589 compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga";
593 clock-names = "aclk", "hclk", "sclk";
595 reset-names = "core", "axi", "ahb";
596 power-domains = <&power RK3568_PD_RGA>;
599 vepu: video-codec@fdee0000 {
600 compatible = "rockchip,rk3568-vepu";
604 clock-names = "aclk", "hclk";
606 power-domains = <&power RK3568_PD_RGA>;
610 compatible = "rockchip,rk3568-iommu";
614 clock-names = "aclk", "iface";
615 power-domains = <&power RK3568_PD_RGA>;
616 #iommu-cells = <0>;
620 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
625 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
626 fifo-depth = <0x100>;
627 max-frequency = <150000000>;
629 reset-names = "reset";
634 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
638 interrupt-names = "macirq", "eth_wake_irq";
643 clock-names = "stmmaceth", "mac_clk_rx",
648 reset-names = "stmmaceth";
650 snps,axi-config = <&gmac1_stmmac_axi_setup>;
651 snps,mixed-burst;
652 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
653 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
658 compatible = "snps,dwmac-mdio";
659 #address-cells = <0x1>;
660 #size-cells = <0x0>;
663 gmac1_stmmac_axi_setup: stmmac-axi-config {
669 gmac1_mtl_rx_setup: rx-queues-config {
670 snps,rx-queues-to-use = <1>;
674 gmac1_mtl_tx_setup: tx-queues-config {
675 snps,tx-queues-to-use = <1>;
682 reg-names = "vop", "gamma-lut";
686 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
688 power-domains = <&power RK3568_PD_VO>;
693 #address-cells = <1>;
694 #size-cells = <0>;
698 #address-cells = <1>;
699 #size-cells = <0>;
704 #address-cells = <1>;
705 #size-cells = <0>;
710 #address-cells = <1>;
711 #size-cells = <0>;
717 compatible = "rockchip,rk3568-iommu";
721 clock-names = "aclk", "iface";
722 #iommu-cells = <0>;
723 power-domains = <&power RK3568_PD_VO>;
728 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
731 clock-names = "pclk";
733 phy-names = "dphy";
735 power-domains = <&power RK3568_PD_VO>;
736 reset-names = "apb";
742 #address-cells = <1>;
743 #size-cells = <0>;
756 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
759 clock-names = "pclk";
761 phy-names = "dphy";
763 power-domains = <&power RK3568_PD_VO>;
764 reset-names = "apb";
770 #address-cells = <1>;
771 #size-cells = <0>;
784 compatible = "rockchip,rk3568-dw-hdmi";
792 clock-names = "iahb", "isfr", "cec", "ref";
793 pinctrl-names = "default";
794 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
795 power-domains = <&power RK3568_PD_VO>;
796 reg-io-width = <4>;
798 #sound-dai-cells = <0>;
802 #address-cells = <1>;
803 #size-cells = <0>;
816 compatible = "rockchip,rk3568-qos", "syscon";
821 compatible = "rockchip,rk3568-qos", "syscon";
826 compatible = "rockchip,rk3568-qos", "syscon";
831 compatible = "rockchip,rk3568-qos", "syscon";
836 compatible = "rockchip,rk3568-qos", "syscon";
841 compatible = "rockchip,rk3568-qos", "syscon";
846 compatible = "rockchip,rk3568-qos", "syscon";
851 compatible = "rockchip,rk3568-qos", "syscon";
856 compatible = "rockchip,rk3568-qos", "syscon";
861 compatible = "rockchip,rk3568-qos", "syscon";
866 compatible = "rockchip,rk3568-qos", "syscon";
871 compatible = "rockchip,rk3568-qos", "syscon";
876 compatible = "rockchip,rk3568-qos", "syscon";
881 compatible = "rockchip,rk3568-qos", "syscon";
886 compatible = "rockchip,rk3568-qos", "syscon";
891 compatible = "rockchip,rk3568-qos", "syscon";
896 compatible = "rockchip,rk3568-qos", "syscon";
901 compatible = "rockchip,rk3568-qos", "syscon";
906 compatible = "rockchip,rk3568-qos", "syscon";
911 compatible = "rockchip,rk3568-qos", "syscon";
916 compatible = "rockchip,rk3568-qos", "syscon";
921 compatible = "rockchip,rk3568-qos", "syscon";
926 compatible = "rockchip,rk3568-qos", "syscon";
931 compatible = "rockchip,rk3568-qos", "syscon";
936 compatible = "rockchip,rk3568-dfi";
943 compatible = "rockchip,rk3568-pcie";
947 reg-names = "dbi", "apb", "config";
953 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
954 bus-range = <0x0 0xf>;
958 clock-names = "aclk_mst", "aclk_slv",
961 #interrupt-cells = <1>;
962 interrupt-map-mask = <0 0 0 7>;
963 interrupt-map = <0 0 0 1 &pcie_intc 0>,
967 linux,pci-domain = <0>;
968 num-ib-windows = <6>;
969 num-ob-windows = <2>;
970 max-link-speed = <2>;
971 msi-map = <0x0 &its 0x0 0x1000>;
972 num-lanes = <1>;
974 phy-names = "pcie-phy";
975 power-domains = <&power RK3568_PD_PIPE>;
980 reset-names = "pipe";
981 #address-cells = <3>;
982 #size-cells = <2>;
985 pcie_intc: legacy-interrupt-controller {
986 #address-cells = <0>;
987 #interrupt-cells = <1>;
988 interrupt-controller;
989 interrupt-parent = <&gic>;
995 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1000 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1001 fifo-depth = <0x100>;
1002 max-frequency = <150000000>;
1004 reset-names = "reset";
1009 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1014 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1015 fifo-depth = <0x100>;
1016 max-frequency = <150000000>;
1018 reset-names = "reset";
1027 clock-names = "clk_sfc", "hclk_sfc";
1028 pinctrl-0 = <&fspi_pins>;
1029 pinctrl-names = "default";
1034 compatible = "rockchip,rk3568-dwcmshc";
1037 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
1038 assigned-clock-rates = <200000000>, <24000000>;
1042 clock-names = "core", "bus", "axi", "block", "timer";
1052 compatible = "rockchip,rk3568-rng";
1055 clock-names = "core", "ahb";
1061 compatible = "rockchip,rk3568-i2s-tdm";
1064 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1065 assigned-clock-rates = <1188000000>, <1188000000>;
1067 clock-names = "mclk_tx", "mclk_rx", "hclk";
1069 dma-names = "tx";
1071 reset-names = "tx-m", "rx-m";
1073 #sound-dai-cells = <0>;
1078 compatible = "rockchip,rk3568-i2s-tdm";
1081 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
1082 assigned-clock-rates = <1188000000>, <1188000000>;
1085 clock-names = "mclk_tx", "mclk_rx", "hclk";
1087 dma-names = "rx", "tx";
1089 reset-names = "tx-m", "rx-m";
1091 pinctrl-names = "default";
1092 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
1098 #sound-dai-cells = <0>;
1103 compatible = "rockchip,rk3568-i2s-tdm";
1106 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1107 assigned-clock-rates = <1188000000>;
1109 clock-names = "mclk_tx", "mclk_rx", "hclk";
1111 dma-names = "tx", "rx";
1113 reset-names = "tx-m";
1115 pinctrl-names = "default";
1116 pinctrl-0 = <&i2s2m0_sclktx
1120 #sound-dai-cells = <0>;
1125 compatible = "rockchip,rk3568-i2s-tdm";
1130 clock-names = "mclk_tx", "mclk_rx", "hclk";
1132 dma-names = "tx", "rx";
1134 reset-names = "tx-m", "rx-m";
1136 #sound-dai-cells = <0>;
1141 compatible = "rockchip,rk3568-pdm";
1145 clock-names = "pdm_clk", "pdm_hclk";
1147 dma-names = "rx";
1148 pinctrl-0 = <&pdmm0_clk
1154 pinctrl-names = "default";
1156 reset-names = "pdm-m";
1157 #sound-dai-cells = <0>;
1162 compatible = "rockchip,rk3568-spdif";
1165 clock-names = "mclk", "hclk";
1168 dma-names = "tx";
1169 pinctrl-names = "default";
1170 pinctrl-0 = <&spdifm0_tx>;
1171 #sound-dai-cells = <0>;
1175 dmac0: dma-controller@fe530000 {
1180 arm,pl330-periph-burst;
1182 clock-names = "apb_pclk";
1183 #dma-cells = <1>;
1186 dmac1: dma-controller@fe550000 {
1191 arm,pl330-periph-burst;
1193 clock-names = "apb_pclk";
1194 #dma-cells = <1>;
1198 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1202 clock-names = "i2c", "pclk";
1203 pinctrl-0 = <&i2c1_xfer>;
1204 pinctrl-names = "default";
1205 #address-cells = <1>;
1206 #size-cells = <0>;
1211 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1215 clock-names = "i2c", "pclk";
1216 pinctrl-0 = <&i2c2m0_xfer>;
1217 pinctrl-names = "default";
1218 #address-cells = <1>;
1219 #size-cells = <0>;
1224 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1228 clock-names = "i2c", "pclk";
1229 pinctrl-0 = <&i2c3m0_xfer>;
1230 pinctrl-names = "default";
1231 #address-cells = <1>;
1232 #size-cells = <0>;
1237 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1241 clock-names = "i2c", "pclk";
1242 pinctrl-0 = <&i2c4m0_xfer>;
1243 pinctrl-names = "default";
1244 #address-cells = <1>;
1245 #size-cells = <0>;
1250 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1254 clock-names = "i2c", "pclk";
1255 pinctrl-0 = <&i2c5m0_xfer>;
1256 pinctrl-names = "default";
1257 #address-cells = <1>;
1258 #size-cells = <0>;
1263 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
1267 clock-names = "tclk", "pclk";
1271 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1275 clock-names = "spiclk", "apb_pclk";
1277 dma-names = "tx", "rx";
1278 pinctrl-names = "default";
1279 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1280 #address-cells = <1>;
1281 #size-cells = <0>;
1286 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1290 clock-names = "spiclk", "apb_pclk";
1292 dma-names = "tx", "rx";
1293 pinctrl-names = "default";
1294 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1295 #address-cells = <1>;
1296 #size-cells = <0>;
1301 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1305 clock-names = "spiclk", "apb_pclk";
1307 dma-names = "tx", "rx";
1308 pinctrl-names = "default";
1309 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1310 #address-cells = <1>;
1311 #size-cells = <0>;
1316 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1320 clock-names = "spiclk", "apb_pclk";
1322 dma-names = "tx", "rx";
1323 pinctrl-names = "default";
1324 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
1325 #address-cells = <1>;
1326 #size-cells = <0>;
1331 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1335 clock-names = "baudclk", "apb_pclk";
1337 pinctrl-0 = <&uart1m0_xfer>;
1338 pinctrl-names = "default";
1339 reg-io-width = <4>;
1340 reg-shift = <2>;
1345 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1349 clock-names = "baudclk", "apb_pclk";
1351 pinctrl-0 = <&uart2m0_xfer>;
1352 pinctrl-names = "default";
1353 reg-io-width = <4>;
1354 reg-shift = <2>;
1359 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1363 clock-names = "baudclk", "apb_pclk";
1365 pinctrl-0 = <&uart3m0_xfer>;
1366 pinctrl-names = "default";
1367 reg-io-width = <4>;
1368 reg-shift = <2>;
1373 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1377 clock-names = "baudclk", "apb_pclk";
1379 pinctrl-0 = <&uart4m0_xfer>;
1380 pinctrl-names = "default";
1381 reg-io-width = <4>;
1382 reg-shift = <2>;
1387 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1391 clock-names = "baudclk", "apb_pclk";
1393 pinctrl-0 = <&uart5m0_xfer>;
1394 pinctrl-names = "default";
1395 reg-io-width = <4>;
1396 reg-shift = <2>;
1401 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1405 clock-names = "baudclk", "apb_pclk";
1407 pinctrl-0 = <&uart6m0_xfer>;
1408 pinctrl-names = "default";
1409 reg-io-width = <4>;
1410 reg-shift = <2>;
1415 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1419 clock-names = "baudclk", "apb_pclk";
1421 pinctrl-0 = <&uart7m0_xfer>;
1422 pinctrl-names = "default";
1423 reg-io-width = <4>;
1424 reg-shift = <2>;
1429 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1433 clock-names = "baudclk", "apb_pclk";
1435 pinctrl-0 = <&uart8m0_xfer>;
1436 pinctrl-names = "default";
1437 reg-io-width = <4>;
1438 reg-shift = <2>;
1443 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1447 clock-names = "baudclk", "apb_pclk";
1449 pinctrl-0 = <&uart9m0_xfer>;
1450 pinctrl-names = "default";
1451 reg-io-width = <4>;
1452 reg-shift = <2>;
1456 thermal_zones: thermal-zones {
1457 cpu_thermal: cpu-thermal {
1458 polling-delay-passive = <100>;
1459 polling-delay = <1000>;
1461 thermal-sensors = <&tsadc 0>;
1481 cooling-maps {
1484 cooling-device =
1493 gpu_thermal: gpu-thermal {
1494 polling-delay-passive = <20>; /* milliseconds */
1495 polling-delay = <1000>; /* milliseconds */
1497 thermal-sensors = <&tsadc 1>;
1500 gpu_threshold: gpu-threshold {
1505 gpu_target: gpu-target {
1510 gpu_crit: gpu-crit {
1517 cooling-maps {
1520 cooling-device =
1528 compatible = "rockchip,rk3568-tsadc";
1531 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
1532 assigned-clock-rates = <17000000>, <700000>;
1534 clock-names = "tsadc", "apb_pclk";
1538 rockchip,hw-tshut-temp = <95000>;
1539 pinctrl-names = "default", "sleep";
1540 pinctrl-0 = <&tsadc_shutorg>;
1541 pinctrl-1 = <&tsadc_pin>;
1542 #thermal-sensor-cells = <1>;
1547 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
1551 clock-names = "saradc", "apb_pclk";
1553 reset-names = "saradc-apb";
1554 #io-channel-cells = <1>;
1559 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1562 clock-names = "pwm", "pclk";
1563 pinctrl-0 = <&pwm4_pins>;
1564 pinctrl-names = "default";
1565 #pwm-cells = <3>;
1570 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1573 clock-names = "pwm", "pclk";
1574 pinctrl-0 = <&pwm5_pins>;
1575 pinctrl-names = "default";
1576 #pwm-cells = <3>;
1581 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1584 clock-names = "pwm", "pclk";
1585 pinctrl-0 = <&pwm6_pins>;
1586 pinctrl-names = "default";
1587 #pwm-cells = <3>;
1592 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1595 clock-names = "pwm", "pclk";
1596 pinctrl-0 = <&pwm7_pins>;
1597 pinctrl-names = "default";
1598 #pwm-cells = <3>;
1603 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1606 clock-names = "pwm", "pclk";
1607 pinctrl-0 = <&pwm8m0_pins>;
1608 pinctrl-names = "default";
1609 #pwm-cells = <3>;
1614 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1617 clock-names = "pwm", "pclk";
1618 pinctrl-0 = <&pwm9m0_pins>;
1619 pinctrl-names = "default";
1620 #pwm-cells = <3>;
1625 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1628 clock-names = "pwm", "pclk";
1629 pinctrl-0 = <&pwm10m0_pins>;
1630 pinctrl-names = "default";
1631 #pwm-cells = <3>;
1636 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1639 clock-names = "pwm", "pclk";
1640 pinctrl-0 = <&pwm11m0_pins>;
1641 pinctrl-names = "default";
1642 #pwm-cells = <3>;
1647 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1650 clock-names = "pwm", "pclk";
1651 pinctrl-0 = <&pwm12m0_pins>;
1652 pinctrl-names = "default";
1653 #pwm-cells = <3>;
1658 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1661 clock-names = "pwm", "pclk";
1662 pinctrl-0 = <&pwm13m0_pins>;
1663 pinctrl-names = "default";
1664 #pwm-cells = <3>;
1669 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1672 clock-names = "pwm", "pclk";
1673 pinctrl-0 = <&pwm14m0_pins>;
1674 pinctrl-names = "default";
1675 #pwm-cells = <3>;
1680 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1683 clock-names = "pwm", "pclk";
1684 pinctrl-0 = <&pwm15m0_pins>;
1685 pinctrl-names = "default";
1686 #pwm-cells = <3>;
1691 compatible = "rockchip,rk3568-naneng-combphy";
1696 clock-names = "ref", "apb", "pipe";
1697 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
1698 assigned-clock-rates = <100000000>;
1700 reset-names = "phy";
1701 rockchip,pipe-grf = <&pipegrf>;
1702 rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
1703 #phy-cells = <1>;
1708 compatible = "rockchip,rk3568-naneng-combphy";
1713 clock-names = "ref", "apb", "pipe";
1714 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
1715 assigned-clock-rates = <100000000>;
1717 reset-names = "phy";
1718 rockchip,pipe-grf = <&pipegrf>;
1719 rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
1720 #phy-cells = <1>;
1725 compatible = "rockchip,rk3568-csi-dphy";
1728 clock-names = "pclk";
1729 #phy-cells = <0>;
1731 reset-names = "apb";
1736 dsi_dphy0: mipi-dphy@fe850000 {
1737 compatible = "rockchip,rk3568-dsi-dphy";
1739 clock-names = "ref", "pclk";
1741 #phy-cells = <0>;
1742 power-domains = <&power RK3568_PD_VO>;
1743 reset-names = "apb";
1748 dsi_dphy1: mipi-dphy@fe860000 {
1749 compatible = "rockchip,rk3568-dsi-dphy";
1751 clock-names = "ref", "pclk";
1753 #phy-cells = <0>;
1754 power-domains = <&power RK3568_PD_VO>;
1755 reset-names = "apb";
1761 compatible = "rockchip,rk3568-usb2phy";
1764 clock-names = "phyclk";
1765 clock-output-names = "clk_usbphy0_480m";
1768 #clock-cells = <0>;
1771 usb2phy0_host: host-port {
1772 #phy-cells = <0>;
1776 usb2phy0_otg: otg-port {
1777 #phy-cells = <0>;
1783 compatible = "rockchip,rk3568-usb2phy";
1786 clock-names = "phyclk";
1787 clock-output-names = "clk_usbphy1_480m";
1790 #clock-cells = <0>;
1793 usb2phy1_host: host-port {
1794 #phy-cells = <0>;
1798 usb2phy1_otg: otg-port {
1799 #phy-cells = <0>;
1805 compatible = "rockchip,rk3568-pinctrl";
1808 #address-cells = <2>;
1809 #size-cells = <2>;
1813 compatible = "rockchip,gpio-bank";
1817 gpio-controller;
1818 gpio-ranges = <&pinctrl 0 0 32>;
1819 #gpio-cells = <2>;
1820 interrupt-controller;
1821 #interrupt-cells = <2>;
1825 compatible = "rockchip,gpio-bank";
1829 gpio-controller;
1830 gpio-ranges = <&pinctrl 0 32 32>;
1831 #gpio-cells = <2>;
1832 interrupt-controller;
1833 #interrupt-cells = <2>;
1837 compatible = "rockchip,gpio-bank";
1841 gpio-controller;
1842 gpio-ranges = <&pinctrl 0 64 32>;
1843 #gpio-cells = <2>;
1844 interrupt-controller;
1845 #interrupt-cells = <2>;
1849 compatible = "rockchip,gpio-bank";
1853 gpio-controller;
1854 gpio-ranges = <&pinctrl 0 96 32>;
1855 #gpio-cells = <2>;
1856 interrupt-controller;
1857 #interrupt-cells = <2>;
1861 compatible = "rockchip,gpio-bank";
1865 gpio-controller;
1866 gpio-ranges = <&pinctrl 0 128 32>;
1867 #gpio-cells = <2>;
1868 interrupt-controller;
1869 #interrupt-cells = <2>;
1874 #include "rk3568-pinctrl.dtsi"