Lines Matching full:cru
6 #include <dt-bindings/clock/rk3568-cru.h>
217 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
218 <&cru CLK_SATA1_RXOOB>;
231 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
232 <&cru CLK_SATA2_RXOOB>;
246 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
247 <&cru ACLK_USB3OTG0>;
253 resets = <&cru SRST_USB3OTG0>;
262 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
263 <&cru ACLK_USB3OTG1>;
271 resets = <&cru SRST_USB3OTG1>;
304 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
305 <&cru PCLK_USB>;
315 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
316 <&cru PCLK_USB>;
326 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
327 <&cru PCLK_USB>;
337 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
338 <&cru PCLK_USB>;
390 cru: clock-controller@fdd20000 { label
391 compatible = "rockchip,rk3568-cru";
397 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
487 clocks = <&cru ACLK_GPU_PRE>,
488 <&cru PCLK_GPU_PRE>;
496 clocks = <&cru HCLK_VI>,
497 <&cru PCLK_VI>;
506 clocks = <&cru HCLK_VO>,
507 <&cru PCLK_VO>,
508 <&cru ACLK_VOP_PRE>;
517 clocks = <&cru HCLK_RGA_PRE>,
518 <&cru PCLK_RGA_PRE>;
530 clocks = <&cru HCLK_VPU_PRE>;
536 clocks = <&cru HCLK_RKVDEC_PRE>;
544 clocks = <&cru HCLK_RKVENC_PRE>;
560 clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
572 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
583 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
592 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>;
594 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
603 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
613 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
623 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
624 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
628 resets = <&cru SRST_SDMMC2>;
639 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
640 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
641 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
642 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
647 resets = <&cru SRST_A_GMAC1>;
684 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>,
685 <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
720 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
732 clocks = <&cru PCLK_DSITX_0>;
737 resets = <&cru SRST_P_DSITX_0>;
760 clocks = <&cru PCLK_DSITX_1>;
765 resets = <&cru SRST_P_DSITX_1>;
787 clocks = <&cru PCLK_HDMI_HOST>,
788 <&cru CLK_HDMI_SFR>,
789 <&cru CLK_HDMI_CEC>,
791 <&cru HCLK_VO>;
955 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
956 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
957 <&cru CLK_PCIE20_AUX_NDFT>;
979 resets = <&cru SRST_PCIE20_POWERUP>;
998 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
999 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
1003 resets = <&cru SRST_SDMMC0>;
1012 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
1013 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
1017 resets = <&cru SRST_SDMMC1>;
1026 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1037 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
1039 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1040 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1041 <&cru TCLK_EMMC>;
1054 clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
1056 resets = <&cru SRST_TRNG_NS>;
1064 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1066 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1070 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1081 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
1083 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>,
1084 <&cru HCLK_I2S1_8CH>;
1088 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1106 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1108 clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
1112 resets = <&cru SRST_M_I2S2_2CH>;
1128 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>,
1129 <&cru HCLK_I2S3_2CH>;
1133 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>;
1144 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
1155 resets = <&cru SRST_M_PDM>;
1166 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
1181 clocks = <&cru ACLK_BUS>;
1192 clocks = <&cru ACLK_BUS>;
1201 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1214 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1227 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1240 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1253 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1266 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
1274 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1289 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1304 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1319 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
1334 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1348 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1362 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1376 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1390 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1404 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1418 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1432 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1446 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1531 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
1533 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
1535 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>,
1536 <&cru SRST_TSADCPHY>;
1550 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
1552 resets = <&cru SRST_P_SARADC>;
1561 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1572 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1583 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1594 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1605 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1616 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1627 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1638 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1649 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1660 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1671 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1682 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1694 <&cru PCLK_PIPEPHY1>,
1695 <&cru PCLK_PIPE>;
1699 resets = <&cru SRST_PIPEPHY1>;
1711 <&cru PCLK_PIPEPHY2>,
1712 <&cru PCLK_PIPE>;
1716 resets = <&cru SRST_PIPEPHY2>;
1727 clocks = <&cru PCLK_MIPICSIPHY>;
1730 resets = <&cru SRST_P_MIPICSIPHY>;
1740 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>;
1744 resets = <&cru SRST_P_MIPIDSIPHY0>;
1752 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
1756 resets = <&cru SRST_P_MIPIDSIPHY1>;
1828 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
1840 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
1852 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
1864 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;