Lines Matching +full:0 +full:xfd400000
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&scmi_clk 0>;
59 i-cache-size = <0x8000>;
62 d-cache-size = <0x8000>;
71 reg = <0x0 0x100>;
74 i-cache-size = <0x8000>;
77 d-cache-size = <0x8000>;
86 reg = <0x0 0x200>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
101 reg = <0x0 0x300>;
104 i-cache-size = <0x8000>;
107 d-cache-size = <0x8000>;
122 cache-size = <0x80000>;
135 arm,smc-id = <0x82000010>;
138 #size-cells = <0>;
141 reg = <0x14>;
190 #clock-cells = <0>;
197 pinctrl-0 = <&clk32k_out0>;
199 #clock-cells = <0>;
204 reg = <0x0 0x0010f000 0x0 0x100>;
207 ranges = <0 0x0 0x0010f000 0x100>;
209 scmi_shmem: sram@0 {
211 reg = <0x0 0x100>;
217 reg = <0 0xfc400000 0 0x1000>;
224 ports-implemented = <0x1>;
231 reg = <0 0xfc800000 0 0x1000>;
238 ports-implemented = <0x1>;
245 reg = <0x0 0xfcc00000 0x0 0x400000>;
261 reg = <0x0 0xfd000000 0x0 0x400000>;
279 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
280 <0x0 0xfd460000 0 0x80000>; /* GICR */
284 mbi-alias = <0x0 0xfd410000>;
291 reg = <0x0 0xfd800000 0x0 0x40000>;
302 reg = <0x0 0xfd840000 0x0 0x40000>;
313 reg = <0x0 0xfd880000 0x0 0x40000>;
324 reg = <0x0 0xfd8c0000 0x0 0x40000>;
335 reg = <0x0 0xfdc20000 0x0 0x10000>;
344 reg = <0x0 0xfdc50000 0x0 0x1000>;
349 reg = <0x0 0xfdc60000 0x0 0x10000>;
354 reg = <0x0 0xfdc80000 0x0 0x1000>;
359 reg = <0x0 0xfdc90000 0x0 0x1000>;
364 reg = <0x0 0xfdca0000 0x0 0x8000>;
369 reg = <0x0 0xfdca8000 0x0 0x8000>;
374 reg = <0x0 0xfdd00000 0x0 0x1000>;
381 reg = <0x0 0xfdd20000 0x0 0x1000>;
394 reg = <0x0 0xfdd40000 0x0 0x1000>;
398 pinctrl-0 = <&i2c0_xfer>;
401 #size-cells = <0>;
407 reg = <0x0 0xfdd50000 0x0 0x100>;
411 dmas = <&dmac0 0>, <&dmac0 1>;
412 pinctrl-0 = <&uart0_xfer>;
421 reg = <0x0 0xfdd70000 0x0 0x10>;
424 pinctrl-0 = <&pwm0m0_pins>;
432 reg = <0x0 0xfdd70010 0x0 0x10>;
435 pinctrl-0 = <&pwm1m0_pins>;
443 reg = <0x0 0xfdd70020 0x0 0x10>;
446 pinctrl-0 = <&pwm2m0_pins>;
454 reg = <0x0 0xfdd70030 0x0 0x10>;
457 pinctrl-0 = <&pwm3_pins>;
465 reg = <0x0 0xfdd90000 0x0 0x1000>;
471 #size-cells = <0>;
479 #power-domain-cells = <0>;
490 #power-domain-cells = <0>;
501 #power-domain-cells = <0>;
514 #power-domain-cells = <0>;
521 #power-domain-cells = <0>;
528 #power-domain-cells = <0>;
537 #power-domain-cells = <0>;
544 reg = <0x0 0xfde60000 0x0 0x4000>;
558 reg = <0x0 0xfdea0000 0x0 0x800>;
569 reg = <0x0 0xfdea0800 0x0 0x40>;
574 #iommu-cells = <0>;
579 reg = <0x0 0xfdeb0000 0x0 0x180>;
590 reg = <0x0 0xfdee0000 0x0 0x800>;
600 reg = <0x0 0xfdee0800 0x0 0x40>;
605 #iommu-cells = <0>;
610 reg = <0x0 0xfe000000 0x0 0x4000>;
615 fifo-depth = <0x100>;
624 reg = <0x0 0xfe010000 0x0 0x10000>;
648 #address-cells = <0x1>;
649 #size-cells = <0x0>;
653 snps,blen = <0 0 0 0 16 8 4>;
670 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
683 #size-cells = <0>;
685 vp0: port@0 {
686 reg = <0>;
688 #size-cells = <0>;
694 #size-cells = <0>;
700 #size-cells = <0>;
707 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
711 #iommu-cells = <0>;
718 reg = <0x00 0xfe060000 0x00 0x10000>;
732 #size-cells = <0>;
734 dsi0_in: port@0 {
735 reg = <0>;
746 reg = <0x0 0xfe070000 0x0 0x10000>;
760 #size-cells = <0>;
762 dsi1_in: port@0 {
763 reg = <0>;
774 reg = <0x0 0xfe0a0000 0x0 0x20000>;
783 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
787 #sound-dai-cells = <0>;
792 #size-cells = <0>;
794 hdmi_in: port@0 {
795 reg = <0>;
806 reg = <0x0 0xfe128000 0x0 0x20>;
811 reg = <0x0 0xfe138080 0x0 0x20>;
816 reg = <0x0 0xfe138100 0x0 0x20>;
821 reg = <0x0 0xfe138180 0x0 0x20>;
826 reg = <0x0 0xfe148000 0x0 0x20>;
831 reg = <0x0 0xfe148080 0x0 0x20>;
836 reg = <0x0 0xfe148100 0x0 0x20>;
841 reg = <0x0 0xfe150000 0x0 0x20>;
846 reg = <0x0 0xfe158000 0x0 0x20>;
851 reg = <0x0 0xfe158100 0x0 0x20>;
856 reg = <0x0 0xfe158180 0x0 0x20>;
861 reg = <0x0 0xfe158200 0x0 0x20>;
866 reg = <0x0 0xfe158280 0x0 0x20>;
871 reg = <0x0 0xfe158300 0x0 0x20>;
876 reg = <0x0 0xfe180000 0x0 0x20>;
881 reg = <0x0 0xfe190000 0x0 0x20>;
886 reg = <0x0 0xfe190280 0x0 0x20>;
891 reg = <0x0 0xfe190300 0x0 0x20>;
896 reg = <0x0 0xfe190380 0x0 0x20>;
901 reg = <0x0 0xfe190400 0x0 0x20>;
906 reg = <0x0 0xfe198000 0x0 0x20>;
911 reg = <0x0 0xfe1a8000 0x0 0x20>;
916 reg = <0x0 0xfe1a8080 0x0 0x20>;
921 reg = <0x0 0xfe1a8100 0x0 0x20>;
926 reg = <0x00 0xfe230000 0x00 0x400>;
933 reg = <0x3 0xc0000000 0x0 0x00400000>,
934 <0x0 0xfe260000 0x0 0x00010000>,
935 <0x0 0xf4000000 0x0 0x00100000>;
943 bus-range = <0x0 0xf>;
951 interrupt-map-mask = <0 0 0 7>;
952 interrupt-map = <0 0 0 1 &pcie_intc 0>,
953 <0 0 0 2 &pcie_intc 1>,
954 <0 0 0 3 &pcie_intc 2>,
955 <0 0 0 4 &pcie_intc 3>;
956 linux,pci-domain = <0>;
960 msi-map = <0x0 &gic 0x0 0x1000>;
965 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
966 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
967 <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
975 #address-cells = <0>;
985 reg = <0x0 0xfe2b0000 0x0 0x4000>;
990 fifo-depth = <0x100>;
999 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1004 fifo-depth = <0x100>;
1013 reg = <0x0 0xfe300000 0x0 0x4000>;
1017 pinctrl-0 = <&fspi_pins>;
1024 reg = <0x0 0xfe310000 0x0 0x10000>;
1037 reg = <0x0 0xfe388000 0x0 0x4000>;
1046 reg = <0x0 0xfe400000 0x0 0x1000>;
1052 dmas = <&dmac1 0>;
1057 #sound-dai-cells = <0>;
1063 reg = <0x0 0xfe410000 0x0 0x1000>;
1076 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
1082 #sound-dai-cells = <0>;
1088 reg = <0x0 0xfe420000 0x0 0x1000>;
1100 pinctrl-0 = <&i2s2m0_sclktx
1104 #sound-dai-cells = <0>;
1110 reg = <0x0 0xfe430000 0x0 0x1000>;
1120 #sound-dai-cells = <0>;
1126 reg = <0x0 0xfe440000 0x0 0x1000>;
1132 pinctrl-0 = <&pdmm0_clk
1141 #sound-dai-cells = <0>;
1147 reg = <0x0 0xfe460000 0x0 0x1000>;
1154 pinctrl-0 = <&spdifm0_tx>;
1155 #sound-dai-cells = <0>;
1161 reg = <0x0 0xfe530000 0x0 0x4000>;
1172 reg = <0x0 0xfe550000 0x0 0x4000>;
1183 reg = <0x0 0xfe5a0000 0x0 0x1000>;
1187 pinctrl-0 = <&i2c1_xfer>;
1190 #size-cells = <0>;
1196 reg = <0x0 0xfe5b0000 0x0 0x1000>;
1200 pinctrl-0 = <&i2c2m0_xfer>;
1203 #size-cells = <0>;
1209 reg = <0x0 0xfe5c0000 0x0 0x1000>;
1213 pinctrl-0 = <&i2c3m0_xfer>;
1216 #size-cells = <0>;
1222 reg = <0x0 0xfe5d0000 0x0 0x1000>;
1226 pinctrl-0 = <&i2c4m0_xfer>;
1229 #size-cells = <0>;
1235 reg = <0x0 0xfe5e0000 0x0 0x1000>;
1239 pinctrl-0 = <&i2c5m0_xfer>;
1242 #size-cells = <0>;
1248 reg = <0x0 0xfe600000 0x0 0x100>;
1256 reg = <0x0 0xfe610000 0x0 0x1000>;
1263 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1265 #size-cells = <0>;
1271 reg = <0x0 0xfe620000 0x0 0x1000>;
1278 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1280 #size-cells = <0>;
1286 reg = <0x0 0xfe630000 0x0 0x1000>;
1293 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1295 #size-cells = <0>;
1301 reg = <0x0 0xfe640000 0x0 0x1000>;
1308 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
1310 #size-cells = <0>;
1316 reg = <0x0 0xfe650000 0x0 0x100>;
1321 pinctrl-0 = <&uart1m0_xfer>;
1330 reg = <0x0 0xfe660000 0x0 0x100>;
1335 pinctrl-0 = <&uart2m0_xfer>;
1344 reg = <0x0 0xfe670000 0x0 0x100>;
1349 pinctrl-0 = <&uart3m0_xfer>;
1358 reg = <0x0 0xfe680000 0x0 0x100>;
1363 pinctrl-0 = <&uart4m0_xfer>;
1372 reg = <0x0 0xfe690000 0x0 0x100>;
1377 pinctrl-0 = <&uart5m0_xfer>;
1386 reg = <0x0 0xfe6a0000 0x0 0x100>;
1391 pinctrl-0 = <&uart6m0_xfer>;
1400 reg = <0x0 0xfe6b0000 0x0 0x100>;
1405 pinctrl-0 = <&uart7m0_xfer>;
1414 reg = <0x0 0xfe6c0000 0x0 0x100>;
1419 pinctrl-0 = <&uart8m0_xfer>;
1428 reg = <0x0 0xfe6d0000 0x0 0x100>;
1433 pinctrl-0 = <&uart9m0_xfer>;
1445 thermal-sensors = <&tsadc 0>;
1513 reg = <0x0 0xfe710000 0x0 0x100>;
1524 pinctrl-0 = <&tsadc_shutorg>;
1532 reg = <0x0 0xfe720000 0x0 0x100>;
1544 reg = <0x0 0xfe6e0000 0x0 0x10>;
1547 pinctrl-0 = <&pwm4_pins>;
1555 reg = <0x0 0xfe6e0010 0x0 0x10>;
1558 pinctrl-0 = <&pwm5_pins>;
1566 reg = <0x0 0xfe6e0020 0x0 0x10>;
1569 pinctrl-0 = <&pwm6_pins>;
1577 reg = <0x0 0xfe6e0030 0x0 0x10>;
1580 pinctrl-0 = <&pwm7_pins>;
1588 reg = <0x0 0xfe6f0000 0x0 0x10>;
1591 pinctrl-0 = <&pwm8m0_pins>;
1599 reg = <0x0 0xfe6f0010 0x0 0x10>;
1602 pinctrl-0 = <&pwm9m0_pins>;
1610 reg = <0x0 0xfe6f0020 0x0 0x10>;
1613 pinctrl-0 = <&pwm10m0_pins>;
1621 reg = <0x0 0xfe6f0030 0x0 0x10>;
1624 pinctrl-0 = <&pwm11m0_pins>;
1632 reg = <0x0 0xfe700000 0x0 0x10>;
1635 pinctrl-0 = <&pwm12m0_pins>;
1643 reg = <0x0 0xfe700010 0x0 0x10>;
1646 pinctrl-0 = <&pwm13m0_pins>;
1654 reg = <0x0 0xfe700020 0x0 0x10>;
1657 pinctrl-0 = <&pwm14m0_pins>;
1665 reg = <0x0 0xfe700030 0x0 0x10>;
1668 pinctrl-0 = <&pwm15m0_pins>;
1676 reg = <0x0 0xfe830000 0x0 0x100>;
1693 reg = <0x0 0xfe840000 0x0 0x100>;
1710 reg = <0x0 0xfe870000 0x0 0x10000>;
1713 #phy-cells = <0>;
1722 reg = <0x0 0xfe850000 0x0 0x10000>;
1725 #phy-cells = <0>;
1734 reg = <0x0 0xfe860000 0x0 0x10000>;
1737 #phy-cells = <0>;
1746 reg = <0x0 0xfe8a0000 0x0 0x10000>;
1752 #clock-cells = <0>;
1756 #phy-cells = <0>;
1761 #phy-cells = <0>;
1768 reg = <0x0 0xfe8b0000 0x0 0x10000>;
1774 #clock-cells = <0>;
1778 #phy-cells = <0>;
1783 #phy-cells = <0>;
1798 reg = <0x0 0xfdd60000 0x0 0x100>;
1802 gpio-ranges = <&pinctrl 0 0 32>;
1810 reg = <0x0 0xfe740000 0x0 0x100>;
1814 gpio-ranges = <&pinctrl 0 32 32>;
1822 reg = <0x0 0xfe750000 0x0 0x100>;
1826 gpio-ranges = <&pinctrl 0 64 32>;
1834 reg = <0x0 0xfe760000 0x0 0x100>;
1838 gpio-ranges = <&pinctrl 0 96 32>;
1846 reg = <0x0 0xfe770000 0x0 0x100>;
1850 gpio-ranges = <&pinctrl 0 128 32>;