Lines Matching +full:rockchip +full:- +full:vop
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
6 #include "rk356x-base.dtsi"
9 compatible = "rockchip,rk3568";
11 cpu0_opp_table: opp-table-0 {
12 compatible = "operating-points-v2";
13 opp-shared;
15 opp-408000000 {
16 opp-hz = /bits/ 64 <408000000>;
17 opp-microvolt = <850000 850000 1150000>;
18 clock-latency-ns = <40000>;
21 opp-600000000 {
22 opp-hz = /bits/ 64 <600000000>;
23 opp-microvolt = <850000 850000 1150000>;
24 clock-latency-ns = <40000>;
27 opp-816000000 {
28 opp-hz = /bits/ 64 <816000000>;
29 opp-microvolt = <850000 850000 1150000>;
30 clock-latency-ns = <40000>;
31 opp-suspend;
34 opp-1104000000 {
35 opp-hz = /bits/ 64 <1104000000>;
36 opp-microvolt = <900000 900000 1150000>;
37 clock-latency-ns = <40000>;
40 opp-1416000000 {
41 opp-hz = /bits/ 64 <1416000000>;
42 opp-microvolt = <1025000 1025000 1150000>;
43 clock-latency-ns = <40000>;
46 opp-1608000000 {
47 opp-hz = /bits/ 64 <1608000000>;
48 opp-microvolt = <1100000 1100000 1150000>;
49 clock-latency-ns = <40000>;
52 opp-1800000000 {
53 opp-hz = /bits/ 64 <1800000000>;
54 opp-microvolt = <1150000 1150000 1150000>;
55 clock-latency-ns = <40000>;
58 opp-1992000000 {
59 opp-hz = /bits/ 64 <1992000000>;
60 opp-microvolt = <1150000 1150000 1150000>;
61 clock-latency-ns = <40000>;
65 gpu_opp_table: opp-table-1 {
66 compatible = "operating-points-v2";
68 opp-200000000 {
69 opp-hz = /bits/ 64 <200000000>;
70 opp-microvolt = <850000 850000 1000000>;
73 opp-300000000 {
74 opp-hz = /bits/ 64 <300000000>;
75 opp-microvolt = <850000 850000 1000000>;
78 opp-400000000 {
79 opp-hz = /bits/ 64 <400000000>;
80 opp-microvolt = <850000 850000 1000000>;
83 opp-600000000 {
84 opp-hz = /bits/ 64 <600000000>;
85 opp-microvolt = <900000 900000 1000000>;
88 opp-700000000 {
89 opp-hz = /bits/ 64 <700000000>;
90 opp-microvolt = <950000 950000 1000000>;
93 opp-800000000 {
94 opp-hz = /bits/ 64 <800000000>;
95 opp-microvolt = <1000000 1000000 1000000>;
100 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
104 clock-names = "sata", "pmalive", "rxoob";
107 phy-names = "sata-phy";
108 ports-implemented = <0x1>;
109 power-domains = <&power RK3568_PD_PIPE>;
114 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
119 compatible = "rockchip,rk3568-qos", "syscon";
124 compatible = "rockchip,rk3568-qos", "syscon";
129 compatible = "rockchip,rk3568-qos", "syscon";
134 compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
139 compatible = "rockchip,rk3568-pcie3-phy";
141 #phy-cells = <0>;
144 clock-names = "refclk_m", "refclk_n", "pclk";
146 reset-names = "phy";
147 rockchip,phy-grf = <&pcie30_phy_grf>;
152 compatible = "rockchip,rk3568-pcie";
153 #address-cells = <3>;
154 #size-cells = <2>;
155 bus-range = <0x0 0xf>;
159 clock-names = "aclk_mst", "aclk_slv",
167 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
168 #interrupt-cells = <1>;
169 interrupt-map-mask = <0 0 0 7>;
170 interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
174 linux,pci-domain = <1>;
175 num-ib-windows = <6>;
176 num-ob-windows = <2>;
177 max-link-speed = <3>;
178 msi-map = <0x0 &gic 0x1000 0x1000>;
179 num-lanes = <1>;
181 phy-names = "pcie-phy";
182 power-domains = <&power RK3568_PD_PIPE>;
189 reg-names = "dbi", "apb", "config";
191 reset-names = "pipe";
195 pcie3x1_intc: legacy-interrupt-controller {
196 interrupt-controller;
197 #address-cells = <0>;
198 #interrupt-cells = <1>;
199 interrupt-parent = <&gic>;
205 compatible = "rockchip,rk3568-pcie";
206 #address-cells = <3>;
207 #size-cells = <2>;
208 bus-range = <0x0 0xf>;
212 clock-names = "aclk_mst", "aclk_slv",
220 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
221 #interrupt-cells = <1>;
222 interrupt-map-mask = <0 0 0 7>;
223 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
227 linux,pci-domain = <2>;
228 num-ib-windows = <6>;
229 num-ob-windows = <2>;
230 max-link-speed = <3>;
231 msi-map = <0x0 &gic 0x2000 0x1000>;
232 num-lanes = <2>;
234 phy-names = "pcie-phy";
235 power-domains = <&power RK3568_PD_PIPE>;
242 reg-names = "dbi", "apb", "config";
244 reset-names = "pipe";
248 pcie3x2_intc: legacy-interrupt-controller {
249 interrupt-controller;
250 #address-cells = <0>;
251 #interrupt-cells = <1>;
252 interrupt-parent = <&gic>;
258 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
262 interrupt-names = "macirq", "eth_wake_irq";
267 clock-names = "stmmaceth", "mac_clk_rx",
272 reset-names = "stmmaceth";
273 rockchip,grf = <&grf>;
274 snps,axi-config = <&gmac0_stmmac_axi_setup>;
275 snps,mixed-burst;
276 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
277 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
282 compatible = "snps,dwmac-mdio";
283 #address-cells = <0x1>;
284 #size-cells = <0x0>;
287 gmac0_stmmac_axi_setup: stmmac-axi-config {
293 gmac0_mtl_rx_setup: rx-queues-config {
294 snps,rx-queues-to-use = <1>;
298 gmac0_mtl_tx_setup: tx-queues-config {
299 snps,tx-queues-to-use = <1>;
305 compatible = "rockchip,rk3568v2-canfd";
309 clock-names = "baud", "pclk";
311 reset-names = "core", "apb";
312 pinctrl-names = "default";
313 pinctrl-0 = <&can0m0_pins>;
318 compatible = "rockchip,rk3568v2-canfd";
322 clock-names = "baud", "pclk";
324 reset-names = "core", "apb";
325 pinctrl-names = "default";
326 pinctrl-0 = <&can1m0_pins>;
331 compatible = "rockchip,rk3568v2-canfd";
335 clock-names = "baud", "pclk";
337 reset-names = "core", "apb";
338 pinctrl-names = "default";
339 pinctrl-0 = <&can2m0_pins>;
344 compatible = "rockchip,rk3568-naneng-combphy";
349 clock-names = "ref", "apb", "pipe";
350 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
351 assigned-clock-rates = <100000000>;
353 rockchip,pipe-grf = <&pipegrf>;
354 rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
355 #phy-cells = <1>;
361 operating-points-v2 = <&cpu0_opp_table>;
365 operating-points-v2 = <&cpu0_opp_table>;
369 operating-points-v2 = <&cpu0_opp_table>;
373 operating-points-v2 = <&cpu0_opp_table>;
377 operating-points-v2 = <&gpu_opp_table>;
381 compatible = "rockchip,rk3568-pipe-grf", "syscon";
385 power-domain@RK3568_PD_PIPE {
396 #power-domain-cells = <0>;
406 phy-names = "usb2-phy", "usb3-phy";
409 &vop {
410 compatible = "rockchip,rk3568-vop";