Lines Matching +full:pwm +full:- +full:gpio
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3562-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/rockchip,rk3562-power.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/reset/rockchip,rk3562-cru.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
14 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
31 xin32k: clock-xin32k {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <32768>;
35 clock-output-names = "xin32k";
38 xin24m: clock-xin24m {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <24000000>;
42 clock-output-names = "xin24m";
46 #address-cells = <2>;
47 #size-cells = <0>;
51 compatible = "arm,cortex-a53";
53 enable-method = "psci";
55 cpu-idle-states = <&CPU_SLEEP>;
56 operating-points-v2 = <&cpu0_opp_table>;
57 #cooling-cells = <2>;
58 dynamic-power-coefficient = <138>;
63 compatible = "arm,cortex-a53";
65 enable-method = "psci";
67 cpu-idle-states = <&CPU_SLEEP>;
68 operating-points-v2 = <&cpu0_opp_table>;
69 #cooling-cells = <2>;
70 dynamic-power-coefficient = <138>;
75 compatible = "arm,cortex-a53";
77 enable-method = "psci";
79 cpu-idle-states = <&CPU_SLEEP>;
80 operating-points-v2 = <&cpu0_opp_table>;
81 #cooling-cells = <2>;
82 dynamic-power-coefficient = <138>;
87 compatible = "arm,cortex-a53";
89 enable-method = "psci";
91 cpu-idle-states = <&CPU_SLEEP>;
92 operating-points-v2 = <&cpu0_opp_table>;
93 #cooling-cells = <2>;
94 dynamic-power-coefficient = <138>;
97 idle-states {
98 entry-method = "psci";
100 CPU_SLEEP: cpu-sleep {
101 compatible = "arm,idle-state";
102 local-timer-stop;
103 arm,psci-suspend-param = <0x0010000>;
104 entry-latency-us = <120>;
105 exit-latency-us = <250>;
106 min-residency-us = <900>;
111 cpu0_opp_table: opp-table-cpu0 {
112 compatible = "operating-points-v2";
113 opp-shared;
115 opp-408000000 {
116 opp-hz = /bits/ 64 <408000000>;
117 opp-microvolt = <825000 825000 1150000>;
118 clock-latency-ns = <40000>;
119 opp-suspend;
121 opp-600000000 {
122 opp-hz = /bits/ 64 <600000000>;
123 opp-microvolt = <825000 825000 1150000>;
124 clock-latency-ns = <40000>;
126 opp-816000000 {
127 opp-hz = /bits/ 64 <816000000>;
128 opp-microvolt = <825000 825000 1150000>;
129 clock-latency-ns = <40000>;
131 opp-1008000000 {
132 opp-hz = /bits/ 64 <1008000000>;
133 opp-microvolt = <850000 850000 1150000>;
134 clock-latency-ns = <40000>;
136 opp-1200000000 {
137 opp-hz = /bits/ 64 <1200000000>;
138 opp-microvolt = <925000 925000 1150000>;
139 clock-latency-ns = <40000>;
141 opp-1416000000 {
142 opp-hz = /bits/ 64 <1416000000>;
143 opp-microvolt = <1000000 1000000 1150000>;
144 clock-latency-ns = <40000>;
146 opp-1608000000 {
147 opp-supported-hw = <0xf9 0xffff>;
148 opp-hz = /bits/ 64 <1608000000>;
149 opp-microvolt = <1037500 1037500 1150000>;
150 clock-latency-ns = <40000>;
152 opp-1800000000 {
153 opp-hz = /bits/ 64 <1800000000>;
154 opp-microvolt = <1125000 1125000 1150000>;
155 clock-latency-ns = <40000>;
157 opp-2016000000 {
158 opp-hz = /bits/ 64 <2016000000>;
159 opp-microvolt = <1150000 1150000 1150000>;
160 clock-latency-ns = <40000>;
165 gpu_opp_table: opp-table-gpu {
166 compatible = "operating-points-v2";
168 opp-300000000 {
169 opp-hz = /bits/ 64 <300000000>;
170 opp-microvolt = <825000 825000 1000000>;
172 opp-400000000 {
173 opp-hz = /bits/ 64 <400000000>;
174 opp-microvolt = <825000 825000 1000000>;
176 opp-500000000 {
177 opp-hz = /bits/ 64 <500000000>;
178 opp-microvolt = <825000 825000 1000000>;
180 opp-600000000 {
181 opp-hz = /bits/ 64 <600000000>;
182 opp-microvolt = <825000 825000 1000000>;
184 opp-700000000 {
185 opp-hz = /bits/ 64 <700000000>;
186 opp-microvolt = <900000 900000 1000000>;
188 opp-800000000 {
189 opp-hz = /bits/ 64 <800000000>;
190 opp-microvolt = <950000 950000 1000000>;
192 opp-900000000 {
193 opp-hz = /bits/ 64 <900000000>;
194 opp-microvolt = <1000000 1000000 1000000>;
198 arm_pmu: arm-pmu {
199 compatible = "arm,cortex-a53-pmu";
204 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
209 compatible = "arm,scmi-smc";
211 arm,smc-id = <0x82000010>;
212 #address-cells = <1>;
213 #size-cells = <0>;
217 #clock-cells = <1>;
223 compatible = "rockchip,rk3562-pinctrl";
225 #address-cells = <2>;
226 #size-cells = <2>;
229 gpio0: gpio@ff260000 {
230 compatible = "rockchip,gpio-bank";
233 gpio-controller;
234 gpio-ranges = <&pinctrl 0 0 32>;
236 interrupt-controller;
237 #gpio-cells = <2>;
238 #interrupt-cells = <2>;
241 gpio1: gpio@ff620000 {
242 compatible = "rockchip,gpio-bank";
245 gpio-controller;
246 gpio-ranges = <&pinctrl 0 32 32>;
248 interrupt-controller;
249 #gpio-cells = <2>;
250 #interrupt-cells = <2>;
253 gpio2: gpio@ff630000 {
254 compatible = "rockchip,gpio-bank";
257 gpio-controller;
258 gpio-ranges = <&pinctrl 0 64 32>;
260 interrupt-controller;
261 #gpio-cells = <2>;
262 #interrupt-cells = <2>;
265 gpio3: gpio@ffac0000 {
266 compatible = "rockchip,gpio-bank";
269 gpio-controller;
270 gpio-ranges = <&pinctrl 0 96 32>;
272 interrupt-controller;
273 #gpio-cells = <2>;
274 #interrupt-cells = <2>;
277 gpio4: gpio@ffad0000 {
278 compatible = "rockchip,gpio-bank";
281 gpio-controller;
282 gpio-ranges = <&pinctrl 0 128 32>;
284 interrupt-controller;
285 #gpio-cells = <2>;
286 #interrupt-cells = <2>;
291 compatible = "arm,psci-1.0";
295 reserved-memory {
296 #address-cells = <2>;
297 #size-cells = <2>;
301 compatible = "arm,scmi-shmem";
303 no-map;
308 compatible = "arm,armv8-timer";
316 compatible = "simple-bus";
317 #address-cells = <2>;
318 #size-cells = <2>;
322 compatible = "rockchip,rk3562-pcie", "rockchip,rk3568-pcie";
326 reg-names = "dbi", "apb", "config";
327 bus-range = <0x0 0xff>;
331 clock-names = "aclk_mst", "aclk_slv",
340 interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
341 #interrupt-cells = <1>;
342 interrupt-map-mask = <0 0 0 7>;
343 interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
347 linux,pci-domain = <0>;
348 max-link-speed = <2>;
349 num-ib-windows = <8>;
350 num-viewport = <8>;
351 num-ob-windows = <2>;
352 num-lanes = <1>;
354 phy-names = "pcie-phy";
355 power-domains = <&power RK3562_PD_PHP>;
360 reset-names = "pipe";
361 #address-cells = <3>;
362 #size-cells = <2>;
365 pcie2x1_intc: legacy-interrupt-controller {
366 interrupt-controller;
367 #address-cells = <0>;
368 #interrupt-cells = <1>;
369 interrupt-parent = <&gic>;
374 gic: interrupt-controller@fe901000 {
375 compatible = "arm,gic-400";
376 #interrupt-cells = <3>;
377 #address-cells = <0>;
378 interrupt-controller;
387 compatible = "rockchip,rk3562-qos", "syscon";
392 compatible = "rockchip,rk3562-qos", "syscon";
397 compatible = "rockchip,rk3562-qos", "syscon";
402 compatible = "rockchip,rk3562-qos", "syscon";
407 compatible = "rockchip,rk3562-qos", "syscon";
412 compatible = "rockchip,rk3562-qos", "syscon";
417 compatible = "rockchip,rk3562-qos", "syscon";
422 compatible = "rockchip,rk3562-qos", "syscon";
427 compatible = "rockchip,rk3562-qos", "syscon";
432 compatible = "rockchip,rk3562-qos", "syscon";
437 compatible = "rockchip,rk3562-qos", "syscon";
442 compatible = "rockchip,rk3562-qos", "syscon";
447 compatible = "rockchip,rk3562-qos", "syscon";
452 compatible = "rockchip,rk3562-qos", "syscon";
457 compatible = "rockchip,rk3562-qos", "syscon";
462 compatible = "rockchip,rk3562-qos", "syscon";
467 compatible = "rockchip,rk3562-qos", "syscon";
472 compatible = "rockchip,rk3562-qos", "syscon";
477 compatible = "rockchip,rk3562-qos", "syscon";
482 compatible = "rockchip,rk3562-qos", "syscon";
487 compatible = "rockchip,rk3562-qos", "syscon";
492 compatible = "rockchip,rk3562-qos", "syscon";
497 compatible = "rockchip,rk3562-qos", "syscon";
502 compatible = "rockchip,rk3562-qos", "syscon";
507 compatible = "rockchip,rk3562-qos", "syscon";
512 compatible = "rockchip,rk3562-qos", "syscon";
517 compatible = "rockchip,rk3562-qos", "syscon";
522 compatible = "rockchip,rk3562-qos", "syscon";
527 compatible = "rockchip,rk3562-pmu-grf", "syscon", "simple-mfd";
530 reboot_mode: reboot-mode {
531 compatible = "syscon-reboot-mode";
533 mode-normal = <BOOT_NORMAL>;
534 mode-loader = <BOOT_BL_DOWNLOAD>;
535 mode-recovery = <BOOT_RECOVERY>;
536 mode-bootloader = <BOOT_FASTBOOT>;
541 compatible = "rockchip,rk3562-sys-grf", "syscon";
546 compatible = "rockchip,rk3562-peri-grf", "syscon";
551 compatible = "rockchip,rk3562-ioc-grf", "syscon";
556 compatible = "rockchip,rk3562-usbphy-grf", "syscon";
561 compatible = "rockchip,rk3562-pipephy-grf", "syscon";
565 cru: clock-controller@ff100000 {
566 compatible = "rockchip,rk3562-cru";
568 #clock-cells = <1>;
569 #reset-cells = <1>;
571 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
573 assigned-clock-rates = <1188000000>, <1000000000>,
578 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
581 clock-names = "i2c", "pclk";
583 pinctrl-names = "default";
584 pinctrl-0 = <&i2c0_xfer>;
585 #address-cells = <1>;
586 #size-cells = <0>;
591 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
595 clock-names = "baudclk", "apb_pclk";
596 reg-shift = <2>;
597 reg-io-width = <4>;
602 compatible = "rockchip,rk3562-spi", "rockchip,rk3066-spi";
606 clock-names = "spiclk", "apb_pclk";
608 dma-names = "tx", "rx";
609 num-cs = <2>;
610 pinctrl-names = "default";
611 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>;
612 #address-cells = <1>;
613 #size-cells = <0>;
617 pwm0: pwm@ff230000 {
618 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
621 clock-names = "pwm", "pclk";
622 pinctrl-names = "default";
623 pinctrl-0 = <&pwm0m0_pins>;
624 #pwm-cells = <3>;
628 pwm1: pwm@ff230010 {
629 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
632 clock-names = "pwm", "pclk";
633 pinctrl-names = "default";
634 pinctrl-0 = <&pwm1m0_pins>;
635 #pwm-cells = <3>;
639 pwm2: pwm@ff230020 {
640 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
643 clock-names = "pwm", "pclk";
644 pinctrl-names = "default";
645 pinctrl-0 = <&pwm2m0_pins>;
646 #pwm-cells = <3>;
650 pwm3: pwm@ff230030 {
651 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
654 clock-names = "pwm", "pclk";
655 pinctrl-names = "default";
656 pinctrl-0 = <&pwm3m0_pins>;
657 #pwm-cells = <3>;
661 pmu: power-management@ff258000 {
662 compatible = "rockchip,rk3562-pmu", "syscon", "simple-mfd";
665 power: power-controller {
666 compatible = "rockchip,rk3562-power-controller";
667 #power-domain-cells = <1>;
668 #address-cells = <1>;
669 #size-cells = <0>;
671 power-domain@RK3562_PD_GPU {
674 #power-domain-cells = <0>;
677 power-domain@RK3562_PD_NPU {
680 #power-domain-cells = <0>;
683 power-domain@RK3562_PD_VDPU {
686 #power-domain-cells = <0>;
689 power-domain@RK3562_PD_VI {
693 #power-domain-cells = <1>;
694 #address-cells = <1>;
695 #size-cells = <0>;
697 power-domain@RK3562_PD_VEPU {
700 #power-domain-cells = <0>;
704 power-domain@RK3562_PD_VO {
707 #power-domain-cells = <1>;
708 #address-cells = <1>;
709 #size-cells = <0>;
711 power-domain@RK3562_PD_RGA {
716 #power-domain-cells = <0>;
720 power-domain@RK3562_PD_PHP {
724 #power-domain-cells = <0>;
730 compatible = "rockchip,rk3562-mali", "arm,mali-bifrost";
734 clock-names = "clk_gpu", "clk_gpu_brg", "aclk_gpu";
735 dynamic-power-coefficient = <820>;
739 interrupt-names = "job", "mmu", "gpu";
740 operating-points-v2 = <&gpu_opp_table>;
741 power-domains = <&power RK3562_PD_GPU>;
742 #cooling-cells = <2>;
747 compatible = "rockchip,rk3066-spi";
751 clock-names = "spiclk", "apb_pclk";
753 dma-names = "tx", "rx";
754 num-cs = <2>;
755 pinctrl-names = "default";
756 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>;
757 #address-cells = <1>;
758 #size-cells = <0>;
763 compatible = "rockchip,rk3066-spi";
767 clock-names = "spiclk", "apb_pclk";
769 dma-names = "tx", "rx";
770 num-cs = <2>;
771 pinctrl-names = "default";
772 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>;
773 #address-cells = <1>;
774 #size-cells = <0>;
779 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
783 clock-names = "baudclk", "apb_pclk";
784 reg-shift = <2>;
785 reg-io-width = <4>;
790 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
794 clock-names = "baudclk", "apb_pclk";
795 reg-shift = <2>;
796 reg-io-width = <4>;
801 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
805 clock-names = "baudclk", "apb_pclk";
806 reg-shift = <2>;
807 reg-io-width = <4>;
812 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
816 clock-names = "baudclk", "apb_pclk";
817 reg-shift = <2>;
818 reg-io-width = <4>;
823 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
827 clock-names = "baudclk", "apb_pclk";
828 reg-shift = <2>;
829 reg-io-width = <4>;
834 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
838 clock-names = "baudclk", "apb_pclk";
839 reg-shift = <2>;
840 reg-io-width = <4>;
845 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
849 clock-names = "baudclk", "apb_pclk";
850 reg-shift = <2>;
851 reg-io-width = <4>;
856 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
860 clock-names = "baudclk", "apb_pclk";
861 reg-shift = <2>;
862 reg-io-width = <4>;
867 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
871 clock-names = "baudclk", "apb_pclk";
872 reg-shift = <2>;
873 reg-io-width = <4>;
877 pwm4: pwm@ff700000 {
878 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
881 clock-names = "pwm", "pclk";
882 pinctrl-names = "default";
883 pinctrl-0 = <&pwm4m0_pins>;
884 #pwm-cells = <3>;
888 pwm5: pwm@ff700010 {
889 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
892 clock-names = "pwm", "pclk";
893 pinctrl-names = "default";
894 pinctrl-0 = <&pwm5m0_pins>;
895 #pwm-cells = <3>;
899 pwm6: pwm@ff700020 {
900 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
903 clock-names = "pwm", "pclk";
904 pinctrl-names = "default";
905 pinctrl-0 = <&pwm6m0_pins>;
906 #pwm-cells = <3>;
910 pwm7: pwm@ff700030 {
911 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
914 clock-names = "pwm", "pclk";
915 pinctrl-names = "default";
916 pinctrl-0 = <&pwm7m0_pins>;
917 #pwm-cells = <3>;
921 pwm8: pwm@ff710000 {
922 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
925 clock-names = "pwm", "pclk";
926 pinctrl-names = "default";
927 pinctrl-0 = <&pwm8m0_pins>;
928 #pwm-cells = <3>;
932 pwm9: pwm@ff710010 {
933 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
936 clock-names = "pwm", "pclk";
937 pinctrl-names = "default";
938 pinctrl-0 = <&pwm9m0_pins>;
939 #pwm-cells = <3>;
943 pwm10: pwm@ff710020 {
944 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
947 clock-names = "pwm", "pclk";
948 pinctrl-names = "default";
949 pinctrl-0 = <&pwm10m0_pins>;
950 #pwm-cells = <3>;
954 pwm11: pwm@ff710030 {
955 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
958 clock-names = "pwm", "pclk";
959 pinctrl-names = "default";
960 pinctrl-0 = <&pwm11m0_pins>;
961 #pwm-cells = <3>;
965 pwm12: pwm@ff720000 {
966 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
969 clock-names = "pwm", "pclk";
970 pinctrl-names = "default";
971 pinctrl-0 = <&pwm12m0_pins>;
972 #pwm-cells = <3>;
976 pwm13: pwm@ff720010 {
977 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
980 clock-names = "pwm", "pclk";
981 pinctrl-names = "default";
982 pinctrl-0 = <&pwm13m0_pins>;
983 #pwm-cells = <3>;
987 pwm14: pwm@ff720020 {
988 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
991 clock-names = "pwm", "pclk";
992 pinctrl-names = "default";
993 pinctrl-0 = <&pwm14m0_pins>;
994 #pwm-cells = <3>;
998 pwm15: pwm@ff720030 {
999 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1002 clock-names = "pwm", "pclk";
1003 pinctrl-names = "default";
1004 pinctrl-0 = <&pwm15m0_pins>;
1005 #pwm-cells = <3>;
1010 compatible = "rockchip,rk3562-saradc";
1014 clock-names = "saradc", "apb_pclk";
1016 reset-names = "saradc-apb";
1017 #io-channel-cells = <1>;
1022 compatible = "rockchip,rk3562-naneng-combphy";
1024 #phy-cells = <1>;
1027 clock-names = "ref", "apb", "pipe";
1028 assigned-clocks = <&cru CLK_PIPEPHY_REF>;
1029 assigned-clock-rates = <100000000>;
1031 reset-names = "phy";
1032 rockchip,pipe-grf = <&peri_grf>;
1033 rockchip,pipe-phy-grf = <&pipephy_grf>;
1042 clock-names = "clk_sfc", "hclk_sfc";
1043 #address-cells = <1>;
1044 #size-cells = <0>;
1049 compatible = "rockchip,rk3562-dwcmshc", "rockchip,rk3588-dwcmshc";
1052 assigned-clocks = <&cru BCLK_EMMC>, <&cru CCLK_EMMC>;
1053 assigned-clock-rates = <200000000>, <200000000>;
1057 clock-names = "core", "bus", "axi", "block", "timer";
1061 reset-names = "core", "bus", "axi", "block", "timer";
1062 max-frequency = <200000000>;
1067 compatible = "rockchip,rk3562-dw-mshc",
1068 "rockchip,rk3288-dw-mshc";
1073 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1074 fifo-depth = <0x100>;
1075 max-frequency = <200000000>;
1077 reset-names = "reset";
1082 compatible = "rockchip,rk3562-dw-mshc",
1083 "rockchip,rk3288-dw-mshc";
1088 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1089 fifo-depth = <0x100>;
1090 max-frequency = <200000000>;
1092 reset-names = "reset";
1096 dmac: dma-controller@ff990000 {
1099 arm,pl330-periph-burst;
1101 clock-names = "apb_pclk";
1104 #dma-cells = <1>;
1108 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
1111 clock-names = "i2c", "pclk";
1113 pinctrl-names = "default";
1114 pinctrl-0 = <&i2c1m0_xfer>;
1115 #address-cells = <1>;
1116 #size-cells = <0>;
1121 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
1124 clock-names = "i2c", "pclk";
1126 pinctrl-names = "default";
1127 pinctrl-0 = <&i2c2m0_xfer>;
1128 #address-cells = <1>;
1129 #size-cells = <0>;
1134 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
1137 clock-names = "i2c", "pclk";
1139 pinctrl-names = "default";
1140 pinctrl-0 = <&i2c3m0_xfer>;
1141 #address-cells = <1>;
1142 #size-cells = <0>;
1147 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
1150 clock-names = "i2c", "pclk";
1152 pinctrl-names = "default";
1153 pinctrl-0 = <&i2c4m0_xfer>;
1154 #address-cells = <1>;
1155 #size-cells = <0>;
1160 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
1163 clock-names = "i2c", "pclk";
1165 pinctrl-names = "default";
1166 pinctrl-0 = <&i2c5m0_xfer>;
1167 #address-cells = <1>;
1168 #size-cells = <0>;
1173 compatible = "rockchip,rk3562-saradc";
1177 clock-names = "saradc", "apb_pclk";
1179 reset-names = "saradc-apb";
1180 #io-channel-cells = <1>;
1186 #include "rk3562-pinctrl.dtsi"