Lines Matching +full:disable +full:- +full:cqe +full:- +full:dcmd
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
50 #address-cells = <2>;
51 #size-cells = <0>;
53 cpu-map {
54 cluster0 { /* Cortex-A53 */
69 cluster1 { /* Cortex-A72 */
81 compatible = "arm,cortex-a53";
83 enable-method = "psci";
84 capacity-dmips-mhz = <485>;
86 #cooling-cells = <2>; /* min followed by max */
87 dynamic-power-coefficient = <100>;
88 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
89 i-cache-size = <0x8000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <256>;
92 d-cache-size = <0x8000>;
93 d-cache-line-size = <64>;
94 d-cache-sets = <128>;
95 next-level-cache = <&l2_cache_l>;
100 compatible = "arm,cortex-a53";
102 enable-method = "psci";
103 capacity-dmips-mhz = <485>;
105 #cooling-cells = <2>; /* min followed by max */
106 dynamic-power-coefficient = <100>;
107 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
108 i-cache-size = <0x8000>;
109 i-cache-line-size = <64>;
110 i-cache-sets = <256>;
111 d-cache-size = <0x8000>;
112 d-cache-line-size = <64>;
113 d-cache-sets = <128>;
114 next-level-cache = <&l2_cache_l>;
119 compatible = "arm,cortex-a53";
121 enable-method = "psci";
122 capacity-dmips-mhz = <485>;
124 #cooling-cells = <2>; /* min followed by max */
125 dynamic-power-coefficient = <100>;
126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
127 i-cache-size = <0x8000>;
128 i-cache-line-size = <64>;
129 i-cache-sets = <256>;
130 d-cache-size = <0x8000>;
131 d-cache-line-size = <64>;
132 d-cache-sets = <128>;
133 next-level-cache = <&l2_cache_l>;
138 compatible = "arm,cortex-a53";
140 enable-method = "psci";
141 capacity-dmips-mhz = <485>;
143 #cooling-cells = <2>; /* min followed by max */
144 dynamic-power-coefficient = <100>;
145 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
146 i-cache-size = <0x8000>;
147 i-cache-line-size = <64>;
148 i-cache-sets = <256>;
149 d-cache-size = <0x8000>;
150 d-cache-line-size = <64>;
151 d-cache-sets = <128>;
152 next-level-cache = <&l2_cache_l>;
157 compatible = "arm,cortex-a72";
159 enable-method = "psci";
160 capacity-dmips-mhz = <1024>;
162 #cooling-cells = <2>; /* min followed by max */
163 dynamic-power-coefficient = <436>;
164 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
165 i-cache-size = <0xC000>;
166 i-cache-line-size = <64>;
167 i-cache-sets = <256>;
168 d-cache-size = <0x8000>;
169 d-cache-line-size = <64>;
170 d-cache-sets = <256>;
171 next-level-cache = <&l2_cache_b>;
173 thermal-idle {
174 #cooling-cells = <2>;
175 duration-us = <10000>;
176 exit-latency-us = <500>;
182 compatible = "arm,cortex-a72";
184 enable-method = "psci";
185 capacity-dmips-mhz = <1024>;
187 #cooling-cells = <2>; /* min followed by max */
188 dynamic-power-coefficient = <436>;
189 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
190 i-cache-size = <0xC000>;
191 i-cache-line-size = <64>;
192 i-cache-sets = <256>;
193 d-cache-size = <0x8000>;
194 d-cache-line-size = <64>;
195 d-cache-sets = <256>;
196 next-level-cache = <&l2_cache_b>;
198 thermal-idle {
199 #cooling-cells = <2>;
200 duration-us = <10000>;
201 exit-latency-us = <500>;
205 l2_cache_l: l2-cache-cluster0 {
207 cache-level = <2>;
208 cache-unified;
209 cache-size = <0x80000>;
210 cache-line-size = <64>;
211 cache-sets = <512>;
214 l2_cache_b: l2-cache-cluster1 {
216 cache-level = <2>;
217 cache-unified;
218 cache-size = <0x100000>;
219 cache-line-size = <64>;
220 cache-sets = <1024>;
223 idle-states {
224 entry-method = "psci";
226 CPU_SLEEP: cpu-sleep {
227 compatible = "arm,idle-state";
228 local-timer-stop;
229 arm,psci-suspend-param = <0x0010000>;
230 entry-latency-us = <120>;
231 exit-latency-us = <250>;
232 min-residency-us = <900>;
235 CLUSTER_SLEEP: cluster-sleep {
236 compatible = "arm,idle-state";
237 local-timer-stop;
238 arm,psci-suspend-param = <0x1010000>;
239 entry-latency-us = <400>;
240 exit-latency-us = <500>;
241 min-residency-us = <2000>;
246 display-subsystem {
247 compatible = "rockchip,display-subsystem";
251 dmc: memory-controller {
252 compatible = "rockchip,rk3399-dmc";
254 devfreq-events = <&dfi>;
256 clock-names = "dmc_clk";
261 compatible = "arm,cortex-a53-pmu";
266 compatible = "arm,cortex-a72-pmu";
271 compatible = "arm,psci-1.0";
276 compatible = "arm,armv8-timer";
281 arm,no-tick-in-suspend;
285 compatible = "fixed-clock";
286 clock-frequency = <24000000>;
287 clock-output-names = "xin24m";
288 #clock-cells = <0>;
292 compatible = "rockchip,rk3399-pcie";
295 reg-names = "axi-base", "apb-base";
297 #address-cells = <3>;
298 #size-cells = <2>;
299 #interrupt-cells = <1>;
300 aspm-no-l0s;
301 bus-range = <0x0 0x1f>;
304 clock-names = "aclk", "aclk-perf",
309 interrupt-names = "sys", "legacy", "client";
310 interrupt-map-mask = <0 0 0 7>;
311 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
315 max-link-speed = <1>;
316 msi-map = <0x0 &its 0x0 0x1000>;
319 phy-names = "pcie-phy-0", "pcie-phy-1",
320 "pcie-phy-2", "pcie-phy-3";
327 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
331 pcie0_intc: interrupt-controller {
332 interrupt-controller;
333 #address-cells = <0>;
334 #interrupt-cells = <1>;
338 pcie0_ep: pcie-ep@f8000000 {
339 compatible = "rockchip,rk3399-pcie-ep";
342 reg-names = "apb-base", "mem-base";
345 clock-names = "aclk", "aclk-perf",
347 max-functions = /bits/ 8 <8>;
348 num-lanes = <4>;
353 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
357 phy-names = "pcie-phy-0", "pcie-phy-1",
358 "pcie-phy-2", "pcie-phy-3";
359 rockchip,max-outbound-regions = <32>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&pcie_clkreqnb_cpm>;
366 compatible = "rockchip,rk3399-gmac";
369 interrupt-names = "macirq";
374 clock-names = "stmmaceth", "mac_clk_rx",
378 power-domains = <&power RK3399_PD_GMAC>;
380 reset-names = "stmmaceth";
387 compatible = "rockchip,rk3399-dw-mshc",
388 "rockchip,rk3288-dw-mshc";
391 max-frequency = <150000000>;
394 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
395 fifo-depth = <0x100>;
396 power-domains = <&power RK3399_PD_SDIOAUDIO>;
398 reset-names = "reset";
403 compatible = "rockchip,rk3399-dw-mshc",
404 "rockchip,rk3288-dw-mshc";
407 max-frequency = <150000000>;
408 assigned-clocks = <&cru HCLK_SD>;
409 assigned-clock-rates = <200000000>;
412 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
413 fifo-depth = <0x100>;
414 power-domains = <&power RK3399_PD_SD>;
416 reset-names = "reset";
421 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
424 arasan,soc-ctl-syscon = <&grf>;
425 assigned-clocks = <&cru SCLK_EMMC>;
426 assigned-clock-rates = <200000000>;
428 clock-names = "clk_xin", "clk_ahb";
429 clock-output-names = "emmc_cardclock";
430 #clock-cells = <0>;
432 phy-names = "phy_arasan";
433 power-domains = <&power RK3399_PD_EMMC>;
434 disable-cqe-dcmd;
439 compatible = "generic-ehci";
445 phy-names = "usb";
450 compatible = "generic-ohci";
456 phy-names = "usb";
461 compatible = "generic-ehci";
467 phy-names = "usb";
472 compatible = "generic-ohci";
478 phy-names = "usb";
483 compatible = "arm,coresight-cpu-debug", "arm,primecell";
486 clock-names = "apb_pclk";
491 compatible = "arm,coresight-cpu-debug", "arm,primecell";
494 clock-names = "apb_pclk";
499 compatible = "arm,coresight-cpu-debug", "arm,primecell";
502 clock-names = "apb_pclk";
507 compatible = "arm,coresight-cpu-debug", "arm,primecell";
510 clock-names = "apb_pclk";
515 compatible = "arm,coresight-cpu-debug", "arm,primecell";
518 clock-names = "apb_pclk";
523 compatible = "arm,coresight-cpu-debug", "arm,primecell";
526 clock-names = "apb_pclk";
531 compatible = "rockchip,rk3399-dwc3";
532 #address-cells = <2>;
533 #size-cells = <2>;
538 clock-names = "ref_clk", "suspend_clk",
542 reset-names = "usb3-otg";
551 clock-names = "ref", "bus_early", "suspend";
554 phy-names = "usb2-phy", "usb3-phy";
557 snps,dis-u2-freeclk-exists-quirk;
559 snps,dis-del-phy-power-chg-quirk;
560 snps,dis-tx-ipgap-linecheck-quirk;
561 power-domains = <&power RK3399_PD_USB3>;
567 compatible = "rockchip,rk3399-dwc3";
568 #address-cells = <2>;
569 #size-cells = <2>;
574 clock-names = "ref_clk", "suspend_clk",
578 reset-names = "usb3-otg";
587 clock-names = "ref", "bus_early", "suspend";
590 phy-names = "usb2-phy", "usb3-phy";
593 snps,dis-u2-freeclk-exists-quirk;
595 snps,dis-del-phy-power-chg-quirk;
596 snps,dis-tx-ipgap-linecheck-quirk;
597 power-domains = <&power RK3399_PD_USB3>;
603 compatible = "rockchip,rk3399-cdn-dp";
606 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
607 assigned-clock-rates = <100000000>, <200000000>;
610 clock-names = "core-clk", "pclk", "spdif", "grf";
612 power-domains = <&power RK3399_PD_HDCP>;
615 reset-names = "spdif", "dptx", "apb", "core";
617 #sound-dai-cells = <1>;
622 #address-cells = <1>;
623 #size-cells = <0>;
627 remote-endpoint = <&vopb_out_dp>;
632 remote-endpoint = <&vopl_out_dp>;
638 gic: interrupt-controller@fee00000 {
639 compatible = "arm,gic-v3";
640 #interrupt-cells = <4>;
641 #address-cells = <2>;
642 #size-cells = <2>;
644 interrupt-controller;
652 its: msi-controller@fee20000 {
653 compatible = "arm,gic-v3-its";
654 msi-controller;
655 #msi-cells = <1>;
659 ppi-partitions {
660 ppi_cluster0: interrupt-partition-0 {
664 ppi_cluster1: interrupt-partition-1 {
671 compatible = "rockchip,rk3399-saradc";
674 #io-channel-cells = <1>;
676 clock-names = "saradc", "apb_pclk";
678 reset-names = "saradc-apb";
683 compatible = "rockchip,rk3399-crypto";
687 clock-names = "hclk_master", "hclk_slave", "sclk";
689 reset-names = "master", "slave", "crypto-rst";
693 compatible = "rockchip,rk3399-crypto";
697 clock-names = "hclk_master", "hclk_slave", "sclk";
699 reset-names = "master", "slave", "crypto-rst";
703 compatible = "rockchip,rk3399-i2c";
705 assigned-clocks = <&cru SCLK_I2C1>;
706 assigned-clock-rates = <200000000>;
708 clock-names = "i2c", "pclk";
710 pinctrl-names = "default";
711 pinctrl-0 = <&i2c1_xfer>;
712 #address-cells = <1>;
713 #size-cells = <0>;
718 compatible = "rockchip,rk3399-i2c";
720 assigned-clocks = <&cru SCLK_I2C2>;
721 assigned-clock-rates = <200000000>;
723 clock-names = "i2c", "pclk";
725 pinctrl-names = "default";
726 pinctrl-0 = <&i2c2_xfer>;
727 #address-cells = <1>;
728 #size-cells = <0>;
733 compatible = "rockchip,rk3399-i2c";
735 assigned-clocks = <&cru SCLK_I2C3>;
736 assigned-clock-rates = <200000000>;
738 clock-names = "i2c", "pclk";
740 pinctrl-names = "default";
741 pinctrl-0 = <&i2c3_xfer>;
742 #address-cells = <1>;
743 #size-cells = <0>;
748 compatible = "rockchip,rk3399-i2c";
750 assigned-clocks = <&cru SCLK_I2C5>;
751 assigned-clock-rates = <200000000>;
753 clock-names = "i2c", "pclk";
755 pinctrl-names = "default";
756 pinctrl-0 = <&i2c5_xfer>;
757 #address-cells = <1>;
758 #size-cells = <0>;
763 compatible = "rockchip,rk3399-i2c";
765 assigned-clocks = <&cru SCLK_I2C6>;
766 assigned-clock-rates = <200000000>;
768 clock-names = "i2c", "pclk";
770 pinctrl-names = "default";
771 pinctrl-0 = <&i2c6_xfer>;
772 #address-cells = <1>;
773 #size-cells = <0>;
778 compatible = "rockchip,rk3399-i2c";
780 assigned-clocks = <&cru SCLK_I2C7>;
781 assigned-clock-rates = <200000000>;
783 clock-names = "i2c", "pclk";
785 pinctrl-names = "default";
786 pinctrl-0 = <&i2c7_xfer>;
787 #address-cells = <1>;
788 #size-cells = <0>;
793 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
796 clock-names = "baudclk", "apb_pclk";
798 reg-shift = <2>;
799 reg-io-width = <4>;
800 pinctrl-names = "default";
801 pinctrl-0 = <&uart0_xfer>;
806 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
809 clock-names = "baudclk", "apb_pclk";
811 reg-shift = <2>;
812 reg-io-width = <4>;
813 pinctrl-names = "default";
814 pinctrl-0 = <&uart1_xfer>;
819 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
822 clock-names = "baudclk", "apb_pclk";
824 reg-shift = <2>;
825 reg-io-width = <4>;
826 pinctrl-names = "default";
827 pinctrl-0 = <&uart2c_xfer>;
832 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
835 clock-names = "baudclk", "apb_pclk";
837 reg-shift = <2>;
838 reg-io-width = <4>;
839 pinctrl-names = "default";
840 pinctrl-0 = <&uart3_xfer>;
845 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
848 clock-names = "spiclk", "apb_pclk";
851 dma-names = "tx", "rx";
852 pinctrl-names = "default";
853 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
854 #address-cells = <1>;
855 #size-cells = <0>;
860 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
863 clock-names = "spiclk", "apb_pclk";
866 dma-names = "tx", "rx";
867 pinctrl-names = "default";
868 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
869 #address-cells = <1>;
870 #size-cells = <0>;
875 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
878 clock-names = "spiclk", "apb_pclk";
881 dma-names = "tx", "rx";
882 pinctrl-names = "default";
883 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
884 #address-cells = <1>;
885 #size-cells = <0>;
890 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
893 clock-names = "spiclk", "apb_pclk";
896 dma-names = "tx", "rx";
897 pinctrl-names = "default";
898 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
899 #address-cells = <1>;
900 #size-cells = <0>;
905 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
908 clock-names = "spiclk", "apb_pclk";
911 dma-names = "tx", "rx";
912 pinctrl-names = "default";
913 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
914 power-domains = <&power RK3399_PD_SDIOAUDIO>;
915 #address-cells = <1>;
916 #size-cells = <0>;
920 thermal_zones: thermal-zones {
921 cpu_thermal: cpu-thermal {
922 polling-delay-passive = <100>;
923 polling-delay = <1000>;
925 thermal-sensors = <&tsadc 0>;
945 cooling-maps {
948 cooling-device =
954 cooling-device =
965 gpu_thermal: gpu-thermal {
966 polling-delay-passive = <100>;
967 polling-delay = <1000>;
969 thermal-sensors = <&tsadc 1>;
984 cooling-maps {
987 cooling-device =
995 compatible = "rockchip,rk3399-tsadc";
998 assigned-clocks = <&cru SCLK_TSADC>;
999 assigned-clock-rates = <750000>;
1001 clock-names = "tsadc", "apb_pclk";
1003 reset-names = "tsadc-apb";
1005 rockchip,hw-tshut-temp = <95000>;
1006 pinctrl-names = "init", "default", "sleep";
1007 pinctrl-0 = <&otp_pin>;
1008 pinctrl-1 = <&otp_out>;
1009 pinctrl-2 = <&otp_pin>;
1010 #thermal-sensor-cells = <1>;
1015 compatible = "rockchip,rk3399-qos", "syscon";
1020 compatible = "rockchip,rk3399-qos", "syscon";
1025 compatible = "rockchip,rk3399-qos", "syscon";
1030 compatible = "rockchip,rk3399-qos", "syscon";
1035 compatible = "rockchip,rk3399-qos", "syscon";
1040 compatible = "rockchip,rk3399-qos", "syscon";
1045 compatible = "rockchip,rk3399-qos", "syscon";
1050 compatible = "rockchip,rk3399-qos", "syscon";
1055 compatible = "rockchip,rk3399-qos", "syscon";
1060 compatible = "rockchip,rk3399-qos", "syscon";
1065 compatible = "rockchip,rk3399-qos", "syscon";
1070 compatible = "rockchip,rk3399-qos", "syscon";
1075 compatible = "rockchip,rk3399-qos", "syscon";
1080 compatible = "rockchip,rk3399-qos", "syscon";
1085 compatible = "rockchip,rk3399-qos", "syscon";
1090 compatible = "rockchip,rk3399-qos", "syscon";
1095 compatible = "rockchip,rk3399-qos", "syscon";
1100 compatible = "rockchip,rk3399-qos", "syscon";
1105 compatible = "rockchip,rk3399-qos", "syscon";
1110 compatible = "rockchip,rk3399-qos", "syscon";
1115 compatible = "rockchip,rk3399-qos", "syscon";
1120 compatible = "rockchip,rk3399-qos", "syscon";
1125 compatible = "rockchip,rk3399-qos", "syscon";
1130 compatible = "rockchip,rk3399-qos", "syscon";
1135 compatible = "rockchip,rk3399-qos", "syscon";
1139 pmu: power-management@ff310000 {
1140 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
1150 power: power-controller {
1151 compatible = "rockchip,rk3399-power-controller";
1152 #power-domain-cells = <1>;
1153 #address-cells = <1>;
1154 #size-cells = <0>;
1157 power-domain@RK3399_PD_IEP {
1162 #power-domain-cells = <0>;
1164 power-domain@RK3399_PD_RGA {
1170 #power-domain-cells = <0>;
1172 power-domain@RK3399_PD_VCODEC {
1177 #power-domain-cells = <0>;
1179 power-domain@RK3399_PD_VDU {
1187 #power-domain-cells = <0>;
1191 power-domain@RK3399_PD_GPU {
1195 #power-domain-cells = <0>;
1199 power-domain@RK3399_PD_EDP {
1202 #power-domain-cells = <0>;
1204 power-domain@RK3399_PD_EMMC {
1208 #power-domain-cells = <0>;
1210 power-domain@RK3399_PD_GMAC {
1215 #power-domain-cells = <0>;
1217 power-domain@RK3399_PD_SD {
1222 #power-domain-cells = <0>;
1224 power-domain@RK3399_PD_SDIOAUDIO {
1228 #power-domain-cells = <0>;
1230 power-domain@RK3399_PD_TCPD0 {
1234 #power-domain-cells = <0>;
1236 power-domain@RK3399_PD_TCPD1 {
1240 #power-domain-cells = <0>;
1242 power-domain@RK3399_PD_USB3 {
1247 #power-domain-cells = <0>;
1249 power-domain@RK3399_PD_VIO {
1251 #power-domain-cells = <1>;
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1255 power-domain@RK3399_PD_HDCP {
1261 #power-domain-cells = <0>;
1263 power-domain@RK3399_PD_ISP0 {
1269 #power-domain-cells = <0>;
1271 power-domain@RK3399_PD_ISP1 {
1277 #power-domain-cells = <0>;
1279 power-domain@RK3399_PD_VO {
1281 #power-domain-cells = <1>;
1282 #address-cells = <1>;
1283 #size-cells = <0>;
1285 power-domain@RK3399_PD_VOPB {
1291 #power-domain-cells = <0>;
1293 power-domain@RK3399_PD_VOPL {
1298 #power-domain-cells = <0>;
1306 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1309 pmu_io_domains: io-domains {
1310 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1316 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1319 clock-names = "spiclk", "apb_pclk";
1321 pinctrl-names = "default";
1322 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1323 #address-cells = <1>;
1324 #size-cells = <0>;
1329 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1332 clock-names = "baudclk", "apb_pclk";
1334 reg-shift = <2>;
1335 reg-io-width = <4>;
1336 pinctrl-names = "default";
1337 pinctrl-0 = <&uart4_xfer>;
1342 compatible = "rockchip,rk3399-i2c";
1344 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1345 assigned-clock-rates = <200000000>;
1347 clock-names = "i2c", "pclk";
1349 pinctrl-names = "default";
1350 pinctrl-0 = <&i2c0_xfer>;
1351 #address-cells = <1>;
1352 #size-cells = <0>;
1357 compatible = "rockchip,rk3399-i2c";
1359 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1360 assigned-clock-rates = <200000000>;
1362 clock-names = "i2c", "pclk";
1364 pinctrl-names = "default";
1365 pinctrl-0 = <&i2c4_xfer>;
1366 #address-cells = <1>;
1367 #size-cells = <0>;
1372 compatible = "rockchip,rk3399-i2c";
1374 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1375 assigned-clock-rates = <200000000>;
1377 clock-names = "i2c", "pclk";
1379 pinctrl-names = "default";
1380 pinctrl-0 = <&i2c8_xfer>;
1381 #address-cells = <1>;
1382 #size-cells = <0>;
1387 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1389 #pwm-cells = <3>;
1390 pinctrl-names = "default";
1391 pinctrl-0 = <&pwm0_pin>;
1397 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1399 #pwm-cells = <3>;
1400 pinctrl-names = "default";
1401 pinctrl-0 = <&pwm1_pin>;
1407 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1409 #pwm-cells = <3>;
1410 pinctrl-names = "default";
1411 pinctrl-0 = <&pwm2_pin>;
1417 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1419 #pwm-cells = <3>;
1420 pinctrl-names = "default";
1421 pinctrl-0 = <&pwm3a_pin>;
1428 compatible = "rockchip,rk3399-dfi";
1432 clock-names = "pclk_ddr_mon";
1435 vpu: video-codec@ff650000 {
1436 compatible = "rockchip,rk3399-vpu";
1440 interrupt-names = "vepu", "vdpu";
1442 clock-names = "aclk", "hclk";
1444 power-domains = <&power RK3399_PD_VCODEC>;
1452 clock-names = "aclk", "iface";
1453 #iommu-cells = <0>;
1454 power-domains = <&power RK3399_PD_VCODEC>;
1457 vdec: video-codec@ff660000 {
1458 compatible = "rockchip,rk3399-vdec";
1463 clock-names = "axi", "ahb", "cabac", "core";
1465 power-domains = <&power RK3399_PD_VDU>;
1473 clock-names = "aclk", "iface";
1474 power-domains = <&power RK3399_PD_VDU>;
1475 #iommu-cells = <0>;
1483 clock-names = "aclk", "iface";
1484 #iommu-cells = <0>;
1489 compatible = "rockchip,rk3399-rga";
1493 clock-names = "aclk", "hclk", "sclk";
1495 reset-names = "core", "axi", "ahb";
1496 power-domains = <&power RK3399_PD_RGA>;
1500 compatible = "rockchip,rk3399-efuse";
1502 #address-cells = <1>;
1503 #size-cells = <1>;
1505 clock-names = "pclk_efuse";
1508 cpu_id: cpu-id@7 {
1511 cpub_leakage: cpu-leakage@17 {
1514 gpu_leakage: gpu-leakage@18 {
1517 center_leakage: center-leakage@19 {
1520 cpul_leakage: cpu-leakage@1a {
1523 logic_leakage: logic-leakage@1b {
1526 wafer_info: wafer-info@1c {
1531 dmac_bus: dma-controller@ff6d0000 {
1536 #dma-cells = <1>;
1537 arm,pl330-periph-burst;
1539 clock-names = "apb_pclk";
1542 dmac_peri: dma-controller@ff6e0000 {
1547 #dma-cells = <1>;
1548 arm,pl330-periph-burst;
1550 clock-names = "apb_pclk";
1553 pmucru: clock-controller@ff750000 {
1554 compatible = "rockchip,rk3399-pmucru";
1557 clock-names = "xin24m";
1559 #clock-cells = <1>;
1560 #reset-cells = <1>;
1561 assigned-clocks = <&pmucru PLL_PPLL>;
1562 assigned-clock-rates = <676000000>;
1565 cru: clock-controller@ff760000 {
1566 compatible = "rockchip,rk3399-cru";
1569 clock-names = "xin24m";
1571 #clock-cells = <1>;
1572 #reset-cells = <1>;
1573 assigned-clocks =
1585 assigned-clock-rates =
1600 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1602 #address-cells = <1>;
1603 #size-cells = <1>;
1605 io_domains: io-domains {
1606 compatible = "rockchip,rk3399-io-voltage-domain";
1610 mipi_dphy_rx0: mipi-dphy-rx0 {
1611 compatible = "rockchip,rk3399-mipi-dphy-rx0";
1615 clock-names = "dphy-ref", "dphy-cfg", "grf";
1616 power-domains = <&power RK3399_PD_VIO>;
1617 #phy-cells = <0>;
1622 compatible = "rockchip,rk3399-usb2phy";
1625 clock-names = "phyclk";
1626 #clock-cells = <0>;
1627 clock-output-names = "clk_usbphy0_480m";
1630 u2phy0_host: host-port {
1631 #phy-cells = <0>;
1633 interrupt-names = "linestate";
1637 u2phy0_otg: otg-port {
1638 #phy-cells = <0>;
1642 interrupt-names = "otg-bvalid", "otg-id",
1649 compatible = "rockchip,rk3399-usb2phy";
1652 clock-names = "phyclk";
1653 #clock-cells = <0>;
1654 clock-output-names = "clk_usbphy1_480m";
1657 u2phy1_host: host-port {
1658 #phy-cells = <0>;
1660 interrupt-names = "linestate";
1664 u2phy1_otg: otg-port {
1665 #phy-cells = <0>;
1669 interrupt-names = "otg-bvalid", "otg-id",
1676 compatible = "rockchip,rk3399-emmc-phy";
1679 clock-names = "emmcclk";
1680 drive-impedance-ohm = <50>;
1681 #phy-cells = <0>;
1685 pcie_phy: pcie-phy {
1686 compatible = "rockchip,rk3399-pcie-phy";
1688 clock-names = "refclk";
1689 #phy-cells = <1>;
1691 reset-names = "phy";
1697 compatible = "rockchip,rk3399-typec-phy";
1701 clock-names = "tcpdcore", "tcpdphy-ref";
1702 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1703 assigned-clock-rates = <50000000>;
1704 power-domains = <&power RK3399_PD_TCPD0>;
1708 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1712 tcphy0_dp: dp-port {
1713 #phy-cells = <0>;
1716 tcphy0_usb3: usb3-port {
1717 #phy-cells = <0>;
1722 compatible = "rockchip,rk3399-typec-phy";
1726 clock-names = "tcpdcore", "tcpdphy-ref";
1727 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1728 assigned-clock-rates = <50000000>;
1729 power-domains = <&power RK3399_PD_TCPD1>;
1733 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1737 tcphy1_dp: dp-port {
1738 #phy-cells = <0>;
1741 tcphy1_usb3: usb3-port {
1742 #phy-cells = <0>;
1747 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt";
1754 compatible = "rockchip,rk3399-timer";
1758 clock-names = "pclk", "timer";
1762 compatible = "rockchip,rk3399-spdif";
1766 dma-names = "tx";
1767 clock-names = "mclk", "hclk";
1769 pinctrl-names = "default";
1770 pinctrl-0 = <&spdif_bus>;
1771 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1772 #sound-dai-cells = <0>;
1777 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1782 dma-names = "tx", "rx";
1783 clock-names = "i2s_clk", "i2s_hclk";
1785 pinctrl-names = "bclk_on", "bclk_off";
1786 pinctrl-0 = <&i2s0_8ch_bus>;
1787 pinctrl-1 = <&i2s0_8ch_bus_bclk_off>;
1788 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1789 #sound-dai-cells = <0>;
1794 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1798 dma-names = "tx", "rx";
1799 clock-names = "i2s_clk", "i2s_hclk";
1801 pinctrl-names = "default";
1802 pinctrl-0 = <&i2s1_2ch_bus>;
1803 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1804 #sound-dai-cells = <0>;
1809 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1813 dma-names = "tx", "rx";
1814 clock-names = "i2s_clk", "i2s_hclk";
1816 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1817 #sound-dai-cells = <0>;
1822 compatible = "rockchip,rk3399-vop-lit";
1825 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1826 assigned-clock-rates = <400000000>, <100000000>;
1828 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1830 power-domains = <&power RK3399_PD_VOPL>;
1832 reset-names = "axi", "ahb", "dclk";
1836 #address-cells = <1>;
1837 #size-cells = <0>;
1841 remote-endpoint = <&mipi_in_vopl>;
1846 remote-endpoint = <&edp_in_vopl>;
1851 remote-endpoint = <&hdmi_in_vopl>;
1856 remote-endpoint = <&mipi1_in_vopl>;
1861 remote-endpoint = <&dp_in_vopl>;
1871 clock-names = "aclk", "iface";
1872 power-domains = <&power RK3399_PD_VOPL>;
1873 #iommu-cells = <0>;
1878 compatible = "rockchip,rk3399-vop-big";
1881 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1882 assigned-clock-rates = <400000000>, <100000000>;
1884 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1886 power-domains = <&power RK3399_PD_VOPB>;
1888 reset-names = "axi", "ahb", "dclk";
1892 #address-cells = <1>;
1893 #size-cells = <0>;
1897 remote-endpoint = <&edp_in_vopb>;
1902 remote-endpoint = <&mipi_in_vopb>;
1907 remote-endpoint = <&hdmi_in_vopb>;
1912 remote-endpoint = <&mipi1_in_vopb>;
1917 remote-endpoint = <&dp_in_vopb>;
1927 clock-names = "aclk", "iface";
1928 power-domains = <&power RK3399_PD_VOPB>;
1929 #iommu-cells = <0>;
1934 compatible = "rockchip,rk3399-cif-isp";
1940 clock-names = "isp", "aclk", "hclk";
1943 phy-names = "dphy";
1944 power-domains = <&power RK3399_PD_ISP0>;
1948 #address-cells = <1>;
1949 #size-cells = <0>;
1953 #address-cells = <1>;
1954 #size-cells = <0>;
1964 clock-names = "aclk", "iface";
1965 #iommu-cells = <0>;
1966 power-domains = <&power RK3399_PD_ISP0>;
1967 rockchip,disable-mmu-reset;
1971 compatible = "rockchip,rk3399-cif-isp";
1977 clock-names = "isp", "aclk", "hclk";
1980 phy-names = "dphy";
1981 power-domains = <&power RK3399_PD_ISP1>;
1985 #address-cells = <1>;
1986 #size-cells = <0>;
1990 #address-cells = <1>;
1991 #size-cells = <0>;
2001 clock-names = "aclk", "iface";
2002 #iommu-cells = <0>;
2003 power-domains = <&power RK3399_PD_ISP1>;
2004 rockchip,disable-mmu-reset;
2007 hdmi_sound: hdmi-sound {
2008 compatible = "simple-audio-card";
2009 simple-audio-card,format = "i2s";
2010 simple-audio-card,mclk-fs = <256>;
2011 simple-audio-card,name = "hdmi-sound";
2014 simple-audio-card,cpu {
2015 sound-dai = <&i2s2>;
2017 simple-audio-card,codec {
2018 sound-dai = <&hdmi>;
2023 compatible = "rockchip,rk3399-dw-hdmi";
2025 reg-io-width = <4>;
2032 clock-names = "iahb", "isfr", "cec", "grf", "ref";
2033 power-domains = <&power RK3399_PD_HDCP>;
2035 #sound-dai-cells = <0>;
2039 #address-cells = <1>;
2040 #size-cells = <0>;
2044 #address-cells = <1>;
2045 #size-cells = <0>;
2049 remote-endpoint = <&vopb_out_hdmi>;
2053 remote-endpoint = <&vopl_out_hdmi>;
2064 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
2069 clock-names = "ref", "pclk", "phy_cfg", "grf";
2070 power-domains = <&power RK3399_PD_VIO>;
2072 reset-names = "apb";
2074 #address-cells = <1>;
2075 #size-cells = <0>;
2079 #address-cells = <1>;
2080 #size-cells = <0>;
2084 #address-cells = <1>;
2085 #size-cells = <0>;
2089 remote-endpoint = <&vopb_out_mipi>;
2094 remote-endpoint = <&vopl_out_mipi>;
2105 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
2110 clock-names = "ref", "pclk", "phy_cfg", "grf";
2111 power-domains = <&power RK3399_PD_VIO>;
2113 reset-names = "apb";
2115 #address-cells = <1>;
2116 #size-cells = <0>;
2117 #phy-cells = <0>;
2121 #address-cells = <1>;
2122 #size-cells = <0>;
2126 #address-cells = <1>;
2127 #size-cells = <0>;
2131 remote-endpoint = <&vopb_out_mipi1>;
2136 remote-endpoint = <&vopl_out_mipi1>;
2147 compatible = "rockchip,rk3399-edp";
2151 clock-names = "dp", "pclk", "grf";
2152 pinctrl-names = "default";
2153 pinctrl-0 = <&edp_hpd>;
2154 power-domains = <&power RK3399_PD_EDP>;
2156 reset-names = "dp";
2161 #address-cells = <1>;
2162 #size-cells = <0>;
2166 #address-cells = <1>;
2167 #size-cells = <0>;
2171 remote-endpoint = <&vopb_out_edp>;
2176 remote-endpoint = <&vopl_out_edp>;
2187 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
2192 interrupt-names = "job", "mmu", "gpu";
2194 #cooling-cells = <2>;
2195 dynamic-power-coefficient = <2640>;
2196 power-domains = <&power RK3399_PD_GPU>;
2201 compatible = "rockchip,rk3399-pinctrl";
2204 #address-cells = <2>;
2205 #size-cells = <2>;
2209 compatible = "rockchip,gpio-bank";
2214 gpio-controller;
2215 #gpio-cells = <0x2>;
2217 interrupt-controller;
2218 #interrupt-cells = <0x2>;
2222 compatible = "rockchip,gpio-bank";
2227 gpio-controller;
2228 #gpio-cells = <0x2>;
2230 interrupt-controller;
2231 #interrupt-cells = <0x2>;
2235 compatible = "rockchip,gpio-bank";
2240 gpio-controller;
2241 #gpio-cells = <0x2>;
2243 interrupt-controller;
2244 #interrupt-cells = <0x2>;
2248 compatible = "rockchip,gpio-bank";
2253 gpio-controller;
2254 #gpio-cells = <0x2>;
2256 interrupt-controller;
2257 #interrupt-cells = <0x2>;
2261 compatible = "rockchip,gpio-bank";
2266 gpio-controller;
2267 #gpio-cells = <0x2>;
2269 interrupt-controller;
2270 #interrupt-cells = <0x2>;
2273 pcfg_pull_up: pcfg-pull-up {
2274 bias-pull-up;
2277 pcfg_pull_down: pcfg-pull-down {
2278 bias-pull-down;
2281 pcfg_pull_none: pcfg-pull-none {
2282 bias-disable;
2285 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2286 bias-disable;
2287 drive-strength = <12>;
2290 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2291 bias-disable;
2292 drive-strength = <13>;
2295 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2296 bias-disable;
2297 drive-strength = <18>;
2300 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2301 bias-disable;
2302 drive-strength = <20>;
2305 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2306 bias-pull-up;
2307 drive-strength = <2>;
2310 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2311 bias-pull-up;
2312 drive-strength = <8>;
2315 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2316 bias-pull-up;
2317 drive-strength = <18>;
2320 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2321 bias-pull-up;
2322 drive-strength = <20>;
2325 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2326 bias-pull-down;
2327 drive-strength = <4>;
2330 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2331 bias-pull-down;
2332 drive-strength = <8>;
2335 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2336 bias-pull-down;
2337 drive-strength = <12>;
2340 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2341 bias-pull-down;
2342 drive-strength = <18>;
2345 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2346 bias-pull-down;
2347 drive-strength = <20>;
2350 pcfg_output_high: pcfg-output-high {
2351 output-high;
2354 pcfg_output_low: pcfg-output-low {
2355 output-low;
2358 pcfg_input_enable: pcfg-input-enable {
2359 input-enable;
2362 pcfg_input_pull_up: pcfg-input-pull-up {
2363 input-enable;
2364 bias-pull-up;
2367 pcfg_input_pull_down: pcfg-input-pull-down {
2368 input-enable;
2369 bias-pull-down;
2373 clk_32k: clk-32k {
2379 cif_clkin: cif-clkin {
2384 cif_clkouta: cif-clkouta {
2391 edp_hpd: edp-hpd {
2398 rgmii_pins: rgmii-pins {
2432 rmii_pins: rmii-pins {
2458 i2c0_xfer: i2c0-xfer {
2466 i2c1_xfer: i2c1-xfer {
2474 i2c2_xfer: i2c2-xfer {
2482 i2c3_xfer: i2c3-xfer {
2490 i2c4_xfer: i2c4-xfer {
2498 i2c5_xfer: i2c5-xfer {
2506 i2c6_xfer: i2c6-xfer {
2514 i2c7_xfer: i2c7-xfer {
2522 i2c8_xfer: i2c8-xfer {
2530 i2s0_2ch_bus: i2s0-2ch-bus {
2540 i2s0_2ch_bus_bclk_off: i2s0-2ch-bus-bclk-off {
2550 i2s0_8ch_bus: i2s0-8ch-bus {
2563 i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off {
2578 i2s1_2ch_bus: i2s1-2ch-bus {
2587 i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off {
2598 sdio0_bus1: sdio0-bus1 {
2603 sdio0_bus4: sdio0-bus4 {
2611 sdio0_cmd: sdio0-cmd {
2616 sdio0_clk: sdio0-clk {
2621 sdio0_cd: sdio0-cd {
2626 sdio0_pwr: sdio0-pwr {
2631 sdio0_bkpwr: sdio0-bkpwr {
2636 sdio0_wp: sdio0-wp {
2641 sdio0_int: sdio0-int {
2648 sdmmc_bus1: sdmmc-bus1 {
2653 sdmmc_bus4: sdmmc-bus4 {
2661 sdmmc_clk: sdmmc-clk {
2666 sdmmc_cmd: sdmmc-cmd {
2671 sdmmc_cd: sdmmc-cd {
2676 sdmmc_wp: sdmmc-wp {
2683 ap_pwroff: ap-pwroff {
2687 ddrio_pwroff: ddrio-pwroff {
2693 spdif_bus: spdif-bus {
2698 spdif_bus_1: spdif-bus-1 {
2705 spi0_clk: spi0-clk {
2709 spi0_cs0: spi0-cs0 {
2713 spi0_cs1: spi0-cs1 {
2717 spi0_tx: spi0-tx {
2721 spi0_rx: spi0-rx {
2728 spi1_clk: spi1-clk {
2732 spi1_cs0: spi1-cs0 {
2736 spi1_rx: spi1-rx {
2740 spi1_tx: spi1-tx {
2747 spi2_clk: spi2-clk {
2751 spi2_cs0: spi2-cs0 {
2755 spi2_rx: spi2-rx {
2759 spi2_tx: spi2-tx {
2766 spi3_clk: spi3-clk {
2770 spi3_cs0: spi3-cs0 {
2774 spi3_rx: spi3-rx {
2778 spi3_tx: spi3-tx {
2785 spi4_clk: spi4-clk {
2789 spi4_cs0: spi4-cs0 {
2793 spi4_rx: spi4-rx {
2797 spi4_tx: spi4-tx {
2804 spi5_clk: spi5-clk {
2808 spi5_cs0: spi5-cs0 {
2812 spi5_rx: spi5-rx {
2816 spi5_tx: spi5-tx {
2823 test_clkout0: test-clkout0 {
2828 test_clkout1: test-clkout1 {
2833 test_clkout2: test-clkout2 {
2840 otp_pin: otp-pin {
2844 otp_out: otp-out {
2850 uart0_xfer: uart0-xfer {
2856 uart0_cts: uart0-cts {
2861 uart0_rts: uart0-rts {
2868 uart1_xfer: uart1-xfer {
2876 uart2a_xfer: uart2a-xfer {
2884 uart2b_xfer: uart2b-xfer {
2892 uart2c_xfer: uart2c-xfer {
2900 uart3_xfer: uart3-xfer {
2906 uart3_cts: uart3-cts {
2911 uart3_rts: uart3-rts {
2918 uart4_xfer: uart4-xfer {
2926 uarthdcp_xfer: uarthdcp-xfer {
2934 pwm0_pin: pwm0-pin {
2939 pwm0_pin_pull_down: pwm0-pin-pull-down {
2944 vop0_pwm_pin: vop0-pwm-pin {
2949 vop1_pwm_pin: vop1-pwm-pin {
2956 pwm1_pin: pwm1-pin {
2961 pwm1_pin_pull_down: pwm1-pin-pull-down {
2968 pwm2_pin: pwm2-pin {
2973 pwm2_pin_pull_down: pwm2-pin-pull-down {
2980 pwm3a_pin: pwm3a-pin {
2987 pwm3b_pin: pwm3b-pin {
2994 hdmi_i2c_xfer: hdmi-i2c-xfer {
3000 hdmi_cec: hdmi-cec {
3007 pcie_clkreqn_cpm: pci-clkreqn-cpm {
3012 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {