Lines Matching +full:lvds +full:- +full:decoder
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3368-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3368-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
43 #address-cells = <0x2>;
44 #size-cells = <0x0>;
46 cpu-map {
80 compatible = "arm,cortex-a53";
82 enable-method = "psci";
83 #cooling-cells = <2>; /* min followed by max */
88 compatible = "arm,cortex-a53";
90 enable-method = "psci";
91 #cooling-cells = <2>; /* min followed by max */
96 compatible = "arm,cortex-a53";
98 enable-method = "psci";
99 #cooling-cells = <2>; /* min followed by max */
104 compatible = "arm,cortex-a53";
106 enable-method = "psci";
107 #cooling-cells = <2>; /* min followed by max */
112 compatible = "arm,cortex-a53";
114 enable-method = "psci";
115 #cooling-cells = <2>; /* min followed by max */
120 compatible = "arm,cortex-a53";
122 enable-method = "psci";
123 #cooling-cells = <2>; /* min followed by max */
128 compatible = "arm,cortex-a53";
130 enable-method = "psci";
131 #cooling-cells = <2>; /* min followed by max */
136 compatible = "arm,cortex-a53";
138 enable-method = "psci";
139 #cooling-cells = <2>; /* min followed by max */
143 arm-pmu {
144 compatible = "arm,cortex-a53-pmu";
153 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
159 compatible = "arm,psci-0.2";
164 compatible = "arm,armv8-timer";
176 compatible = "fixed-clock";
177 clock-frequency = <24000000>;
178 clock-output-names = "xin24m";
179 #clock-cells = <0>;
183 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
185 max-frequency = <150000000>;
188 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
189 fifo-depth = <0x100>;
192 reset-names = "reset";
197 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
199 max-frequency = <150000000>;
202 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
203 fifo-depth = <0x100>;
206 reset-names = "reset";
211 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
213 max-frequency = <150000000>;
216 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
217 fifo-depth = <0x100>;
220 reset-names = "reset";
228 #io-channel-cells = <1>;
230 clock-names = "saradc", "apb_pclk";
232 reset-names = "saradc-apb";
237 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
240 clock-names = "spiclk", "apb_pclk";
242 pinctrl-names = "default";
243 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
244 #address-cells = <1>;
245 #size-cells = <0>;
250 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
253 clock-names = "spiclk", "apb_pclk";
255 pinctrl-names = "default";
256 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
257 #address-cells = <1>;
258 #size-cells = <0>;
263 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
266 clock-names = "spiclk", "apb_pclk";
268 pinctrl-names = "default";
269 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
270 #address-cells = <1>;
271 #size-cells = <0>;
276 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
279 #address-cells = <1>;
280 #size-cells = <0>;
281 clock-names = "i2c";
283 pinctrl-names = "default";
284 pinctrl-0 = <&i2c2_xfer>;
289 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
292 #address-cells = <1>;
293 #size-cells = <0>;
294 clock-names = "i2c";
296 pinctrl-names = "default";
297 pinctrl-0 = <&i2c3_xfer>;
302 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
305 #address-cells = <1>;
306 #size-cells = <0>;
307 clock-names = "i2c";
309 pinctrl-names = "default";
310 pinctrl-0 = <&i2c4_xfer>;
315 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
318 #address-cells = <1>;
319 #size-cells = <0>;
320 clock-names = "i2c";
322 pinctrl-names = "default";
323 pinctrl-0 = <&i2c5_xfer>;
328 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
330 clock-frequency = <24000000>;
332 clock-names = "baudclk", "apb_pclk";
334 reg-shift = <2>;
335 reg-io-width = <4>;
340 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
342 clock-frequency = <24000000>;
344 clock-names = "baudclk", "apb_pclk";
346 reg-shift = <2>;
347 reg-io-width = <4>;
352 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
354 clock-frequency = <24000000>;
356 clock-names = "baudclk", "apb_pclk";
358 reg-shift = <2>;
359 reg-io-width = <4>;
364 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
366 clock-frequency = <24000000>;
368 clock-names = "baudclk", "apb_pclk";
370 reg-shift = <2>;
371 reg-io-width = <4>;
375 dmac_peri: dma-controller@ff250000 {
380 #dma-cells = <1>;
381 arm,pl330-broken-no-flushp;
382 arm,pl330-periph-burst;
384 clock-names = "apb_pclk";
387 thermal-zones {
388 cpu_thermal: cpu-thermal {
389 polling-delay-passive = <100>; /* milliseconds */
390 polling-delay = <5000>; /* milliseconds */
392 thermal-sensors = <&tsadc 0>;
412 cooling-maps {
415 cooling-device =
423 cooling-device =
432 gpu_thermal: gpu-thermal {
433 polling-delay-passive = <100>; /* milliseconds */
434 polling-delay = <5000>; /* milliseconds */
436 thermal-sensors = <&tsadc 1>;
451 cooling-maps {
454 cooling-device =
465 compatible = "rockchip,rk3368-tsadc";
469 clock-names = "tsadc", "apb_pclk";
471 reset-names = "tsadc-apb";
472 pinctrl-names = "init", "default", "sleep";
473 pinctrl-0 = <&otp_pin>;
474 pinctrl-1 = <&otp_out>;
475 pinctrl-2 = <&otp_pin>;
476 #thermal-sensor-cells = <1>;
477 rockchip,hw-tshut-temp = <95000>;
482 compatible = "rockchip,rk3368-gmac";
485 interrupt-names = "macirq";
491 clock-names = "stmmaceth",
499 compatible = "generic-ehci";
507 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
512 clock-names = "otg";
514 g-np-tx-fifo-size = <16>;
515 g-rx-fifo-size = <275>;
516 g-tx-fifo-size = <256 128 128 64 64 32>;
520 dmac_bus: dma-controller@ff600000 {
525 #dma-cells = <1>;
526 arm,pl330-broken-no-flushp;
527 arm,pl330-periph-burst;
529 clock-names = "apb_pclk";
533 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
536 clock-names = "i2c";
538 pinctrl-names = "default";
539 pinctrl-0 = <&i2c0_xfer>;
540 #address-cells = <1>;
541 #size-cells = <0>;
546 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
549 #address-cells = <1>;
550 #size-cells = <0>;
551 clock-names = "i2c";
553 pinctrl-names = "default";
554 pinctrl-0 = <&i2c1_xfer>;
559 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
561 #pwm-cells = <3>;
562 pinctrl-names = "default";
563 pinctrl-0 = <&pwm0_pin>;
569 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
571 #pwm-cells = <3>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&pwm1_pin>;
579 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
581 #pwm-cells = <3>;
587 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
589 #pwm-cells = <3>;
590 pinctrl-names = "default";
591 pinctrl-0 = <&pwm3_pin>;
597 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
600 clock-names = "baudclk", "apb_pclk";
602 pinctrl-names = "default";
603 pinctrl-0 = <&uart2_xfer>;
604 reg-shift = <2>;
605 reg-io-width = <4>;
610 compatible = "rockchip,rk3368-mailbox";
617 clock-names = "pclk_mailbox";
618 #mbox-cells = <1>;
622 pmu: power-management@ff730000 {
623 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
626 power: power-controller {
627 compatible = "rockchip,rk3368-power-controller";
628 #power-domain-cells = <1>;
629 #address-cells = <1>;
630 #size-cells = <0>;
651 * *_DPHY* LVDS
655 power-domain@RK3368_PD_VIO {
696 #power-domain-cells = <0>;
701 * (video endecoder & decoder) clocks that on the
704 power-domain@RK3368_PD_VIDEO {
713 #power-domain-cells = <0>;
720 power-domain@RK3368_PD_GPU_1 {
726 #power-domain-cells = <0>;
732 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
735 pmu_io_domains: io-domains {
736 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
740 reboot-mode {
741 compatible = "syscon-reboot-mode";
743 mode-normal = <BOOT_NORMAL>;
744 mode-recovery = <BOOT_RECOVERY>;
745 mode-bootloader = <BOOT_FASTBOOT>;
746 mode-loader = <BOOT_BL_DOWNLOAD>;
750 cru: clock-controller@ff760000 {
751 compatible = "rockchip,rk3368-cru";
754 clock-names = "xin24m";
756 #clock-cells = <1>;
757 #reset-cells = <1>;
761 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
764 io_domains: io-domains {
765 compatible = "rockchip,rk3368-io-voltage-domain";
771 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
779 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
783 clock-names = "pclk", "timer";
787 compatible = "rockchip,rk3368-spdif";
791 clock-names = "mclk", "hclk";
793 dma-names = "tx";
794 pinctrl-names = "default";
795 pinctrl-0 = <&spdif_tx>;
796 #sound-dai-cells = <0>;
800 i2s_2ch: i2s-2ch@ff890000 {
801 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
804 clock-names = "i2s_clk", "i2s_hclk";
807 dma-names = "tx", "rx";
808 #sound-dai-cells = <0>;
812 i2s_8ch: i2s-8ch@ff898000 {
813 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
816 clock-names = "i2s_clk", "i2s_hclk";
819 dma-names = "tx", "rx";
820 pinctrl-names = "default";
821 pinctrl-0 = <&i2s_8ch_bus>;
822 #sound-dai-cells = <0>;
831 clock-names = "aclk", "iface";
832 power-domains = <&power RK3368_PD_VIO>;
833 #iommu-cells = <0>;
843 clock-names = "aclk", "iface";
844 #iommu-cells = <0>;
845 power-domains = <&power RK3368_PD_VIO>;
846 rockchip,disable-mmu-reset;
855 clock-names = "aclk", "iface";
856 power-domains = <&power RK3368_PD_VIO>;
857 #iommu-cells = <0>;
867 clock-names = "aclk", "iface";
868 #iommu-cells = <0>;
878 clock-names = "aclk", "iface";
879 #iommu-cells = <0>;
884 compatible = "rockchip,rk3368-qos", "syscon";
889 compatible = "rockchip,rk3368-qos", "syscon";
894 compatible = "rockchip,rk3368-qos", "syscon";
899 compatible = "rockchip,rk3368-qos", "syscon";
904 compatible = "rockchip,rk3368-qos", "syscon";
909 compatible = "rockchip,rk3368-qos", "syscon";
914 compatible = "rockchip,rk3368-qos", "syscon";
919 compatible = "rockchip,rk3368-qos", "syscon";
924 compatible = "rockchip,rk3368-qos", "syscon";
929 compatible = "rockchip,rk3368-qos", "syscon";
934 compatible = "rockchip,rk3368-qos", "syscon";
939 compatible = "rockchip,rk3368-qos", "syscon";
944 compatible = "rockchip,rk3368-qos", "syscon";
949 compatible = "rockchip,rk3368-efuse";
951 #address-cells = <1>;
952 #size-cells = <1>;
954 clock-names = "pclk_efuse";
956 cpu_leakage: cpu-leakage@17 {
959 temp_adjust: temp-adjust@1f {
964 gic: interrupt-controller@ffb71000 {
965 compatible = "arm,gic-400";
966 interrupt-controller;
967 #interrupt-cells = <3>;
968 #address-cells = <0>;
979 compatible = "rockchip,rk3368-pinctrl";
982 #address-cells = <0x2>;
983 #size-cells = <0x2>;
987 compatible = "rockchip,gpio-bank";
992 gpio-controller;
993 #gpio-cells = <0x2>;
995 interrupt-controller;
996 #interrupt-cells = <0x2>;
1000 compatible = "rockchip,gpio-bank";
1005 gpio-controller;
1006 #gpio-cells = <0x2>;
1008 interrupt-controller;
1009 #interrupt-cells = <0x2>;
1013 compatible = "rockchip,gpio-bank";
1018 gpio-controller;
1019 #gpio-cells = <0x2>;
1021 interrupt-controller;
1022 #interrupt-cells = <0x2>;
1026 compatible = "rockchip,gpio-bank";
1031 gpio-controller;
1032 #gpio-cells = <0x2>;
1034 interrupt-controller;
1035 #interrupt-cells = <0x2>;
1038 pcfg_pull_up: pcfg-pull-up {
1039 bias-pull-up;
1042 pcfg_pull_down: pcfg-pull-down {
1043 bias-pull-down;
1046 pcfg_pull_none: pcfg-pull-none {
1047 bias-disable;
1050 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1051 bias-disable;
1052 drive-strength = <12>;
1056 emmc_clk: emmc-clk {
1060 emmc_cmd: emmc-cmd {
1064 emmc_pwr: emmc-pwr {
1068 emmc_bus1: emmc-bus1 {
1072 emmc_bus4: emmc-bus4 {
1079 emmc_bus8: emmc-bus8 {
1092 rgmii_pins: rgmii-pins {
1110 rmii_pins: rmii-pins {
1125 i2c0_xfer: i2c0-xfer {
1132 i2c1_xfer: i2c1-xfer {
1139 i2c2_xfer: i2c2-xfer {
1146 i2c3_xfer: i2c3-xfer {
1153 i2c4_xfer: i2c4-xfer {
1160 i2c5_xfer: i2c5-xfer {
1167 i2s_8ch_bus: i2s-8ch-bus {
1181 pwm0_pin: pwm0-pin {
1187 pwm1_pin: pwm1-pin {
1193 pwm3_pin: pwm3-pin {
1199 sdio0_bus1: sdio0-bus1 {
1203 sdio0_bus4: sdio0-bus4 {
1210 sdio0_cmd: sdio0-cmd {
1214 sdio0_clk: sdio0-clk {
1218 sdio0_cd: sdio0-cd {
1222 sdio0_wp: sdio0-wp {
1226 sdio0_pwr: sdio0-pwr {
1230 sdio0_bkpwr: sdio0-bkpwr {
1234 sdio0_int: sdio0-int {
1240 sdmmc_clk: sdmmc-clk {
1244 sdmmc_cmd: sdmmc-cmd {
1248 sdmmc_cd: sdmmc-cd {
1252 sdmmc_bus1: sdmmc-bus1 {
1256 sdmmc_bus4: sdmmc-bus4 {
1265 spdif_tx: spdif-tx {
1271 spi0_clk: spi0-clk {
1274 spi0_cs0: spi0-cs0 {
1277 spi0_cs1: spi0-cs1 {
1280 spi0_tx: spi0-tx {
1283 spi0_rx: spi0-rx {
1289 spi1_clk: spi1-clk {
1292 spi1_cs0: spi1-cs0 {
1295 spi1_cs1: spi1-cs1 {
1298 spi1_rx: spi1-rx {
1301 spi1_tx: spi1-tx {
1307 spi2_clk: spi2-clk {
1310 spi2_cs0: spi2-cs0 {
1313 spi2_rx: spi2-rx {
1316 spi2_tx: spi2-tx {
1322 otp_pin: otp-pin {
1326 otp_out: otp-out {
1332 uart0_xfer: uart0-xfer {
1337 uart0_cts: uart0-cts {
1341 uart0_rts: uart0-rts {
1347 uart1_xfer: uart1-xfer {
1352 uart1_cts: uart1-cts {
1356 uart1_rts: uart1-rts {
1362 uart2_xfer: uart2-xfer {
1370 uart3_xfer: uart3-xfer {
1375 uart3_cts: uart3-cts {
1379 uart3_rts: uart3-rts {
1385 uart4_xfer: uart4-xfer {
1390 uart4_cts: uart4-cts {
1394 uart4_rts: uart4-rts {