Lines Matching +full:0 +full:xff110000
43 #address-cells = <0x2>;
44 #size-cells = <0x0>;
78 cpu_l0: cpu@0 {
81 reg = <0x0 0x0>;
89 reg = <0x0 0x1>;
97 reg = <0x0 0x2>;
105 reg = <0x0 0x3>;
113 reg = <0x0 0x100>;
121 reg = <0x0 0x101>;
129 reg = <0x0 0x102>;
137 reg = <0x0 0x103>;
179 #clock-cells = <0>;
184 reg = <0x0 0xff0c0000 0x0 0x4000>;
189 fifo-depth = <0x100>;
198 reg = <0x0 0xff0d0000 0x0 0x4000>;
203 fifo-depth = <0x100>;
212 reg = <0x0 0xff0f0000 0x0 0x4000>;
217 fifo-depth = <0x100>;
226 reg = <0x0 0xff100000 0x0 0x100>;
238 reg = <0x0 0xff110000 0x0 0x1000>;
243 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
245 #size-cells = <0>;
251 reg = <0x0 0xff120000 0x0 0x1000>;
256 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
258 #size-cells = <0>;
264 reg = <0x0 0xff130000 0x0 0x1000>;
269 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
271 #size-cells = <0>;
277 reg = <0x0 0xff140000 0x0 0x1000>;
280 #size-cells = <0>;
284 pinctrl-0 = <&i2c2_xfer>;
290 reg = <0x0 0xff150000 0x0 0x1000>;
293 #size-cells = <0>;
297 pinctrl-0 = <&i2c3_xfer>;
303 reg = <0x0 0xff160000 0x0 0x1000>;
306 #size-cells = <0>;
310 pinctrl-0 = <&i2c4_xfer>;
316 reg = <0x0 0xff170000 0x0 0x1000>;
319 #size-cells = <0>;
323 pinctrl-0 = <&i2c5_xfer>;
329 reg = <0x0 0xff180000 0x0 0x100>;
341 reg = <0x0 0xff190000 0x0 0x100>;
353 reg = <0x0 0xff1b0000 0x0 0x100>;
365 reg = <0x0 0xff1c0000 0x0 0x100>;
377 reg = <0x0 0xff250000 0x0 0x4000>;
392 thermal-sensors = <&tsadc 0>;
466 reg = <0x0 0xff280000 0x0 0x100>;
473 pinctrl-0 = <&otp_pin>;
483 reg = <0x0 0xff290000 0x0 0x10000>;
500 reg = <0x0 0xff500000 0x0 0x100>;
509 reg = <0x0 0xff580000 0x0 0x40000>;
522 reg = <0x0 0xff600000 0x0 0x4000>;
523 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
534 reg = <0x0 0xff650000 0x0 0x1000>;
539 pinctrl-0 = <&i2c0_xfer>;
541 #size-cells = <0>;
547 reg = <0x0 0xff660000 0x0 0x1000>;
550 #size-cells = <0>;
554 pinctrl-0 = <&i2c1_xfer>;
560 reg = <0x0 0xff680000 0x0 0x10>;
563 pinctrl-0 = <&pwm0_pin>;
570 reg = <0x0 0xff680010 0x0 0x10>;
573 pinctrl-0 = <&pwm1_pin>;
580 reg = <0x0 0xff680020 0x0 0x10>;
588 reg = <0x0 0xff680030 0x0 0x10>;
591 pinctrl-0 = <&pwm3_pin>;
598 reg = <0x0 0xff690000 0x0 0x100>;
603 pinctrl-0 = <&uart2_xfer>;
611 reg = <0x0 0xff6b0000 0x0 0x1000>;
624 reg = <0x0 0xff730000 0x0 0x1000>;
630 #size-cells = <0>;
696 #power-domain-cells = <0>;
713 #power-domain-cells = <0>;
726 #power-domain-cells = <0>;
733 reg = <0x0 0xff738000 0x0 0x1000>;
742 offset = <0x200>;
752 reg = <0x0 0xff760000 0x0 0x1000>;
762 reg = <0x0 0xff770000 0x0 0x1000>;
772 reg = <0x0 0xff800000 0x0 0x100>;
780 reg = <0x0 0xff810000 0x0 0x20>;
788 reg = <0x0 0xff880000 0x0 0x1000>;
795 pinctrl-0 = <&spdif_tx>;
796 #sound-dai-cells = <0>;
802 reg = <0x0 0xff890000 0x0 0x1000>;
808 #sound-dai-cells = <0>;
814 reg = <0x0 0xff898000 0x0 0x1000>;
818 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
821 pinctrl-0 = <&i2s_8ch_bus>;
822 #sound-dai-cells = <0>;
828 reg = <0x0 0xff900800 0x0 0x100>;
833 #iommu-cells = <0>;
839 reg = <0x0 0xff914000 0x0 0x100>,
840 <0x0 0xff915000 0x0 0x100>;
844 #iommu-cells = <0>;
852 reg = <0x0 0xff930300 0x0 0x100>;
857 #iommu-cells = <0>;
863 reg = <0x0 0xff9a0440 0x0 0x40>,
864 <0x0 0xff9a0480 0x0 0x40>;
868 #iommu-cells = <0>;
874 reg = <0x0 0xff9a0800 0x0 0x100>;
879 #iommu-cells = <0>;
885 reg = <0x0 0xffad0000 0x0 0x20>;
890 reg = <0x0 0xffad0080 0x0 0x20>;
895 reg = <0x0 0xffad0100 0x0 0x20>;
900 reg = <0x0 0xffad0180 0x0 0x20>;
905 reg = <0x0 0xffad0200 0x0 0x20>;
910 reg = <0x0 0xffad0280 0x0 0x20>;
915 reg = <0x0 0xffad0300 0x0 0x20>;
920 reg = <0x0 0xffad0380 0x0 0x20>;
925 reg = <0x0 0xffad0400 0x0 0x20>;
930 reg = <0x0 0xffae0000 0x0 0x20>;
935 reg = <0x0 0xffae0100 0x0 0x20>;
940 reg = <0x0 0xffae0180 0x0 0x20>;
945 reg = <0x0 0xffaf0000 0x0 0x20>;
950 reg = <0x0 0xffb00000 0x0 0x20>;
957 reg = <0x17 0x1>;
960 reg = <0x1f 0x1>;
968 #address-cells = <0>;
970 reg = <0x0 0xffb71000 0x0 0x1000>,
971 <0x0 0xffb72000 0x0 0x2000>,
972 <0x0 0xffb74000 0x0 0x2000>,
973 <0x0 0xffb76000 0x0 0x2000>;
982 #address-cells = <0x2>;
983 #size-cells = <0x2>;
988 reg = <0x0 0xff750000 0x0 0x100>;
990 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
993 #gpio-cells = <0x2>;
996 #interrupt-cells = <0x2>;
1001 reg = <0x0 0xff780000 0x0 0x100>;
1003 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1006 #gpio-cells = <0x2>;
1009 #interrupt-cells = <0x2>;
1014 reg = <0x0 0xff790000 0x0 0x100>;
1016 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1019 #gpio-cells = <0x2>;
1022 #interrupt-cells = <0x2>;
1027 reg = <0x0 0xff7a0000 0x0 0x100>;
1029 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1032 #gpio-cells = <0x2>;
1035 #interrupt-cells = <0x2>;
1126 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1127 <0 RK_PA7 1 &pcfg_pull_none>;
1140 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>,
1188 rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
1308 rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>;
1311 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1314 rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>;
1317 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1323 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
1327 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1348 rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,
1349 <0 RK_PC5 3 &pcfg_pull_none>;
1353 rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>;
1357 rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>;
1386 rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,
1387 <0 RK_PD2 3 &pcfg_pull_none>;
1391 rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>;
1395 rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;