Lines Matching +full:tsadc +full:- +full:apb
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3328-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <2>;
38 #size-cells = <0>;
42 compatible = "arm,cortex-a53";
45 #cooling-cells = <2>;
46 cpu-idle-states = <&CPU_SLEEP>;
47 dynamic-power-coefficient = <120>;
48 enable-method = "psci";
49 operating-points-v2 = <&cpu0_opp_table>;
50 i-cache-size = <0x8000>;
51 i-cache-line-size = <64>;
52 i-cache-sets = <256>;
53 d-cache-size = <0x8000>;
54 d-cache-line-size = <64>;
55 d-cache-sets = <128>;
56 next-level-cache = <&l2_cache>;
61 compatible = "arm,cortex-a53";
64 #cooling-cells = <2>;
65 cpu-idle-states = <&CPU_SLEEP>;
66 dynamic-power-coefficient = <120>;
67 enable-method = "psci";
68 operating-points-v2 = <&cpu0_opp_table>;
69 i-cache-size = <0x8000>;
70 i-cache-line-size = <64>;
71 i-cache-sets = <256>;
72 d-cache-size = <0x8000>;
73 d-cache-line-size = <64>;
74 d-cache-sets = <128>;
75 next-level-cache = <&l2_cache>;
80 compatible = "arm,cortex-a53";
83 #cooling-cells = <2>;
84 cpu-idle-states = <&CPU_SLEEP>;
85 dynamic-power-coefficient = <120>;
86 enable-method = "psci";
87 operating-points-v2 = <&cpu0_opp_table>;
88 i-cache-size = <0x8000>;
89 i-cache-line-size = <64>;
90 i-cache-sets = <256>;
91 d-cache-size = <0x8000>;
92 d-cache-line-size = <64>;
93 d-cache-sets = <128>;
94 next-level-cache = <&l2_cache>;
99 compatible = "arm,cortex-a53";
102 #cooling-cells = <2>;
103 cpu-idle-states = <&CPU_SLEEP>;
104 dynamic-power-coefficient = <120>;
105 enable-method = "psci";
106 operating-points-v2 = <&cpu0_opp_table>;
107 i-cache-size = <0x8000>;
108 i-cache-line-size = <64>;
109 i-cache-sets = <256>;
110 d-cache-size = <0x8000>;
111 d-cache-line-size = <64>;
112 d-cache-sets = <128>;
113 next-level-cache = <&l2_cache>;
116 idle-states {
117 entry-method = "psci";
119 CPU_SLEEP: cpu-sleep {
120 compatible = "arm,idle-state";
121 local-timer-stop;
122 arm,psci-suspend-param = <0x0010000>;
123 entry-latency-us = <120>;
124 exit-latency-us = <250>;
125 min-residency-us = <900>;
129 l2_cache: l2-cache {
131 cache-level = <2>;
132 cache-unified;
133 cache-size = <0x40000>;
134 cache-line-size = <64>;
135 cache-sets = <256>;
139 cpu0_opp_table: opp-table-0 {
140 compatible = "operating-points-v2";
141 opp-shared;
143 opp-408000000 {
144 opp-hz = /bits/ 64 <408000000>;
145 opp-microvolt = <950000>;
146 clock-latency-ns = <40000>;
147 opp-suspend;
149 opp-600000000 {
150 opp-hz = /bits/ 64 <600000000>;
151 opp-microvolt = <950000>;
152 clock-latency-ns = <40000>;
154 opp-816000000 {
155 opp-hz = /bits/ 64 <816000000>;
156 opp-microvolt = <1000000>;
157 clock-latency-ns = <40000>;
159 opp-1008000000 {
160 opp-hz = /bits/ 64 <1008000000>;
161 opp-microvolt = <1100000>;
162 clock-latency-ns = <40000>;
164 opp-1200000000 {
165 opp-hz = /bits/ 64 <1200000000>;
166 opp-microvolt = <1225000>;
167 clock-latency-ns = <40000>;
169 opp-1296000000 {
170 opp-hz = /bits/ 64 <1296000000>;
171 opp-microvolt = <1300000>;
172 clock-latency-ns = <40000>;
176 analog_sound: analog-sound {
177 compatible = "simple-audio-card";
178 simple-audio-card,format = "i2s";
179 simple-audio-card,mclk-fs = <256>;
180 simple-audio-card,name = "Analog";
183 simple-audio-card,cpu {
184 sound-dai = <&i2s1>;
187 simple-audio-card,codec {
188 sound-dai = <&codec>;
192 arm-pmu {
193 compatible = "arm,cortex-a53-pmu";
198 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
201 display_subsystem: display-subsystem {
202 compatible = "rockchip,display-subsystem";
206 hdmi_sound: hdmi-sound {
207 compatible = "simple-audio-card";
208 simple-audio-card,format = "i2s";
209 simple-audio-card,mclk-fs = <128>;
210 simple-audio-card,name = "HDMI";
213 simple-audio-card,cpu {
214 sound-dai = <&i2s0>;
217 simple-audio-card,codec {
218 sound-dai = <&hdmi>;
223 compatible = "arm,psci-1.0", "arm,psci-0.2";
228 compatible = "arm,armv8-timer";
236 compatible = "fixed-clock";
237 #clock-cells = <0>;
238 clock-frequency = <24000000>;
239 clock-output-names = "xin24m";
243 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
247 clock-names = "i2s_clk", "i2s_hclk";
249 dma-names = "tx", "rx";
250 #sound-dai-cells = <0>;
255 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
259 clock-names = "i2s_clk", "i2s_hclk";
261 dma-names = "tx", "rx";
262 #sound-dai-cells = <0>;
267 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
271 clock-names = "i2s_clk", "i2s_hclk";
273 dma-names = "tx", "rx";
274 #sound-dai-cells = <0>;
279 compatible = "rockchip,rk3328-spdif";
283 clock-names = "mclk", "hclk";
285 dma-names = "tx";
286 pinctrl-names = "default";
287 pinctrl-0 = <&spdifm2_tx>;
288 #sound-dai-cells = <0>;
296 clock-names = "pdm_clk", "pdm_hclk";
298 dma-names = "rx";
299 pinctrl-names = "default", "sleep";
300 pinctrl-0 = <&pdmm0_clk
305 pinctrl-1 = <&pdmm0_clk_sleep
314 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
317 io_domains: io-domains {
318 compatible = "rockchip,rk3328-io-voltage-domain";
323 compatible = "rockchip,rk3328-grf-gpio";
324 gpio-controller;
325 #gpio-cells = <2>;
328 power: power-controller {
329 compatible = "rockchip,rk3328-power-controller";
330 #power-domain-cells = <1>;
331 #address-cells = <1>;
332 #size-cells = <0>;
334 power-domain@RK3328_PD_HEVC {
337 #power-domain-cells = <0>;
339 power-domain@RK3328_PD_VIDEO {
345 #power-domain-cells = <0>;
347 power-domain@RK3328_PD_VPU {
350 #power-domain-cells = <0>;
354 reboot-mode {
355 compatible = "syscon-reboot-mode";
357 mode-normal = <BOOT_NORMAL>;
358 mode-recovery = <BOOT_RECOVERY>;
359 mode-bootloader = <BOOT_FASTBOOT>;
360 mode-loader = <BOOT_BL_DOWNLOAD>;
365 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
369 clock-names = "baudclk", "apb_pclk";
371 dma-names = "tx", "rx";
372 pinctrl-names = "default";
373 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
374 reg-io-width = <4>;
375 reg-shift = <2>;
380 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
384 clock-names = "baudclk", "apb_pclk";
386 dma-names = "tx", "rx";
387 pinctrl-names = "default";
388 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
389 reg-io-width = <4>;
390 reg-shift = <2>;
395 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
399 clock-names = "baudclk", "apb_pclk";
401 dma-names = "tx", "rx";
402 pinctrl-names = "default";
403 pinctrl-0 = <&uart2m1_xfer>;
404 reg-io-width = <4>;
405 reg-shift = <2>;
410 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
413 #address-cells = <1>;
414 #size-cells = <0>;
416 clock-names = "i2c", "pclk";
417 pinctrl-names = "default";
418 pinctrl-0 = <&i2c0_xfer>;
423 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
426 #address-cells = <1>;
427 #size-cells = <0>;
429 clock-names = "i2c", "pclk";
430 pinctrl-names = "default";
431 pinctrl-0 = <&i2c1_xfer>;
436 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
439 #address-cells = <1>;
440 #size-cells = <0>;
442 clock-names = "i2c", "pclk";
443 pinctrl-names = "default";
444 pinctrl-0 = <&i2c2_xfer>;
449 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
452 #address-cells = <1>;
453 #size-cells = <0>;
455 clock-names = "i2c", "pclk";
456 pinctrl-names = "default";
457 pinctrl-0 = <&i2c3_xfer>;
462 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
465 #address-cells = <1>;
466 #size-cells = <0>;
468 clock-names = "spiclk", "apb_pclk";
470 dma-names = "tx", "rx";
471 pinctrl-names = "default";
472 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
477 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt";
484 compatible = "rockchip,rk3328-pwm";
487 clock-names = "pwm", "pclk";
488 pinctrl-names = "default";
489 pinctrl-0 = <&pwm0_pin>;
490 #pwm-cells = <3>;
495 compatible = "rockchip,rk3328-pwm";
498 clock-names = "pwm", "pclk";
499 pinctrl-names = "default";
500 pinctrl-0 = <&pwm1_pin>;
501 #pwm-cells = <3>;
506 compatible = "rockchip,rk3328-pwm";
509 clock-names = "pwm", "pclk";
510 pinctrl-names = "default";
511 pinctrl-0 = <&pwm2_pin>;
512 #pwm-cells = <3>;
517 compatible = "rockchip,rk3328-pwm";
520 clock-names = "pwm", "pclk";
521 pinctrl-names = "default";
522 pinctrl-0 = <&pwmir_pin>;
523 #pwm-cells = <3>;
527 dmac: dma-controller@ff1f0000 {
532 arm,pl330-periph-burst;
534 clock-names = "apb_pclk";
535 #dma-cells = <1>;
538 thermal-zones {
539 soc_thermal: soc-thermal {
540 polling-delay-passive = <20>;
541 polling-delay = <1000>;
542 sustainable-power = <1000>;
544 thermal-sensors = <&tsadc 0>;
547 threshold: trip-point0 {
552 target: trip-point1 {
557 soc_crit: soc-crit {
564 cooling-maps {
567 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
578 tsadc: tsadc@ff250000 { label
579 compatible = "rockchip,rk3328-tsadc";
582 assigned-clocks = <&cru SCLK_TSADC>;
583 assigned-clock-rates = <50000>;
585 clock-names = "tsadc", "apb_pclk";
586 pinctrl-names = "init", "default", "sleep";
587 pinctrl-0 = <&otp_pin>;
588 pinctrl-1 = <&otp_out>;
589 pinctrl-2 = <&otp_pin>;
591 reset-names = "tsadc-apb";
593 rockchip,hw-tshut-temp = <100000>;
594 #thermal-sensor-cells = <1>;
599 compatible = "rockchip,rk3328-efuse";
601 #address-cells = <1>;
602 #size-cells = <1>;
604 clock-names = "pclk_efuse";
605 rockchip,efuse-size = <0x20>;
611 cpu_leakage: cpu-leakage@17 {
614 logic_leakage: logic-leakage@19 {
617 efuse_cpu_version: cpu-version@1a {
624 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
627 #io-channel-cells = <1>;
629 clock-names = "saradc", "apb_pclk";
631 reset-names = "saradc-apb";
636 compatible = "rockchip,rk3328-mali", "arm,mali-450";
645 interrupt-names = "gp",
653 clock-names = "bus", "core";
662 clock-names = "aclk", "iface";
663 #iommu-cells = <0>;
672 clock-names = "aclk", "iface";
673 #iommu-cells = <0>;
677 vpu: video-codec@ff350000 {
678 compatible = "rockchip,rk3328-vpu";
681 interrupt-names = "vdpu";
683 clock-names = "aclk", "hclk";
685 power-domains = <&power RK3328_PD_VPU>;
693 clock-names = "aclk", "iface";
694 #iommu-cells = <0>;
695 power-domains = <&power RK3328_PD_VPU>;
698 vdec: video-codec@ff360000 {
699 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
704 clock-names = "axi", "ahb", "cabac", "core";
705 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
707 assigned-clock-rates = <400000000>, <400000000>, <300000000>;
709 power-domains = <&power RK3328_PD_VIDEO>;
717 clock-names = "aclk", "iface";
718 #iommu-cells = <0>;
719 power-domains = <&power RK3328_PD_VIDEO>;
723 compatible = "rockchip,rk3328-vop";
727 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
729 reset-names = "axi", "ahb", "dclk";
734 #address-cells = <1>;
735 #size-cells = <0>;
739 remote-endpoint = <&hdmi_in_vop>;
749 clock-names = "aclk", "iface";
750 #iommu-cells = <0>;
755 compatible = "rockchip,rk3328-dw-hdmi";
757 reg-io-width = <4>;
762 clock-names = "iahb",
766 phy-names = "hdmi";
767 pinctrl-names = "default";
768 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
770 #sound-dai-cells = <0>;
774 #address-cells = <1>;
775 #size-cells = <0>;
781 remote-endpoint = <&vop_out_hdmi>;
792 compatible = "rockchip,rk3328-codec";
795 clock-names = "pclk", "mclk";
797 #sound-dai-cells = <0>;
802 compatible = "rockchip,rk3328-hdmi-phy";
806 clock-names = "sysclk", "refoclk", "refpclk";
807 clock-output-names = "hdmi_phy";
808 #clock-cells = <0>;
809 nvmem-cells = <&efuse_cpu_version>;
810 nvmem-cell-names = "cpu-version";
811 #phy-cells = <0>;
815 cru: clock-controller@ff440000 {
816 compatible = "rockchip,rk3328-cru";
819 clock-names = "xin24m";
821 #clock-cells = <1>;
822 #reset-cells = <1>;
823 assigned-clocks =
846 assigned-clock-parents =
850 assigned-clock-rates =
870 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
871 "simple-mfd";
873 #address-cells = <1>;
874 #size-cells = <1>;
877 compatible = "rockchip,rk3328-usb2phy";
880 clock-names = "phyclk";
881 clock-output-names = "usb480m_phy";
882 #clock-cells = <0>;
883 assigned-clocks = <&cru USB480M>;
884 assigned-clock-parents = <&u2phy>;
887 u2phy_otg: otg-port {
888 #phy-cells = <0>;
892 interrupt-names = "otg-bvalid", "otg-id",
897 u2phy_host: host-port {
898 #phy-cells = <0>;
900 interrupt-names = "linestate";
907 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
912 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
913 fifo-depth = <0x100>;
914 max-frequency = <150000000>;
916 reset-names = "reset";
921 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
926 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
927 fifo-depth = <0x100>;
928 max-frequency = <150000000>;
930 reset-names = "reset";
935 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
940 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
941 fifo-depth = <0x100>;
942 max-frequency = <150000000>;
944 reset-names = "reset";
949 compatible = "rockchip,rk3328-gmac";
952 interrupt-names = "macirq";
957 clock-names = "stmmaceth", "mac_clk_rx",
962 reset-names = "stmmaceth";
964 tx-fifo-depth = <2048>;
965 rx-fifo-depth = <4096>;
971 compatible = "rockchip,rk3328-gmac";
975 interrupt-names = "macirq";
980 clock-names = "stmmaceth", "mac_clk_rx",
985 reset-names = "stmmaceth";
986 phy-mode = "rmii";
987 phy-handle = <&phy>;
988 tx-fifo-depth = <2048>;
989 rx-fifo-depth = <4096>;
995 compatible = "snps,dwmac-mdio";
996 #address-cells = <1>;
997 #size-cells = <0>;
999 phy: ethernet-phy@0 {
1000 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
1004 pinctrl-names = "default";
1005 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
1006 phy-is-integrated;
1012 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
1017 clock-names = "otg";
1019 g-np-tx-fifo-size = <16>;
1020 g-rx-fifo-size = <280>;
1021 g-tx-fifo-size = <256 128 128 64 32 16>;
1023 phy-names = "usb2-phy";
1028 compatible = "generic-ehci";
1033 phy-names = "usb";
1038 compatible = "generic-ohci";
1043 phy-names = "usb";
1048 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
1053 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1054 fifo-depth = <0x100>;
1055 max-frequency = <150000000>;
1057 reset-names = "reset";
1062 compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
1067 clock-names = "ref_clk", "suspend_clk",
1071 snps,dis-del-phy-power-chg-quirk;
1073 snps,dis-tx-ipgap-linecheck-quirk;
1074 snps,dis-u2-freeclk-exists-quirk;
1080 gic: interrupt-controller@ff811000 {
1081 compatible = "arm,gic-400";
1082 #interrupt-cells = <3>;
1083 #address-cells = <0>;
1084 interrupt-controller;
1094 compatible = "rockchip,rk3328-crypto";
1099 clock-names = "hclk_master", "hclk_slave", "sclk";
1101 reset-names = "crypto-rst";
1105 compatible = "rockchip,rk3328-pinctrl";
1107 #address-cells = <2>;
1108 #size-cells = <2>;
1112 compatible = "rockchip,gpio-bank";
1117 gpio-controller;
1118 #gpio-cells = <2>;
1120 interrupt-controller;
1121 #interrupt-cells = <2>;
1125 compatible = "rockchip,gpio-bank";
1130 gpio-controller;
1131 #gpio-cells = <2>;
1133 interrupt-controller;
1134 #interrupt-cells = <2>;
1138 compatible = "rockchip,gpio-bank";
1143 gpio-controller;
1144 #gpio-cells = <2>;
1146 interrupt-controller;
1147 #interrupt-cells = <2>;
1151 compatible = "rockchip,gpio-bank";
1156 gpio-controller;
1157 #gpio-cells = <2>;
1159 interrupt-controller;
1160 #interrupt-cells = <2>;
1163 pcfg_pull_up: pcfg-pull-up {
1164 bias-pull-up;
1167 pcfg_pull_down: pcfg-pull-down {
1168 bias-pull-down;
1171 pcfg_pull_none: pcfg-pull-none {
1172 bias-disable;
1175 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1176 bias-disable;
1177 drive-strength = <2>;
1180 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1181 bias-pull-up;
1182 drive-strength = <2>;
1185 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1186 bias-pull-up;
1187 drive-strength = <4>;
1190 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1191 bias-disable;
1192 drive-strength = <4>;
1195 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1196 bias-pull-down;
1197 drive-strength = <4>;
1200 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1201 bias-disable;
1202 drive-strength = <8>;
1205 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1206 bias-pull-up;
1207 drive-strength = <8>;
1210 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1211 bias-disable;
1212 drive-strength = <12>;
1215 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1216 bias-pull-up;
1217 drive-strength = <12>;
1220 pcfg_output_high: pcfg-output-high {
1221 output-high;
1224 pcfg_output_low: pcfg-output-low {
1225 output-low;
1228 pcfg_input_high: pcfg-input-high {
1229 bias-pull-up;
1230 input-enable;
1233 pcfg_input: pcfg-input {
1234 input-enable;
1238 i2c0_xfer: i2c0-xfer {
1245 i2c1_xfer: i2c1-xfer {
1252 i2c2_xfer: i2c2-xfer {
1259 i2c3_xfer: i2c3-xfer {
1263 i2c3_pins: i2c3-pins {
1271 hdmii2c_xfer: hdmii2c-xfer {
1277 pdm-0 {
1278 pdmm0_clk: pdmm0-clk {
1282 pdmm0_fsync: pdmm0-fsync {
1286 pdmm0_sdi0: pdmm0-sdi0 {
1290 pdmm0_sdi1: pdmm0-sdi1 {
1294 pdmm0_sdi2: pdmm0-sdi2 {
1298 pdmm0_sdi3: pdmm0-sdi3 {
1302 pdmm0_clk_sleep: pdmm0-clk-sleep {
1307 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1312 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1317 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1322 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1327 pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1333 tsadc {
1334 otp_pin: otp-pin {
1338 otp_out: otp-out {
1344 uart0_xfer: uart0-xfer {
1349 uart0_cts: uart0-cts {
1353 uart0_rts: uart0-rts {
1357 uart0_rts_pin: uart0-rts-pin {
1363 uart1_xfer: uart1-xfer {
1368 uart1_cts: uart1-cts {
1372 uart1_rts: uart1-rts {
1376 uart1_rts_pin: uart1-rts-pin {
1381 uart2-0 {
1382 uart2m0_xfer: uart2m0-xfer {
1388 uart2-1 {
1389 uart2m1_xfer: uart2m1-xfer {
1395 spi0-0 {
1396 spi0m0_clk: spi0m0-clk {
1400 spi0m0_cs0: spi0m0-cs0 {
1404 spi0m0_tx: spi0m0-tx {
1408 spi0m0_rx: spi0m0-rx {
1412 spi0m0_cs1: spi0m0-cs1 {
1417 spi0-1 {
1418 spi0m1_clk: spi0m1-clk {
1422 spi0m1_cs0: spi0m1-cs0 {
1426 spi0m1_tx: spi0m1-tx {
1430 spi0m1_rx: spi0m1-rx {
1434 spi0m1_cs1: spi0m1-cs1 {
1439 spi0-2 {
1440 spi0m2_clk: spi0m2-clk {
1444 spi0m2_cs0: spi0m2-cs0 {
1448 spi0m2_tx: spi0m2-tx {
1452 spi0m2_rx: spi0m2-rx {
1458 i2s1_mclk: i2s1-mclk {
1462 i2s1_sclk: i2s1-sclk {
1466 i2s1_lrckrx: i2s1-lrckrx {
1470 i2s1_lrcktx: i2s1-lrcktx {
1474 i2s1_sdi: i2s1-sdi {
1478 i2s1_sdo: i2s1-sdo {
1482 i2s1_sdio1: i2s1-sdio1 {
1486 i2s1_sdio2: i2s1-sdio2 {
1490 i2s1_sdio3: i2s1-sdio3 {
1494 i2s1_sleep: i2s1-sleep {
1508 i2s2-0 {
1509 i2s2m0_mclk: i2s2m0-mclk {
1513 i2s2m0_sclk: i2s2m0-sclk {
1517 i2s2m0_lrckrx: i2s2m0-lrckrx {
1521 i2s2m0_lrcktx: i2s2m0-lrcktx {
1525 i2s2m0_sdi: i2s2m0-sdi {
1529 i2s2m0_sdo: i2s2m0-sdo {
1533 i2s2m0_sleep: i2s2m0-sleep {
1544 i2s2-1 {
1545 i2s2m1_mclk: i2s2m1-mclk {
1549 i2s2m1_sclk: i2s2m1-sclk {
1553 i2s2m1_lrckrx: i2sm1-lrckrx {
1557 i2s2m1_lrcktx: i2s2m1-lrcktx {
1561 i2s2m1_sdi: i2s2m1-sdi {
1565 i2s2m1_sdo: i2s2m1-sdo {
1569 i2s2m1_sleep: i2s2m1-sleep {
1579 spdif-0 {
1580 spdifm0_tx: spdifm0-tx {
1585 spdif-1 {
1586 spdifm1_tx: spdifm1-tx {
1591 spdif-2 {
1592 spdifm2_tx: spdifm2-tx {
1597 sdmmc0-0 {
1598 sdmmc0m0_pwren: sdmmc0m0-pwren {
1602 sdmmc0m0_pin: sdmmc0m0-pin {
1607 sdmmc0-1 {
1608 sdmmc0m1_pwren: sdmmc0m1-pwren {
1612 sdmmc0m1_pin: sdmmc0m1-pin {
1618 sdmmc0_clk: sdmmc0-clk {
1622 sdmmc0_cmd: sdmmc0-cmd {
1626 sdmmc0_dectn: sdmmc0-dectn {
1630 sdmmc0_wrprt: sdmmc0-wrprt {
1634 sdmmc0_bus1: sdmmc0-bus1 {
1638 sdmmc0_bus4: sdmmc0-bus4 {
1645 sdmmc0_pins: sdmmc0-pins {
1659 sdmmc0ext_clk: sdmmc0ext-clk {
1663 sdmmc0ext_cmd: sdmmc0ext-cmd {
1667 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1671 sdmmc0ext_dectn: sdmmc0ext-dectn {
1675 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1679 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1687 sdmmc0ext_pins: sdmmc0ext-pins {
1701 sdmmc1_clk: sdmmc1-clk {
1705 sdmmc1_cmd: sdmmc1-cmd {
1709 sdmmc1_pwren: sdmmc1-pwren {
1713 sdmmc1_wrprt: sdmmc1-wrprt {
1717 sdmmc1_dectn: sdmmc1-dectn {
1721 sdmmc1_bus1: sdmmc1-bus1 {
1725 sdmmc1_bus4: sdmmc1-bus4 {
1732 sdmmc1_pins: sdmmc1-pins {
1747 emmc_clk: emmc-clk {
1751 emmc_cmd: emmc-cmd {
1755 emmc_pwren: emmc-pwren {
1759 emmc_rstnout: emmc-rstnout {
1763 emmc_bus1: emmc-bus1 {
1767 emmc_bus4: emmc-bus4 {
1775 emmc_bus8: emmc-bus8 {
1789 pwm0_pin: pwm0-pin {
1795 pwm1_pin: pwm1-pin {
1801 pwm2_pin: pwm2-pin {
1807 pwmir_pin: pwmir-pin {
1812 gmac-1 {
1813 rgmiim1_pins: rgmiim1-pins {
1862 rmiim1_pins: rmiim1-pins {
1901 fephyled_speed10: fephyled-speed10 {
1905 fephyled_duplex: fephyled-duplex {
1909 fephyled_rxm1: fephyled-rxm1 {
1913 fephyled_txm1: fephyled-txm1 {
1917 fephyled_linkm1: fephyled-linkm1 {
1923 tsadc_int: tsadc-int {
1926 tsadc_pin: tsadc-pin {
1932 hdmi_cec: hdmi-cec {
1936 hdmi_hpd: hdmi-hpd {
1941 cif-0 {
1942 dvp_d2d9_m0:dvp-d2d9-m0 {
1971 cif-1 {
1972 dvp_d2d9_m1:dvp-d2d9-m1 {