Lines Matching +full:otg +full:- +full:gp +full:- +full:pins
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3328-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <2>;
38 #size-cells = <0>;
42 compatible = "arm,cortex-a53";
45 #cooling-cells = <2>;
46 cpu-idle-states = <&CPU_SLEEP>;
47 dynamic-power-coefficient = <120>;
48 enable-method = "psci";
49 operating-points-v2 = <&cpu0_opp_table>;
50 i-cache-size = <0x8000>;
51 i-cache-line-size = <64>;
52 i-cache-sets = <256>;
53 d-cache-size = <0x8000>;
54 d-cache-line-size = <64>;
55 d-cache-sets = <128>;
56 next-level-cache = <&l2_cache>;
61 compatible = "arm,cortex-a53";
64 #cooling-cells = <2>;
65 cpu-idle-states = <&CPU_SLEEP>;
66 dynamic-power-coefficient = <120>;
67 enable-method = "psci";
68 operating-points-v2 = <&cpu0_opp_table>;
69 i-cache-size = <0x8000>;
70 i-cache-line-size = <64>;
71 i-cache-sets = <256>;
72 d-cache-size = <0x8000>;
73 d-cache-line-size = <64>;
74 d-cache-sets = <128>;
75 next-level-cache = <&l2_cache>;
80 compatible = "arm,cortex-a53";
83 #cooling-cells = <2>;
84 cpu-idle-states = <&CPU_SLEEP>;
85 dynamic-power-coefficient = <120>;
86 enable-method = "psci";
87 operating-points-v2 = <&cpu0_opp_table>;
88 i-cache-size = <0x8000>;
89 i-cache-line-size = <64>;
90 i-cache-sets = <256>;
91 d-cache-size = <0x8000>;
92 d-cache-line-size = <64>;
93 d-cache-sets = <128>;
94 next-level-cache = <&l2_cache>;
99 compatible = "arm,cortex-a53";
102 #cooling-cells = <2>;
103 cpu-idle-states = <&CPU_SLEEP>;
104 dynamic-power-coefficient = <120>;
105 enable-method = "psci";
106 operating-points-v2 = <&cpu0_opp_table>;
107 i-cache-size = <0x8000>;
108 i-cache-line-size = <64>;
109 i-cache-sets = <256>;
110 d-cache-size = <0x8000>;
111 d-cache-line-size = <64>;
112 d-cache-sets = <128>;
113 next-level-cache = <&l2_cache>;
116 idle-states {
117 entry-method = "psci";
119 CPU_SLEEP: cpu-sleep {
120 compatible = "arm,idle-state";
121 local-timer-stop;
122 arm,psci-suspend-param = <0x0010000>;
123 entry-latency-us = <120>;
124 exit-latency-us = <250>;
125 min-residency-us = <900>;
129 l2_cache: l2-cache {
131 cache-level = <2>;
132 cache-unified;
133 cache-size = <0x40000>;
134 cache-line-size = <64>;
135 cache-sets = <256>;
139 cpu0_opp_table: opp-table-0 {
140 compatible = "operating-points-v2";
141 opp-shared;
143 opp-408000000 {
144 opp-hz = /bits/ 64 <408000000>;
145 opp-microvolt = <950000>;
146 clock-latency-ns = <40000>;
147 opp-suspend;
149 opp-600000000 {
150 opp-hz = /bits/ 64 <600000000>;
151 opp-microvolt = <950000>;
152 clock-latency-ns = <40000>;
154 opp-816000000 {
155 opp-hz = /bits/ 64 <816000000>;
156 opp-microvolt = <1000000>;
157 clock-latency-ns = <40000>;
159 opp-1008000000 {
160 opp-hz = /bits/ 64 <1008000000>;
161 opp-microvolt = <1100000>;
162 clock-latency-ns = <40000>;
164 opp-1200000000 {
165 opp-hz = /bits/ 64 <1200000000>;
166 opp-microvolt = <1225000>;
167 clock-latency-ns = <40000>;
169 opp-1296000000 {
170 opp-hz = /bits/ 64 <1296000000>;
171 opp-microvolt = <1300000>;
172 clock-latency-ns = <40000>;
176 analog_sound: analog-sound {
177 compatible = "simple-audio-card";
178 simple-audio-card,format = "i2s";
179 simple-audio-card,mclk-fs = <256>;
180 simple-audio-card,name = "Analog";
183 simple-audio-card,cpu {
184 sound-dai = <&i2s1>;
187 simple-audio-card,codec {
188 sound-dai = <&codec>;
192 arm-pmu {
193 compatible = "arm,cortex-a53-pmu";
198 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
201 display_subsystem: display-subsystem {
202 compatible = "rockchip,display-subsystem";
206 hdmi_sound: hdmi-sound {
207 compatible = "simple-audio-card";
208 simple-audio-card,format = "i2s";
209 simple-audio-card,mclk-fs = <128>;
210 simple-audio-card,name = "HDMI";
213 simple-audio-card,cpu {
214 sound-dai = <&i2s0>;
217 simple-audio-card,codec {
218 sound-dai = <&hdmi>;
223 compatible = "arm,psci-1.0", "arm,psci-0.2";
228 compatible = "arm,armv8-timer";
236 compatible = "fixed-clock";
237 #clock-cells = <0>;
238 clock-frequency = <24000000>;
239 clock-output-names = "xin24m";
243 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
247 clock-names = "i2s_clk", "i2s_hclk";
249 dma-names = "tx", "rx";
250 #sound-dai-cells = <0>;
255 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
259 clock-names = "i2s_clk", "i2s_hclk";
261 dma-names = "tx", "rx";
262 #sound-dai-cells = <0>;
267 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
271 clock-names = "i2s_clk", "i2s_hclk";
273 dma-names = "tx", "rx";
274 #sound-dai-cells = <0>;
279 compatible = "rockchip,rk3328-spdif";
283 clock-names = "mclk", "hclk";
285 dma-names = "tx";
286 pinctrl-names = "default";
287 pinctrl-0 = <&spdifm2_tx>;
288 #sound-dai-cells = <0>;
296 clock-names = "pdm_clk", "pdm_hclk";
298 dma-names = "rx";
299 pinctrl-names = "default", "sleep";
300 pinctrl-0 = <&pdmm0_clk
305 pinctrl-1 = <&pdmm0_clk_sleep
314 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
317 io_domains: io-domains {
318 compatible = "rockchip,rk3328-io-voltage-domain";
323 compatible = "rockchip,rk3328-grf-gpio";
324 gpio-controller;
325 #gpio-cells = <2>;
328 power: power-controller {
329 compatible = "rockchip,rk3328-power-controller";
330 #power-domain-cells = <1>;
331 #address-cells = <1>;
332 #size-cells = <0>;
334 power-domain@RK3328_PD_HEVC {
336 #power-domain-cells = <0>;
338 power-domain@RK3328_PD_VIDEO {
344 #power-domain-cells = <0>;
346 power-domain@RK3328_PD_VPU {
349 #power-domain-cells = <0>;
353 reboot-mode {
354 compatible = "syscon-reboot-mode";
356 mode-normal = <BOOT_NORMAL>;
357 mode-recovery = <BOOT_RECOVERY>;
358 mode-bootloader = <BOOT_FASTBOOT>;
359 mode-loader = <BOOT_BL_DOWNLOAD>;
364 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
368 clock-names = "baudclk", "apb_pclk";
370 dma-names = "tx", "rx";
371 pinctrl-names = "default";
372 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
373 reg-io-width = <4>;
374 reg-shift = <2>;
379 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
383 clock-names = "baudclk", "apb_pclk";
385 dma-names = "tx", "rx";
386 pinctrl-names = "default";
387 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
388 reg-io-width = <4>;
389 reg-shift = <2>;
394 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
398 clock-names = "baudclk", "apb_pclk";
400 dma-names = "tx", "rx";
401 pinctrl-names = "default";
402 pinctrl-0 = <&uart2m1_xfer>;
403 reg-io-width = <4>;
404 reg-shift = <2>;
409 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
412 #address-cells = <1>;
413 #size-cells = <0>;
415 clock-names = "i2c", "pclk";
416 pinctrl-names = "default";
417 pinctrl-0 = <&i2c0_xfer>;
422 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
425 #address-cells = <1>;
426 #size-cells = <0>;
428 clock-names = "i2c", "pclk";
429 pinctrl-names = "default";
430 pinctrl-0 = <&i2c1_xfer>;
435 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
438 #address-cells = <1>;
439 #size-cells = <0>;
441 clock-names = "i2c", "pclk";
442 pinctrl-names = "default";
443 pinctrl-0 = <&i2c2_xfer>;
448 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
451 #address-cells = <1>;
452 #size-cells = <0>;
454 clock-names = "i2c", "pclk";
455 pinctrl-names = "default";
456 pinctrl-0 = <&i2c3_xfer>;
461 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
464 #address-cells = <1>;
465 #size-cells = <0>;
467 clock-names = "spiclk", "apb_pclk";
469 dma-names = "tx", "rx";
470 pinctrl-names = "default";
471 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
476 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt";
483 compatible = "rockchip,rk3328-pwm";
486 clock-names = "pwm", "pclk";
487 pinctrl-names = "default";
488 pinctrl-0 = <&pwm0_pin>;
489 #pwm-cells = <3>;
494 compatible = "rockchip,rk3328-pwm";
497 clock-names = "pwm", "pclk";
498 pinctrl-names = "default";
499 pinctrl-0 = <&pwm1_pin>;
500 #pwm-cells = <3>;
505 compatible = "rockchip,rk3328-pwm";
508 clock-names = "pwm", "pclk";
509 pinctrl-names = "default";
510 pinctrl-0 = <&pwm2_pin>;
511 #pwm-cells = <3>;
516 compatible = "rockchip,rk3328-pwm";
519 clock-names = "pwm", "pclk";
520 pinctrl-names = "default";
521 pinctrl-0 = <&pwmir_pin>;
522 #pwm-cells = <3>;
526 dmac: dma-controller@ff1f0000 {
531 arm,pl330-periph-burst;
533 clock-names = "apb_pclk";
534 #dma-cells = <1>;
537 thermal-zones {
538 soc_thermal: soc-thermal {
539 polling-delay-passive = <20>;
540 polling-delay = <1000>;
541 sustainable-power = <1000>;
543 thermal-sensors = <&tsadc 0>;
546 threshold: trip-point0 {
551 target: trip-point1 {
556 soc_crit: soc-crit {
563 cooling-maps {
566 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
578 compatible = "rockchip,rk3328-tsadc";
581 assigned-clocks = <&cru SCLK_TSADC>;
582 assigned-clock-rates = <50000>;
584 clock-names = "tsadc", "apb_pclk";
585 pinctrl-names = "init", "default", "sleep";
586 pinctrl-0 = <&otp_pin>;
587 pinctrl-1 = <&otp_out>;
588 pinctrl-2 = <&otp_pin>;
590 reset-names = "tsadc-apb";
592 rockchip,hw-tshut-temp = <100000>;
593 #thermal-sensor-cells = <1>;
598 compatible = "rockchip,rk3328-efuse";
600 #address-cells = <1>;
601 #size-cells = <1>;
603 clock-names = "pclk_efuse";
604 rockchip,efuse-size = <0x20>;
610 cpu_leakage: cpu-leakage@17 {
613 logic_leakage: logic-leakage@19 {
616 efuse_cpu_version: cpu-version@1a {
623 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
626 #io-channel-cells = <1>;
628 clock-names = "saradc", "apb_pclk";
630 reset-names = "saradc-apb";
635 compatible = "rockchip,rk3328-mali", "arm,mali-450";
644 interrupt-names = "gp",
652 clock-names = "bus", "core";
661 clock-names = "aclk", "iface";
662 #iommu-cells = <0>;
671 clock-names = "aclk", "iface";
672 #iommu-cells = <0>;
676 vpu: video-codec@ff350000 {
677 compatible = "rockchip,rk3328-vpu";
680 interrupt-names = "vdpu";
682 clock-names = "aclk", "hclk";
684 power-domains = <&power RK3328_PD_VPU>;
692 clock-names = "aclk", "iface";
693 #iommu-cells = <0>;
694 power-domains = <&power RK3328_PD_VPU>;
697 vdec: video-codec@ff360000 {
698 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
703 clock-names = "axi", "ahb", "cabac", "core";
704 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
706 assigned-clock-rates = <400000000>, <400000000>, <300000000>;
708 power-domains = <&power RK3328_PD_VIDEO>;
716 clock-names = "aclk", "iface";
717 #iommu-cells = <0>;
718 power-domains = <&power RK3328_PD_VIDEO>;
722 compatible = "rockchip,rk3328-vop";
726 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
728 reset-names = "axi", "ahb", "dclk";
733 #address-cells = <1>;
734 #size-cells = <0>;
738 remote-endpoint = <&hdmi_in_vop>;
748 clock-names = "aclk", "iface";
749 #iommu-cells = <0>;
754 compatible = "rockchip,rk3328-dw-hdmi";
756 reg-io-width = <4>;
761 clock-names = "iahb",
765 phy-names = "hdmi";
766 pinctrl-names = "default";
767 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
769 #sound-dai-cells = <0>;
773 #address-cells = <1>;
774 #size-cells = <0>;
780 remote-endpoint = <&vop_out_hdmi>;
791 compatible = "rockchip,rk3328-codec";
794 clock-names = "pclk", "mclk";
796 #sound-dai-cells = <0>;
801 compatible = "rockchip,rk3328-hdmi-phy";
805 clock-names = "sysclk", "refoclk", "refpclk";
806 clock-output-names = "hdmi_phy";
807 #clock-cells = <0>;
808 nvmem-cells = <&efuse_cpu_version>;
809 nvmem-cell-names = "cpu-version";
810 #phy-cells = <0>;
814 cru: clock-controller@ff440000 {
815 compatible = "rockchip,rk3328-cru";
818 clock-names = "xin24m";
820 #clock-cells = <1>;
821 #reset-cells = <1>;
822 assigned-clocks =
845 assigned-clock-parents =
849 assigned-clock-rates =
869 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
870 "simple-mfd";
872 #address-cells = <1>;
873 #size-cells = <1>;
876 compatible = "rockchip,rk3328-usb2phy";
879 clock-names = "phyclk";
880 clock-output-names = "usb480m_phy";
881 #clock-cells = <0>;
882 assigned-clocks = <&cru USB480M>;
883 assigned-clock-parents = <&u2phy>;
886 u2phy_otg: otg-port {
887 #phy-cells = <0>;
891 interrupt-names = "otg-bvalid", "otg-id",
896 u2phy_host: host-port {
897 #phy-cells = <0>;
899 interrupt-names = "linestate";
906 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
911 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
912 fifo-depth = <0x100>;
913 max-frequency = <150000000>;
915 reset-names = "reset";
920 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
925 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
926 fifo-depth = <0x100>;
927 max-frequency = <150000000>;
929 reset-names = "reset";
934 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
939 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
940 fifo-depth = <0x100>;
941 max-frequency = <150000000>;
943 reset-names = "reset";
948 compatible = "rockchip,rk3328-gmac";
951 interrupt-names = "macirq";
956 clock-names = "stmmaceth", "mac_clk_rx",
961 reset-names = "stmmaceth";
963 tx-fifo-depth = <2048>;
964 rx-fifo-depth = <4096>;
970 compatible = "rockchip,rk3328-gmac";
974 interrupt-names = "macirq";
979 clock-names = "stmmaceth", "mac_clk_rx",
984 reset-names = "stmmaceth";
985 phy-mode = "rmii";
986 phy-handle = <&phy>;
987 tx-fifo-depth = <2048>;
988 rx-fifo-depth = <4096>;
994 compatible = "snps,dwmac-mdio";
995 #address-cells = <1>;
996 #size-cells = <0>;
998 phy: ethernet-phy@0 {
999 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
1003 pinctrl-names = "default";
1004 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
1005 phy-is-integrated;
1011 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
1016 clock-names = "otg";
1017 dr_mode = "otg";
1018 g-np-tx-fifo-size = <16>;
1019 g-rx-fifo-size = <280>;
1020 g-tx-fifo-size = <256 128 128 64 32 16>;
1022 phy-names = "usb2-phy";
1027 compatible = "generic-ehci";
1032 phy-names = "usb";
1037 compatible = "generic-ohci";
1042 phy-names = "usb";
1047 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
1052 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1053 fifo-depth = <0x100>;
1054 max-frequency = <150000000>;
1056 reset-names = "reset";
1061 compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
1066 clock-names = "ref_clk", "suspend_clk",
1068 dr_mode = "otg";
1070 snps,dis-del-phy-power-chg-quirk;
1072 snps,dis-tx-ipgap-linecheck-quirk;
1073 snps,dis-u2-freeclk-exists-quirk;
1079 gic: interrupt-controller@ff811000 {
1080 compatible = "arm,gic-400";
1081 #interrupt-cells = <3>;
1082 #address-cells = <0>;
1083 interrupt-controller;
1093 compatible = "rockchip,rk3328-crypto";
1098 clock-names = "hclk_master", "hclk_slave", "sclk";
1100 reset-names = "crypto-rst";
1104 compatible = "rockchip,rk3328-pinctrl";
1106 #address-cells = <2>;
1107 #size-cells = <2>;
1111 compatible = "rockchip,gpio-bank";
1116 gpio-controller;
1117 #gpio-cells = <2>;
1119 interrupt-controller;
1120 #interrupt-cells = <2>;
1124 compatible = "rockchip,gpio-bank";
1129 gpio-controller;
1130 #gpio-cells = <2>;
1132 interrupt-controller;
1133 #interrupt-cells = <2>;
1137 compatible = "rockchip,gpio-bank";
1142 gpio-controller;
1143 #gpio-cells = <2>;
1145 interrupt-controller;
1146 #interrupt-cells = <2>;
1150 compatible = "rockchip,gpio-bank";
1155 gpio-controller;
1156 #gpio-cells = <2>;
1158 interrupt-controller;
1159 #interrupt-cells = <2>;
1162 pcfg_pull_up: pcfg-pull-up {
1163 bias-pull-up;
1166 pcfg_pull_down: pcfg-pull-down {
1167 bias-pull-down;
1170 pcfg_pull_none: pcfg-pull-none {
1171 bias-disable;
1174 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1175 bias-disable;
1176 drive-strength = <2>;
1179 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1180 bias-pull-up;
1181 drive-strength = <2>;
1184 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1185 bias-pull-up;
1186 drive-strength = <4>;
1189 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1190 bias-disable;
1191 drive-strength = <4>;
1194 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1195 bias-pull-down;
1196 drive-strength = <4>;
1199 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1200 bias-disable;
1201 drive-strength = <8>;
1204 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1205 bias-pull-up;
1206 drive-strength = <8>;
1209 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1210 bias-disable;
1211 drive-strength = <12>;
1214 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1215 bias-pull-up;
1216 drive-strength = <12>;
1219 pcfg_output_high: pcfg-output-high {
1220 output-high;
1223 pcfg_output_low: pcfg-output-low {
1224 output-low;
1227 pcfg_input_high: pcfg-input-high {
1228 bias-pull-up;
1229 input-enable;
1232 pcfg_input: pcfg-input {
1233 input-enable;
1237 i2c0_xfer: i2c0-xfer {
1238 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
1244 i2c1_xfer: i2c1-xfer {
1245 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
1251 i2c2_xfer: i2c2-xfer {
1252 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
1258 i2c3_xfer: i2c3-xfer {
1259 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1262 i2c3_pins: i2c3-pins {
1263 rockchip,pins =
1270 hdmii2c_xfer: hdmii2c-xfer {
1271 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1276 pdm-0 {
1277 pdmm0_clk: pdmm0-clk {
1278 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1281 pdmm0_fsync: pdmm0-fsync {
1282 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1285 pdmm0_sdi0: pdmm0-sdi0 {
1286 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1289 pdmm0_sdi1: pdmm0-sdi1 {
1290 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1293 pdmm0_sdi2: pdmm0-sdi2 {
1294 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1297 pdmm0_sdi3: pdmm0-sdi3 {
1298 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1301 pdmm0_clk_sleep: pdmm0-clk-sleep {
1302 rockchip,pins =
1306 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1307 rockchip,pins =
1311 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1312 rockchip,pins =
1316 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1317 rockchip,pins =
1321 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1322 rockchip,pins =
1326 pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1327 rockchip,pins =
1333 otp_pin: otp-pin {
1334 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1337 otp_out: otp-out {
1338 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1343 uart0_xfer: uart0-xfer {
1344 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1348 uart0_cts: uart0-cts {
1349 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1352 uart0_rts: uart0-rts {
1353 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1356 uart0_rts_pin: uart0-rts-pin {
1357 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1362 uart1_xfer: uart1-xfer {
1363 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>,
1367 uart1_cts: uart1-cts {
1368 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1371 uart1_rts: uart1-rts {
1372 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1375 uart1_rts_pin: uart1-rts-pin {
1376 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1380 uart2-0 {
1381 uart2m0_xfer: uart2m0-xfer {
1382 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>,
1387 uart2-1 {
1388 uart2m1_xfer: uart2m1-xfer {
1389 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
1394 spi0-0 {
1395 spi0m0_clk: spi0m0-clk {
1396 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1399 spi0m0_cs0: spi0m0-cs0 {
1400 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1403 spi0m0_tx: spi0m0-tx {
1404 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1407 spi0m0_rx: spi0m0-rx {
1408 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1411 spi0m0_cs1: spi0m0-cs1 {
1412 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1416 spi0-1 {
1417 spi0m1_clk: spi0m1-clk {
1418 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1421 spi0m1_cs0: spi0m1-cs0 {
1422 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1425 spi0m1_tx: spi0m1-tx {
1426 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1429 spi0m1_rx: spi0m1-rx {
1430 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1433 spi0m1_cs1: spi0m1-cs1 {
1434 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1438 spi0-2 {
1439 spi0m2_clk: spi0m2-clk {
1440 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1443 spi0m2_cs0: spi0m2-cs0 {
1444 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1447 spi0m2_tx: spi0m2-tx {
1448 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1451 spi0m2_rx: spi0m2-rx {
1452 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1457 i2s1_mclk: i2s1-mclk {
1458 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1461 i2s1_sclk: i2s1-sclk {
1462 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1465 i2s1_lrckrx: i2s1-lrckrx {
1466 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1469 i2s1_lrcktx: i2s1-lrcktx {
1470 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1473 i2s1_sdi: i2s1-sdi {
1474 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1477 i2s1_sdo: i2s1-sdo {
1478 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1481 i2s1_sdio1: i2s1-sdio1 {
1482 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1485 i2s1_sdio2: i2s1-sdio2 {
1486 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1489 i2s1_sdio3: i2s1-sdio3 {
1490 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1493 i2s1_sleep: i2s1-sleep {
1494 rockchip,pins =
1507 i2s2-0 {
1508 i2s2m0_mclk: i2s2m0-mclk {
1509 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1512 i2s2m0_sclk: i2s2m0-sclk {
1513 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1516 i2s2m0_lrckrx: i2s2m0-lrckrx {
1517 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1520 i2s2m0_lrcktx: i2s2m0-lrcktx {
1521 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1524 i2s2m0_sdi: i2s2m0-sdi {
1525 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1528 i2s2m0_sdo: i2s2m0-sdo {
1529 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1532 i2s2m0_sleep: i2s2m0-sleep {
1533 rockchip,pins =
1543 i2s2-1 {
1544 i2s2m1_mclk: i2s2m1-mclk {
1545 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1548 i2s2m1_sclk: i2s2m1-sclk {
1549 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1552 i2s2m1_lrckrx: i2sm1-lrckrx {
1553 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1556 i2s2m1_lrcktx: i2s2m1-lrcktx {
1557 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1560 i2s2m1_sdi: i2s2m1-sdi {
1561 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1564 i2s2m1_sdo: i2s2m1-sdo {
1565 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1568 i2s2m1_sleep: i2s2m1-sleep {
1569 rockchip,pins =
1578 spdif-0 {
1579 spdifm0_tx: spdifm0-tx {
1580 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1584 spdif-1 {
1585 spdifm1_tx: spdifm1-tx {
1586 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1590 spdif-2 {
1591 spdifm2_tx: spdifm2-tx {
1592 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1596 sdmmc0-0 {
1597 sdmmc0m0_pwren: sdmmc0m0-pwren {
1598 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1601 sdmmc0m0_pin: sdmmc0m0-pin {
1602 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1606 sdmmc0-1 {
1607 sdmmc0m1_pwren: sdmmc0m1-pwren {
1608 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1611 sdmmc0m1_pin: sdmmc0m1-pin {
1612 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1617 sdmmc0_clk: sdmmc0-clk {
1618 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
1621 sdmmc0_cmd: sdmmc0-cmd {
1622 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
1625 sdmmc0_dectn: sdmmc0-dectn {
1626 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1629 sdmmc0_wrprt: sdmmc0-wrprt {
1630 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1633 sdmmc0_bus1: sdmmc0-bus1 {
1634 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
1637 sdmmc0_bus4: sdmmc0-bus4 {
1638 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
1644 sdmmc0_pins: sdmmc0-pins {
1645 rockchip,pins =
1658 sdmmc0ext_clk: sdmmc0ext-clk {
1659 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1662 sdmmc0ext_cmd: sdmmc0ext-cmd {
1663 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1666 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1667 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1670 sdmmc0ext_dectn: sdmmc0ext-dectn {
1671 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1674 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1675 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1678 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1679 rockchip,pins =
1686 sdmmc0ext_pins: sdmmc0ext-pins {
1687 rockchip,pins =
1700 sdmmc1_clk: sdmmc1-clk {
1701 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1704 sdmmc1_cmd: sdmmc1-cmd {
1705 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1708 sdmmc1_pwren: sdmmc1-pwren {
1709 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1712 sdmmc1_wrprt: sdmmc1-wrprt {
1713 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1716 sdmmc1_dectn: sdmmc1-dectn {
1717 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1720 sdmmc1_bus1: sdmmc1-bus1 {
1721 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1724 sdmmc1_bus4: sdmmc1-bus4 {
1725 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1731 sdmmc1_pins: sdmmc1-pins {
1732 rockchip,pins =
1746 emmc_clk: emmc-clk {
1747 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1750 emmc_cmd: emmc-cmd {
1751 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1754 emmc_pwren: emmc-pwren {
1755 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1758 emmc_rstnout: emmc-rstnout {
1759 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1762 emmc_bus1: emmc-bus1 {
1763 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1766 emmc_bus4: emmc-bus4 {
1767 rockchip,pins =
1774 emmc_bus8: emmc-bus8 {
1775 rockchip,pins =
1788 pwm0_pin: pwm0-pin {
1789 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1794 pwm1_pin: pwm1-pin {
1795 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1800 pwm2_pin: pwm2-pin {
1801 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1806 pwmir_pin: pwmir-pin {
1807 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1811 gmac-1 {
1812 rgmiim1_pins: rgmiim1-pins {
1813 rockchip,pins =
1861 rmiim1_pins: rmiim1-pins {
1862 rockchip,pins =
1900 fephyled_speed10: fephyled-speed10 {
1901 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1904 fephyled_duplex: fephyled-duplex {
1905 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1908 fephyled_rxm1: fephyled-rxm1 {
1909 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1912 fephyled_txm1: fephyled-txm1 {
1913 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1916 fephyled_linkm1: fephyled-linkm1 {
1917 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1922 tsadc_int: tsadc-int {
1923 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1925 tsadc_pin: tsadc-pin {
1926 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1931 hdmi_cec: hdmi-cec {
1932 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1935 hdmi_hpd: hdmi-hpd {
1936 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1940 cif-0 {
1941 dvp_d2d9_m0:dvp-d2d9-m0 {
1942 rockchip,pins =
1970 cif-1 {
1971 dvp_d2d9_m1:dvp-d2d9-m1 {
1972 rockchip,pins =